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ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks 

PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This commit is contained in:
Fabio Estevam 2014-08-19 15:21:12 -03:00 committed by Shawn Guo
parent bad66c3ebd
commit 0783a56087
1 changed files with 7 additions and 0 deletions
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7
arch/arm/mach-imx/clk-imx6sl.c
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@ -376,6 +376,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Audio-related clocks configuration */
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
/* set PLL5 video as lcdif pix parent clock */
clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
clks[IMX6SL_CLK_PLL2_PFD2]);
/* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED);
}