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arm64: Introduce raw_{d,i}cache_line_size 

On systems with mismatched i/d cache min line sizes, we need to use
the smallest size possible across all CPUs. This will be done by fetching
the system wide safe value from CPU feature infrastructure.
However the some special users(e.g kexec, hibernate) would need the line
size on the CPU (rather than the system wide), when either the system
wide feature may not be accessible or it is guranteed that the caller
executes with a gurantee of no migration.
Provide another helper which will fetch cache line size on the current CPU.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: James Morse <james.morse@arm.com>
Reviewed-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Suzuki K Poulose 2016-09-09 14:07:14 +01:00 committed by Will Deacon
parent c831b2ae25
commit 072f0a6338
3 changed files with 22 additions and 6 deletions
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24
arch/arm64/include/asm/assembler.h
View File

@ -218,9 +218,10 @@ lr .req x30 // link register
.endm .endm
/* /*
* dcache_line_size - get the minimum D-cache line size from the CTR register. * raw_dcache_line_size - get the minimum D-cache line size on this CPU
* from the CTR register.
*/ */
.macro dcache_line_size, reg, tmp .macro raw_dcache_line_size, reg, tmp
mrs \tmp, ctr_el0 // read CTR mrs \tmp, ctr_el0 // read CTR
ubfm \tmp, \tmp, #16, #19 // cache line size encoding ubfm \tmp, \tmp, #16, #19 // cache line size encoding
mov \reg, #4 // bytes per word mov \reg, #4 // bytes per word
@ -228,15 +229,30 @@ lr .req x30 // link register
.endm .endm
/* /*
* icache_line_size - get the minimum I-cache line size from the CTR register. * dcache_line_size - get the safe D-cache line size across all CPUs
*/ */
.macro icache_line_size, reg, tmp .macro dcache_line_size, reg, tmp
raw_dcache_line_size \reg, \tmp
.endm
/*
* raw_icache_line_size - get the minimum I-cache line size on this CPU
* from the CTR register.
*/
.macro raw_icache_line_size, reg, tmp
mrs \tmp, ctr_el0 // read CTR mrs \tmp, ctr_el0 // read CTR
and \tmp, \tmp, #0xf // cache line size encoding and \tmp, \tmp, #0xf // cache line size encoding
mov \reg, #4 // bytes per word mov \reg, #4 // bytes per word
lsl \reg, \reg, \tmp // actual cache line size lsl \reg, \reg, \tmp // actual cache line size
.endm .endm
/*
* icache_line_size - get the safe I-cache line size across all CPUs
*/
.macro icache_line_size, reg, tmp
raw_icache_line_size \reg, \tmp
.endm
/* /*
* tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
*/ */

2
arch/arm64/kernel/hibernate-asm.S
View File

@ -96,7 +96,7 @@ ENTRY(swsusp_arch_suspend_exit)
add x1, x10, #PAGE_SIZE add x1, x10, #PAGE_SIZE
/* Clean the copied page to PoU - based on flush_icache_range() */ /* Clean the copied page to PoU - based on flush_icache_range() */
dcache_line_size x2, x3 raw_dcache_line_size x2, x3
sub x3, x2, #1 sub x3, x2, #1
bic x4, x10, x3 bic x4, x10, x3
2: dc cvau, x4 /* clean D line / unified line */ 2: dc cvau, x4 /* clean D line / unified line */

2
arch/arm64/kernel/relocate_kernel.S
View File

@ -34,7 +34,7 @@ ENTRY(arm64_relocate_new_kernel)
/* Setup the list loop variables. */ /* Setup the list loop variables. */
mov x17, x1 /* x17 = kimage_start */ mov x17, x1 /* x17 = kimage_start */
mov x16, x0 /* x16 = kimage_head */ mov x16, x0 /* x16 = kimage_head */
dcache_line_size x15, x0 /* x15 = dcache line size */ raw_dcache_line_size x15, x0 /* x15 = dcache line size */
mov x14, xzr /* x14 = entry ptr */ mov x14, xzr /* x14 = entry ptr */
mov x13, xzr /* x13 = copy dest */ mov x13, xzr /* x13 = copy dest */