mmc: sh_mobile_sdhi: Add tuning support
Add tuning support for use with SDR104 mode This includes adding support for the sampling clock controller (SCC). Based on work by Ai Kyuse. Cc: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Simon Horman
Ulf Hansson
parent
4f11997773
commit
06f438dd38
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@ -47,6 +47,11 @@
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#define host_to_priv(host) container_of((host)->pdata, struct sh_mobile_sdhi, mmc_data)
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struct sh_mobile_sdhi_scc {
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unsigned long clk_rate; /* clock rate for SDR104 */
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u32 tap; /* sampling clock position for SDR104 */
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};
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struct sh_mobile_sdhi_of_data {
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unsigned long tmio_flags;
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u32 tmio_ocr_mask;
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@ -55,6 +60,9 @@ struct sh_mobile_sdhi_of_data {
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enum dma_slave_buswidth dma_buswidth;
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dma_addr_t dma_rx_offset;
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unsigned bus_shift;
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int scc_offset;
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struct sh_mobile_sdhi_scc *taps;
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int taps_num;
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};
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static const struct sh_mobile_sdhi_of_data of_default_cfg = {
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@ -73,12 +81,35 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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};
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/* Definitions for sampling clocks */
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static struct sh_mobile_sdhi_scc rcar_gen2_scc_taps[] = {
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{
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.clk_rate = 156000000,
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.tap = 0x00000703,
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},
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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},
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};
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static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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.dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.dma_rx_offset = 0x2000,
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.scc_offset = 0x0300,
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.taps = rcar_gen2_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
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};
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/* Definitions for sampling clocks */
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static struct sh_mobile_sdhi_scc rcar_gen3_scc_taps[] = {
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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},
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};
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static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
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@ -86,6 +117,9 @@ static const struct sh_mobile_sdhi_of_data of_rcar_gen3_compatible = {
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TMIO_MMC_CLK_ACTUAL | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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};
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static const struct of_device_id sh_mobile_sdhi_of_match[] = {
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@ -113,6 +147,7 @@ struct sh_mobile_sdhi {
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struct tmio_mmc_dma dma_priv;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default, *pins_uhs;
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void __iomem *scc_ctl;
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};
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static void sh_mobile_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
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@ -263,6 +298,201 @@ static int sh_mobile_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
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return pinctrl_select_state(priv->pinctrl, pin_state);
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}
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/* SCC registers */
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#define SH_MOBILE_SDHI_SCC_DTCNTL 0x000
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#define SH_MOBILE_SDHI_SCC_TAPSET 0x002
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#define SH_MOBILE_SDHI_SCC_DT2FF 0x004
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#define SH_MOBILE_SDHI_SCC_CKSEL 0x006
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#define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008
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#define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A
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/* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0)
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
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#define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
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/* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
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#define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
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#define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
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/* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
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#define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2)
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static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
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struct sh_mobile_sdhi *priv, int addr)
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{
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return readl(priv->scc_ctl + (addr << host->bus_shift));
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}
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static inline void sd_scc_write32(struct tmio_mmc_host *host,
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struct sh_mobile_sdhi *priv,
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int addr, u32 val)
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{
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writel(val, priv->scc_ctl + (addr << host->bus_shift));
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}
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static unsigned int sh_mobile_sdhi_init_tuning(struct tmio_mmc_host *host)
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{
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struct sh_mobile_sdhi *priv;
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if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
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return 0;
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priv = host_to_priv(host);
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/* set sampling clock selection range */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
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/* Initialize SCC */
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sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, host->scc_tappos);
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/* Read TAPNUM */
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return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
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SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
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}
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static void sh_mobile_sdhi_prepare_tuning(struct tmio_mmc_host *host,
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unsigned long tap)
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{
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struct sh_mobile_sdhi *priv = host_to_priv(host);
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/* Set sampling clock position */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
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}
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#define SH_MOBILE_SDHI_MAX_TAP 3
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static int sh_mobile_sdhi_select_tuning(struct tmio_mmc_host *host)
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{
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struct sh_mobile_sdhi *priv = host_to_priv(host);
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unsigned long tap_cnt; /* counter of tuning success */
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unsigned long tap_set; /* tap position */
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unsigned long tap_start;/* start position of tuning success */
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unsigned long tap_end; /* end position of tuning success */
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unsigned long ntap; /* temporary counter of tuning success */
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unsigned long i;
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/* Clear SCC_RVSREQ */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
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/*
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* Find the longest consecutive run of successful probes. If that
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* is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
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* center index as the tap.
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*/
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tap_cnt = 0;
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ntap = 0;
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tap_start = 0;
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tap_end = 0;
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for (i = 0; i < host->tap_num * 2; i++) {
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if (test_bit(i, host->taps))
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ntap++;
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else {
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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ntap = 0;
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}
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}
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
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tap_set = (tap_start + tap_end) / 2 % host->tap_num;
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else
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return -EIO;
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/* Set SCC */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap_set);
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/* Enable auto re-tuning */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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return 0;
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}
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static bool sh_mobile_sdhi_check_scc_error(struct tmio_mmc_host *host)
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{
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struct sh_mobile_sdhi *priv;
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if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
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return 0;
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priv = host_to_priv(host);
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/* Check SCC error */
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if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
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SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
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SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
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/* Clear SCC error */
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
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return true;
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}
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return false;
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}
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static void sh_mobile_sdhi_hw_reset(struct tmio_mmc_host *host)
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{
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struct sh_mobile_sdhi *priv;
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if (!(host->mmc->caps & MMC_CAP_UHS_SDR104))
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return;
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priv = host_to_priv(host);
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/* Reset SCC */
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
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~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
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~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
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sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
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}
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static int sh_mobile_sdhi_wait_idle(struct tmio_mmc_host *host)
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{
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int timeout = 1000;
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@ -333,7 +563,7 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
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struct tmio_mmc_data *mmd = pdev->dev.platform_data;
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struct tmio_mmc_host *host;
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struct resource *res;
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int irq, ret, i = 0;
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int irq, ret, i;
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struct tmio_mmc_dma *dma_priv;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -393,6 +623,11 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
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host->card_busy = sh_mobile_sdhi_card_busy;
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host->start_signal_voltage_switch =
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sh_mobile_sdhi_start_signal_voltage_switch;
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host->init_tuning = sh_mobile_sdhi_init_tuning;
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host->prepare_tuning = sh_mobile_sdhi_prepare_tuning;
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host->select_tuning = sh_mobile_sdhi_select_tuning;
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host->check_scc_error = sh_mobile_sdhi_check_scc_error;
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host->hw_reset = sh_mobile_sdhi_hw_reset;
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}
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/* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
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@ -433,6 +668,34 @@ static int sh_mobile_sdhi_probe(struct platform_device *pdev)
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if (ret < 0)
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goto efree;
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if (host->mmc->caps & MMC_CAP_UHS_SDR104) {
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host->mmc->caps |= MMC_CAP_HW_RESET;
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if (of_id && of_id->data) {
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const struct sh_mobile_sdhi_of_data *of_data;
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const struct sh_mobile_sdhi_scc *taps;
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bool hit = false;
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of_data = of_id->data;
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taps = of_data->taps;
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for (i = 0; i < of_data->taps_num; i++) {
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if (taps[i].clk_rate == 0 ||
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taps[i].clk_rate == host->mmc->f_max) {
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host->scc_tappos = taps->tap;
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hit = true;
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break;
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}
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}
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if (!hit)
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dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
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priv->scc_ctl = host->ctl + of_data->scc_offset;
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}
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}
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i = 0;
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while (1) {
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irq = platform_get_irq(pdev, i);
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if (irq < 0)
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