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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc 

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (49 commits)
  powerpc: Fix build bug with binutils < 2.18 and GCC < 4.2
  powerpc/eeh: Don't panic when EEH_MAX_FAILS is exceeded
  fbdev: Teaches offb about palette on radeon r5xx/r6xx
  powerpc/cell/edac: Log a syndrome code in case of correctable error
  powerpc/cell: Add DMA_ATTR_WEAK_ORDERING dma attribute and use in Cell IOMMU code
  powerpc: Indicate which oprofile counters to use while in compat mode
  powerpc/boot: Change spaces to tabs
  powerpc: Remove duplicate 6xx option in Kconfig
  powerpc: Use PPC_LONG and PPC_LONG_ALIGN in lib/string.S
  powerpc: Use PPC_LONG_ALIGN in uaccess.h
  powerpc: Add a #define for aligning to a long-sized boundary
  powerpc: Fix OF parsing of 64 bits PCI addresses
  powerpc: Use WARN_ON(1) instead of __WARN()
  powerpc: Fix support for latencytop
  powerpc/ps3: Update ps3_defconfig
  powerpc/ps3: Add a sub-match id to ps3_system_bus
  powerpc: Add a 6xx defconfig
  powerpc/dma: Use the struct dma_attrs in iommu code
  powerpc/cell: Add support for power button of future IBM cell blades
  powerpc/cell: Cleanup sysreset_hack for IBM cell blades
  ...
This commit is contained in:
Linus Torvalds 2008-07-22 13:16:01 -07:00
parent 53baaaa968 8725f25acc
commit 06b8147c5d
111 changed files with 6421 additions and 1617 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/DMA-attributes.txt
View File

@ -22,3 +22,12 @@ ready and available in memory. The DMA of the "completion indication"
could race with data DMA. Mapping the memory used for completion
indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
DMA_ATTR_WEAK_ORDERING
----------------------
DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
may be weakly ordered, that is that reads and writes may pass each other.
Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.

189
Documentation/powerpc/booting-without-of.txt
View File

@ -89,10 +89,12 @@ Table of Contents
3) OpenPIC Interrupt Controllers
4) ISA Interrupt Controllers
VIII - Specifying GPIO information for devices
IX - Specifying GPIO information for devices
1) gpios property
2) gpio-controller nodes
X - Specifying device power management information (sleep property)
Appendix A - Sample SOC node for MPC8540
@ -2488,8 +2490,8 @@ encodings listed below:
2 = high to low edge sensitive type enabled
3 = low to high edge sensitive type enabled
VIII - Specifying GPIO information for devices
==============================================
IX - Specifying GPIO information for devices
============================================
1) gpios property
-----------------
@ -2537,116 +2539,151 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
gpio-controller;
};
X - Specifying Device Power Management Information (sleep property)
===================================================================
Devices on SOCs often have mechanisms for placing devices into low-power
states that are decoupled from the devices' own register blocks. Sometimes,
this information is more complicated than a cell-index property can
reasonably describe. Thus, each device controlled in such a manner
may contain a "sleep" property which describes these connections.
The sleep property consists of one or more sleep resources, each of
which consists of a phandle to a sleep controller, followed by a
controller-specific sleep specifier of zero or more cells.
The semantics of what type of low power modes are possible are defined
by the sleep controller. Some examples of the types of low power modes
that may be supported are:
- Dynamic: The device may be disabled or enabled at any time.
- System Suspend: The device may request to be disabled or remain
awake during system suspend, but will not be disabled until then.
- Permanent: The device is disabled permanently (until the next hard
reset).
Some devices may share a clock domain with each other, such that they should
only be suspended when none of the devices are in use. Where reasonable,
such nodes should be placed on a virtual bus, where the bus has the sleep
property. If the clock domain is shared among devices that cannot be
reasonably grouped in this manner, then create a virtual sleep controller
(similar to an interrupt nexus, except that defining a standardized
sleep-map should wait until its necessity is demonstrated).
Appendix A - Sample SOC node for MPC8540
========================================
Note that the #address-cells and #size-cells for the SoC node
in this example have been explicitly listed; these are likely
not necessary as they are usually the same as the root node.
soc8540@e0000000 {
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8540-ccsr", "simple-bus";
device_type = "soc";
ranges = <00000000 e0000000 00100000>
reg = <e0000000 00003000>;
ranges = <0x00000000 0xe0000000 0x00100000>
bus-frequency = <0>;
mdio@24520 {
reg = <24520 20>;
device_type = "mdio";
compatible = "gianfar";
ethernet-phy@0 {
linux,phandle = <2452000>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <1>;
device_type = "ethernet-phy";
};
ethernet-phy@3 {
linux,phandle = <2452002>
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
interrupt-parent = <&pic>;
ethernet@24000 {
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 3 e 3 12 3>;
interrupt-parent = <40000>;
phy-handle = <2452000>;
compatible = "gianfar", "simple-bus";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <29 2 30 2 34 2>;
phy-handle = <&phy0>;
sleep = <&pmc 00000080>;
ranges;
mdio@24520 {
reg = <0x24520 0x20>;
compatible = "fsl,gianfar-mdio";
phy0: ethernet-phy@0 {
interrupts = <5 1>;
reg = <0>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupts = <5 1>;
reg = <1>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupts = <7 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 3 14 3 18 3>;
interrupt-parent = <40000>;
phy-handle = <2452001>;
reg = <0x25000 0x1000>;
local-mac-address = [ 00 E0 0C 00 73 01 ];
interrupts = <13 2 14 2 18 2>;
phy-handle = <&phy1>;
sleep = <&pmc 00000040>;
};
ethernet@26000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "FEC";
compatible = "gianfar";
reg = <26000 1000>;
mac-address = [ 00 E0 0C 00 73 02 ];
interrupts = <19 3>;
interrupt-parent = <40000>;
phy-handle = <2452002>;
reg = <0x26000 0x1000>;
local-mac-address = [ 00 E0 0C 00 73 02 ];
interrupts = <41 2>;
phy-handle = <&phy3>;
sleep = <&pmc 00000020>;
};
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <1a 3>;
interrupt-parent = <40000>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8540-duart", "simple-bus";
sleep = <&pmc 00000002>;
ranges;
serial@4500 {
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
};
serial@4600 {
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
};
};
pic@40000 {
linux,phandle = <40000>;
pic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
reg = <40000 40000>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
i2c@3000 {
interrupt-parent = <40000>;
interrupts = <1b 3>;
reg = <3000 18>;
device_type = "i2c";
interrupts = <43 2>;
reg = <0x3000 0x100>;
compatible = "fsl-i2c";
dfsrr;
sleep = <&pmc 00000004>;
};
pmc: power@e0070 {
compatible = "fsl,mpc8540-pmc", "fsl,mpc8548-pmc";
reg = <0xe0070 0x20>;
};
};

38
Documentation/powerpc/dts-bindings/fsl/cpm_qe/gpio.txt Normal file
View File

@ -0,0 +1,38 @@
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
On CPM1 devices, all ports are using slightly different register layouts.
Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
On CPM2 devices, all ports are 32bit ports and use a common register layout.
Required properties:
- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
"fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
"fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional paramters (currently unused).
- gpio-controller : Marks the port as GPIO controller.
Example of three SOC GPIO banks defined as gpio-controller nodes:
CPM1_PIO_A: gpio-controller@950 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-a";
reg = <0x950 0x10>;
gpio-controller;
};
CPM1_PIO_B: gpio-controller@ab8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-b";
reg = <0xab8 0x10>;
gpio-controller;
};
CPM1_PIO_E: gpio-controller@ac8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-e";
reg = <0xac8 0x18>;
gpio-controller;
};

53
Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
View File

@ -1,22 +1,37 @@
* USB (Universal Serial Bus Controller)
Freescale QUICC Engine USB Controller
Required properties:
- compatible : could be "qe_udc" or "fhci-hcd".
- mode : the could be "host" or "slave".
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
- reg : the first two cells should contain usb registers location and
length, the next two two cells should contain PRAM location and
length.
- interrupts : should contain USB interrupt.
- interrupt-parent : interrupt source phandle.
- fsl,fullspeed-clock : specifies the full speed USB clock source:
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- fsl,lowspeed-clock : specifies the low speed USB clock source:
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- hub-power-budget : USB power budget for the root hub, in mA.
- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
USBRN, SPEED (optional), and POWER (optional).
Example(slave):
usb@6c0 {
compatible = "qe_udc";
reg = <6c0 40>;
interrupts = <8b 0>;
interrupt-parent = <700>;
mode = "slave";
};
Example:
usb@6c0 {
compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
fsl,fullspeed-clock = "clk21";
gpios = <&qe_pio_b 2 0 /* USBOE */
&qe_pio_b 3 0 /* USBTP */
&qe_pio_b 8 0 /* USBTN */
&qe_pio_b 9 0 /* USBRP */
&qe_pio_b 11 0 /* USBRN */
&qe_pio_e 20 0 /* SPEED */
&qe_pio_e 21 0 /* POWER */>;
};

17
Documentation/powerpc/dts-bindings/fsl/mcu-mpc8349emitx.txt Normal file
View File

@ -0,0 +1,17 @@
Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU)
Required properties:
- compatible : "fsl,<mcu-chip>-<board>", "fsl,mcu-mpc8349emitx".
- reg : should specify I2C address (0x0a).
- #gpio-cells : should be 2.
- gpio-controller : should be present.
Example:
mcu@0a {
#gpio-cells = <2>;
compatible = "fsl,mc9s08qg8-mpc8349emitx",
"fsl,mcu-mpc8349emitx";
reg = <0x0a>;
gpio-controller;
};

63
Documentation/powerpc/dts-bindings/fsl/pmc.txt Normal file
View File

@ -0,0 +1,63 @@
* Power Management Controller
Properties:
- compatible: "fsl,<chip>-pmc".
"fsl,mpc8349-pmc" should be listed for any chip whose PMC is
compatible. "fsl,mpc8313-pmc" should also be listed for any chip
whose PMC is compatible, and implies deep-sleep capability.
"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
compatible. "fsl,mpc8536-pmc" should also be listed for any chip
whose PMC is compatible, and implies deep-sleep capability.
"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
compatible; all statements below that apply to "fsl,mpc8548-pmc" also
apply to "fsl,mpc8641d-pmc".
Compatibility does not include bit assigments in SCCR/PMCDR/DEVDISR; these
bit assigments are indicated via the sleep specifier in each device's
sleep property.
- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
is the PMC block, and the second resource is the Clock Configuration
block.
For devices compatible with "fsl,mpc8548-pmc", the first resource
is a 32-byte block beginning with DEVDISR.
- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
resource is the PMC block interrupt.
- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
a wakeup source from deep sleep.
Sleep specifiers:
fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
that is set in the cell, the corresponding bit in SCCR will be saved
and cleared on suspend, and restored on resume. This sleep controller
supports disabling and resuming devices at any time.
fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
which will be ORed into PMCDR upon suspend, and cleared from PMCDR
upon resume. The first two cells are as described for fsl,mpc8578-pmc.
This sleep controller only supports disabling devices during system
sleep, or permanently.
fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
first of which will be ORed into DEVDISR (and the second into
DEVDISR2, if present -- this cell should be zero or absent if the
hardware does not have DEVDISR2) upon a request for permanent device
disabling. This sleep controller does not support configuring devices
to disable during system sleep (unless supported by another compatible
match), or dynamically.
Example:
power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 8>;
};

31
Documentation/powerpc/dts-bindings/fsl/tsec.txt
View File

@ -24,46 +24,39 @@ Example:
* Gianfar-compatible ethernet nodes
Required properties:
Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- compatible : Should be "gianfar"
- reg : Offset and length of the register set for the device
- mac-address : List of bytes representing the ethernet address of
- local-mac-address : List of bytes representing the ethernet address of
this controller
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
transmit, the second is receive, and the third is error.
- phy-handle : The phandle for the PHY connected to this ethernet
controller.
- fixed-link : <a b c d e> where a is emulated phy id - choose any,
but unique to the all specified fixed-links, b is duplex - 0 half,
1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
Recommended properties:
- phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
"tbi", or "rtbi". This property is only really needed if the connection
is of type "rgmii-id", as all other connection types are detected by
hardware.
- fsl,magic-packet : If present, indicates that the hardware supports
waking up via magic packet.
Example:
ethernet@24000 {
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <d 3 e 3 12 3>;
interrupt-parent = <40000>;
phy-handle = <2452000>
reg = <0x24000 0x1000>;
local-mac-address = [ 00 E0 0C 00 73 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};

28
Documentation/powerpc/dts-bindings/fsl/upm-nand.txt Normal file
View File

@ -0,0 +1,28 @@
Freescale Localbus UPM programmed to work with NAND flash
Required properties:
- compatible : "fsl,upm-nand".
- reg : should specify localbus chip select and size used for the chip.
- fsl,upm-addr-offset : UPM pattern offset for the address latch.
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
- gpios : may specify optional GPIO connected to the Ready-Not-Busy pin.
Example:
upm@1,0 {
compatible = "fsl,upm-nand";
reg = <1 0 1>;
fsl,upm-addr-offset = <16>;
fsl,upm-cmd-offset = <8>;
gpios = <&qe_pio_e 18 0>;
flash {
#address-cells = <1>;
#size-cells = <1>;
compatible = "...";
partition@0 {
...
};
};
};

15
Documentation/powerpc/dts-bindings/gpio/led.txt Normal file
View File

@ -0,0 +1,15 @@
LED connected to GPIO
Required properties:
- compatible : should be "gpio-led".
- label : (optional) the label for this LED. If omitted, the label is
taken from the node name (excluding the unit address).
- gpios : should specify LED GPIO.
Example:
led@0 {
compatible = "gpio-led";
label = "hdd";
gpios = <&mcu_pio 0 1>;
};

14
arch/powerpc/Kconfig
View File

@ -199,7 +199,7 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200
depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx
config PPC_DCR_NATIVE
bool
@ -568,11 +568,15 @@ config FSL_GTM
config MCA
bool
# Platforms that what PCI turned unconditionally just do select PCI
# in their config node. Platforms that want to choose at config
# time should select PPC_PCI_CHOICE
config PPC_PCI_CHOICE
bool
config PCI
bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_86xx \
|| PPC_MPC52xx || (EMBEDDED && (PPC_PSERIES || PPC_ISERIES)) \
|| PPC_PS3 || 44x
default y if !40x && !CPM2 && !8xx && !PPC_MPC512x && !PPC_83xx \
bool "PCI support" if PPC_PCI_CHOICE
default y if !40x && !CPM2 && !8xx && !PPC_83xx \
&& !PPC_85xx && !PPC_86xx
default PCI_PERMEDIA if !4xx && !CPM2 && !8xx
default PCI_QSPAN if !4xx && !CPM2 && 8xx

4
arch/powerpc/boot/Makefile
View File

@ -163,12 +163,12 @@ quiet_cmd_flex = FLEX $@
cmd_flex = $(FLEX) -o$@ $<; cp $@ $@_shipped
$(obj)/dtc-src/dtc-parser.tab.c: $(src)/dtc-src/dtc-parser.y FORCE
$(call if_changed,bison)
$(call if_changed,bison)
$(obj)/dtc-src/dtc-parser.tab.h: $(obj)/dtc-src/dtc-parser.tab.c
$(obj)/dtc-src/dtc-lexer.lex.c: $(src)/dtc-src/dtc-lexer.l FORCE
$(call if_changed,flex)
$(call if_changed,flex)
endif
#############

24
arch/powerpc/boot/dts/mpc7448hpc2.dts
View File

@ -18,6 +18,16 @@
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells =<0>;
@ -78,7 +88,7 @@
};
ethernet@6200 {
enet0: ethernet@6200 {
linux,network-index = <0>;
#size-cells = <0>;
device_type = "network";
@ -91,7 +101,7 @@
phy-handle = <&phy8>;
};
ethernet@6600 {
enet1: ethernet@6600 {
linux,network-index = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -105,7 +115,7 @@
phy-handle = <&phy9>;
};
serial@7808 {
serial0: serial@7808 {
device_type = "serial";
compatible = "ns16550";
reg = <0x7808 0x200>;
@ -114,7 +124,7 @@
interrupt-parent = <&mpic>;
};
serial@7c08 {
serial1: serial@7c08 {
device_type = "serial";
compatible = "ns16550";
reg = <0x7c08 0x200>;
@ -131,7 +141,7 @@
compatible = "chrp,open-pic";
device_type = "open-pic";
};
pci@1000 {
pci0: pci@1000 {
compatible = "tsi108-pci";
device_type = "pci";
#interrupt-cells = <1>;
@ -184,8 +194,4 @@
};
};
};
chosen {
linux,stdout-path = "/tsi108@c0000000/serial@7808";
};
};

239
arch/powerpc/boot/dts/mpc8313erdb.dts
View File

@ -109,18 +109,38 @@
reg = <0x200 0x100>;
};
i2c@3000 {
sleep-nexus {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
#size-cells = <1>;
compatible = "simple-bus";
sleep = <&pmc 0x03000000>;
ranges;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
crypto@30000 {
compatible = "fsl,sec2.2", "fsl,sec2.1",
"fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x0122003f>;
};
};
@ -188,37 +208,44 @@
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
phy_type = "utmi_wide";
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <19 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy4: ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <20 0x8>;
reg = <0x4>;
device_type = "ethernet-phy";
};
sleep = <&pmc 0x00300000>;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
sleep = <&pmc 0x20000000>;
ranges;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
compatible = "gianfar", "simple-bus";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 0x8 36 0x8 35 0x8>;
interrupt-parent = <&ipic>;
phy-handle = < &phy1 >;
fsl,magic-packet;
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <19 0x8>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy4: ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <20 0x8>;
reg = <0x4>;
device_type = "ethernet-phy";
};
};
};
enet1: ethernet@25000 {
@ -231,6 +258,8 @@
interrupts = <34 0x8 33 0x8 32 0x8>;
interrupt-parent = <&ipic>;
phy-handle = < &phy4 >;
sleep = <&pmc 0x10000000>;
fsl,magic-packet;
};
serial0: serial@4500 {
@ -253,17 +282,6 @@
interrupt-parent = <&ipic>;
};
crypto@30000 {
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x0122003f>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
@ -277,36 +295,119 @@
reg = <0x700 0x100>;
device_type = "ipic";
};
pmc: power@b00 {
compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 8>;
interrupt-parent = <&ipic>;
fsl,mpc8313-wakeup-timer = <&gtm1>;
/* Remove this (or change to "okay") if you have
* a REVA3 or later board, if you apply one of the
* workarounds listed in section 8.5 of the board
* manual, or if you are adapting this device tree
* to a different board.
*/
status = "fail";
};
gtm1: timer@500 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x500 0x100>;
interrupts = <90 8 78 8 84 8 72 8>;
interrupt-parent = <&ipic>;
};
timer@600 {
compatible = "fsl,mpc8313-gtm", "fsl,gtm";
reg = <0x600 0x100>;
interrupts = <91 8 79 8 85 8 73 8>;
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
cell-index = <1>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
sleep-nexus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
sleep = <&pmc 0x00010000>;
ranges;
/* IDSEL 0x0E -mini PCI */
0x7000 0x0 0x0 0x1 &ipic 18 0x8
0x7000 0x0 0x0 0x2 &ipic 18 0x8
0x7000 0x0 0x0 0x3 &ipic 18 0x8
0x7000 0x0 0x0 0x4 &ipic 18 0x8
pci0: pci@e0008500 {
cell-index = <1>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0E -mini PCI */
0x7000 0x0 0x0 0x1 &ipic 18 0x8
0x7000 0x0 0x0 0x2 &ipic 18 0x8
0x7000 0x0 0x0 0x3 &ipic 18 0x8
0x7000 0x0 0x0 0x4 &ipic 18 0x8
/* IDSEL 0x0F - PCI slot */
0x7800 0x0 0x0 0x1 &ipic 17 0x8
0x7800 0x0 0x0 0x2 &ipic 18 0x8
0x7800 0x0 0x0 0x3 &ipic 17 0x8
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
/* IDSEL 0x0F - PCI slot */
0x7800 0x0 0x0 0x1 &ipic 17 0x8
0x7800 0x0 0x0 0x2 &ipic 18 0x8
0x7800 0x0 0x0 0x3 &ipic 17 0x8
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8313-dma", "fsl,elo-dma";
reg = <0xe00082a8 4>;
ranges = <0 0xe0008100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
dma-channel@0 {
compatible = "fsl,mpc8313-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
};
dma-channel@80 {
compatible = "fsl,mpc8313-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <1>;
};
dma-channel@100 {
compatible = "fsl,mpc8313-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <2>;
};
dma-channel@180 {
compatible = "fsl,mpc8313-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <3>;
};
};
};
};

14
arch/powerpc/boot/dts/mpc8610_hpcd.dts
View File

@ -388,6 +388,20 @@
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
isa@1e {
device_type = "isa";
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0 0 0 0>;
ranges = <1 0 0x01000000 0 0
0x00001000>;
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 0x70 2>;
};
};
};
};
};

8
arch/powerpc/configs/85xx/mpc8544_ds_defconfig
View File

@ -997,10 +997,12 @@ CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set

8
arch/powerpc/configs/85xx/mpc8572_ds_defconfig
View File

@ -997,10 +997,12 @@ CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set

8
arch/powerpc/configs/mpc85xx_defconfig
View File

@ -1005,10 +1005,12 @@ CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set

121
arch/powerpc/configs/mpc8610_hpcd_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.26-rc5
# Mon Jun 9 08:50:24 2008
# Linux kernel version: 2.6.26
# Tue Jul 15 08:31:01 2008
#
# CONFIG_PPC64 is not set
@ -51,6 +51,8 @@ CONFIG_PPC_UDBG_16550=y
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFAULT_UIMAGE=y
CONFIG_HIBERNATE_32=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@ -97,6 +99,7 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_PCSPKR_PLATFORM=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
@ -117,7 +120,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_DMA_ATTRS is not set
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
@ -153,31 +156,43 @@ CONFIG_CLASSIC_RCU=y
#
# Platform support
#
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_PPC_82xx is not set
# CONFIG_PPC_83xx is not set
CONFIG_PPC_86xx=y
CONFIG_PPC_MULTIPLATFORM=y
CONFIG_CLASSIC32=y
CONFIG_PPC_CHRP=y
# CONFIG_PPC_MPC512x is not set
# CONFIG_PPC_MPC5121 is not set
# CONFIG_MPC5121_ADS is not set
# CONFIG_PPC_MPC52xx is not set
CONFIG_PPC_PMAC=y
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PPC_82xx is not set
# CONFIG_PQ2ADS is not set
# CONFIG_PPC_83xx is not set
CONFIG_PPC_86xx=y
# CONFIG_MPC8641_HPCN is not set
# CONFIG_SBC8641D is not set
CONFIG_MPC8610_HPCD=y
CONFIG_MPC8610=y
# CONFIG_EMBEDDED6xx is not set
CONFIG_PPC_NATIVE=y
# CONFIG_UDBG_RTAS_CONSOLE is not set
# CONFIG_IPIC is not set
CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
CONFIG_PPC_I8259=y
CONFIG_PPC_RTAS=y
# CONFIG_RTAS_ERROR_LOGGING is not set
CONFIG_RTAS_PROC=y
# CONFIG_MMIO_NVRAM is not set
# CONFIG_PPC_MPC106 is not set
CONFIG_PPC_MPC106=y
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_FSL_ULI1575 is not set
# CONFIG_PPC601_SYNC_FIX is not set
# CONFIG_TAU is not set
CONFIG_FSL_ULI1575=y
#
# Kernel options
@ -202,6 +217,7 @@ CONFIG_BINFMT_ELF=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_KEXEC is not set
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
@ -228,11 +244,13 @@ CONFIG_ISA_DMA_API=y
#
# Bus options
#
# CONFIG_ISA is not set
CONFIG_ZONE_DMA=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_INDIRECT_PCI=y
CONFIG_FSL_SOC=y
CONFIG_FSL_PCI=y
CONFIG_PPC_PCI_CHOICE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y
@ -469,6 +487,7 @@ CONFIG_OF_I2C=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_MAC_FLOPPY is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
@ -571,6 +590,8 @@ CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_MESH is not set
# CONFIG_SCSI_MAC53C94 is not set
# CONFIG_SCSI_SRP is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
@ -639,6 +660,10 @@ CONFIG_PATA_ALI=y
#
# IEEE 1394 (FireWire) support
#
#
# Enable only one of the two stacks, unless you know what you are doing
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
@ -655,6 +680,8 @@ CONFIG_DUMMY=y
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
# CONFIG_MACE is not set
# CONFIG_BMAC is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
@ -762,14 +789,16 @@ CONFIG_SERIAL_8250_RSA=y
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_PMACZILOG is not set
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_OF_PLATFORM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_BRIQ_PANEL is not set
# CONFIG_HVC_RTAS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set
@ -787,9 +816,11 @@ CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_HYDRA is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_POWERMAC=y
CONFIG_I2C_MPC=y
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_OCORES is not set
@ -826,6 +857,7 @@ CONFIG_I2C_MPC=y
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
@ -888,6 +920,9 @@ CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_OF is not set
# CONFIG_FB_CONTROL is not set
# CONFIG_FB_PLATINUM is not set
# CONFIG_FB_VALKYRIE is not set
# CONFIG_FB_CT65550 is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
@ -1027,11 +1062,18 @@ CONFIG_SND_VERBOSE_PROCFS=y
#
# ALSA PowerMac devices
#
# CONFIG_SND_POWERMAC is not set
#
# ALSA PowerPC devices
#
#
# Apple Onboard Audio driver
#
# CONFIG_SND_AOA is not set
# CONFIG_SND_AOA_SOUNDBUS is not set
#
# System on Chip audio support
#
@ -1075,7 +1117,57 @@ CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PPC is not set
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
@ -1295,8 +1387,11 @@ CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUGGER is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
# CONFIG_IRQSTACKS is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_BOOTX_TEXT is not set
# CONFIG_PPC_EARLY_DEBUG is not set
#

8
arch/powerpc/configs/mpc8641_hpcn_defconfig
View File

@ -991,10 +991,12 @@ CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
# CONFIG_SND_SUPPORT_OLD_API is not set
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set

3304
arch/powerpc/configs/ppc6xx_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

196
arch/powerpc/configs/ps3_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25
# Mon Apr 28 12:39:10 2008
# Linux kernel version: 2.6.26
# Wed Jul 16 13:59:24 2008
#
CONFIG_PPC64=y
@ -14,8 +14,9 @@ CONFIG_POWER4=y
CONFIG_TUNE_CELL=y
CONFIG_PPC_FPU=y
CONFIG_ALTIVEC=y
# CONFIG_VSX is not set
CONFIG_PPC_STD_MMU=y
# CONFIG_PPC_MM_SLICES is not set
CONFIG_PPC_MM_SLICES=y
CONFIG_VIRT_CPU_ACCOUNTING=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
@ -31,6 +32,7 @@ CONFIG_GENERIC_HARDIRQS=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_IRQ_PER_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@ -90,6 +92,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_SYSCTL_SYSCALL=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_EXTRA_PASS=y
@ -117,12 +120,15 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
@ -132,6 +138,7 @@ CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set
CONFIG_BLOCK_COMPAT=y
#
@ -152,13 +159,8 @@ CONFIG_CLASSIC_RCU=y
# Platform support
#
CONFIG_PPC_MULTIPLATFORM=y
# CONFIG_PPC_82xx is not set
# CONFIG_PPC_83xx is not set
# CONFIG_PPC_86xx is not set
# CONFIG_PPC_PSERIES is not set
# CONFIG_PPC_ISERIES is not set
# CONFIG_PPC_MPC512x is not set
# CONFIG_PPC_MPC5121 is not set
# CONFIG_PPC_PMAC is not set
# CONFIG_PPC_MAPLE is not set
# CONFIG_PPC_PASEMI is not set
@ -187,6 +189,7 @@ CONFIG_PPC_CELL=y
# Cell Broadband Engine options
#
CONFIG_SPU_FS=y
CONFIG_SPU_FS_64K_LS=y
CONFIG_SPU_BASE=y
# CONFIG_PQ2ADS is not set
# CONFIG_IPIC is not set
@ -222,6 +225,7 @@ CONFIG_PREEMPT_NONE=y
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_BINFMT_MISC=y
CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
# CONFIG_IOMMU_VMERGE is not set
CONFIG_IOMMU_HELPER=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
@ -248,18 +252,22 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
# CONFIG_SPARSEMEM_VMEMMAP is not set
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTPLUG_SPARSE=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_RESOURCES_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_ARCH_MEMORY_PROBE=y
# CONFIG_PPC_HAS_HASH_64K is not set
CONFIG_PPC_HAS_HASH_64K=y
# CONFIG_PPC_64K_PAGES is not set
CONFIG_FORCE_MAX_ZONEORDER=13
# CONFIG_SCHED_SMT is not set
CONFIG_SCHED_SMT=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
CONFIG_EXTRA_TARGETS=""
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_VERBOSE is not set
# CONFIG_SECCOMP is not set
CONFIG_ISA_DMA_API=y
@ -273,6 +281,7 @@ CONFIG_GENERIC_ISA_DMA=y
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
# CONFIG_HAS_RAPIDIO is not set
CONFIG_PAGE_OFFSET=0xc000000000000000
CONFIG_KERNEL_START=0xc000000000000000
CONFIG_PHYSICAL_START=0x00000000
@ -412,6 +421,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
@ -478,6 +489,7 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_SCSI_DH is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_MACINTOSH_DRIVERS is not set
@ -533,8 +545,18 @@ CONFIG_USB_NET_MCS7830=m
# CONFIG_USB_NET_CDC_SUBSET is not set
# CONFIG_USB_NET_ZAURUS is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
# CONFIG_PPP_FILTER is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=m
# CONFIG_PPP_BSDCOMP is not set
# CONFIG_PPP_MPPE is not set
CONFIG_PPPOE=m
# CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
@ -603,6 +625,7 @@ CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
@ -618,23 +641,17 @@ CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
@ -652,8 +669,17 @@ CONFIG_SSB_POSSIBLE=y
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
@ -671,8 +697,8 @@ CONFIG_FB=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
@ -712,18 +738,12 @@ CONFIG_FB_LOGO_EXTRA=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
#
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=m
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=m
# CONFIG_SND_SEQUENCER is not set
# CONFIG_SND_MIXER_OSS is not set
# CONFIG_SND_PCM_OSS is not set
@ -732,53 +752,20 @@ CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
#
# Generic devices
#
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
#
# ALSA PowerMac devices
#
#
# ALSA PowerMac requires I2C
#
#
# ALSA PowerPC devices
#
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_PPC=y
CONFIG_SND_PS3=m
CONFIG_SND_PS3_DEFAULT_START_DELAY=2000
#
# USB devices
#
# CONFIG_SND_USB_AUDIO is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
#
# System on Chip audio support
#
# CONFIG_SND_SOC is not set
#
# ALSA SoC audio for Freescale SOCs
#
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
# CONFIG_HIDRAW is not set
CONFIG_HIDRAW=y
#
# USB Input Devices
@ -807,17 +794,20 @@ CONFIG_USB=m
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_SUSPEND=y
# CONFIG_USB_OTG is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_EHCI_HCD=m
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
CONFIG_USB_OHCI_HCD=m
# CONFIG_USB_OHCI_HCD_PPC_OF is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
@ -831,6 +821,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
#
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@ -890,12 +881,45 @@ CONFIG_USB_MON=y
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
CONFIG_RTC_LIB=m
CONFIG_RTC_CLASS=m
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_PPC=m
# CONFIG_DMADEVICES is not set
# CONFIG_UIO is not set
@ -911,6 +935,7 @@ CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
@ -959,8 +984,8 @@ CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
# CONFIG_CONFIGFS_FS is not set
#
@ -1059,12 +1084,15 @@ CONFIG_NLS_ISO8859_1=y
#
CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
# CONFIG_CRC_CCITT is not set
CONFIG_CRC_CCITT=m
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=m
CONFIG_ZLIB_DEFLATE=m
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=m
CONFIG_PLIST=y
@ -1082,7 +1110,7 @@ CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
@ -1090,33 +1118,49 @@ CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
CONFIG_DEBUG_LOCKDEP=y
CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
CONFIG_DEBUG_WRITECOUNT=y
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_FTRACE is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_SAMPLES is not set
CONFIG_DEBUG_STACKOVERFLOW=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUGGER is not set
# CONFIG_CODE_PATCHING_SELFTEST is not set
# CONFIG_FTR_FIXUP_SELFTEST is not set
CONFIG_IRQSTACKS=y
# CONFIG_VIRQ_DEBUG is not set
# CONFIG_BOOTX_TEXT is not set
# CONFIG_PPC_EARLY_DEBUG is not set
@ -1172,6 +1216,10 @@ CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set

20
arch/powerpc/kernel/cputable.c
View File

@ -355,6 +355,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 128,
.dcache_bsize = 128,
.machine_check = machine_check_generic,
.oprofile_cpu_type = "ppc64/compat-power5+",
.platform = "power5+",
},
{ /* Power6 */
@ -386,6 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 128,
.dcache_bsize = 128,
.machine_check = machine_check_generic,
.oprofile_cpu_type = "ppc64/compat-power6",
.platform = "power6",
},
{ /* 2.06-compliant processor, i.e. Power7 "architected" mode */
@ -397,6 +399,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 128,
.dcache_bsize = 128,
.machine_check = machine_check_generic,
.oprofile_cpu_type = "ppc64/compat-power7",
.platform = "power7",
},
{ /* Power7 */
@ -1629,6 +1632,23 @@ struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
t->cpu_setup = s->cpu_setup;
t->cpu_restore = s->cpu_restore;
t->platform = s->platform;
/*
* If we have passed through this logic once
* before and have pulled the default case
* because the real PVR was not found inside
* cpu_specs[], then we are possibly running in
* compatibility mode. In that case, let the
* oprofiler know which set of compatibility
* counters to pull from by making sure the
* oprofile_cpu_type string is set to that of
* compatibility mode. If the oprofile_cpu_type
* already has a value, then we are possibly
* overriding a real PVR with a logical one, and,
* in that case, keep the current value for
* oprofile_cpu_type.
*/
if (t->oprofile_cpu_type == NULL)
t->oprofile_cpu_type = s->oprofile_cpu_type;
} else
*t = *s;
*PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;

187
arch/powerpc/kernel/head_fsl_booke.S
View File

@ -151,16 +151,11 @@ skpinv: addi r6,r6,1 /* Increment */
/* Invalidate TLB0 */
li r6,0x04
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
TLBSYNC
/* Invalidate TLB1 */
li r6,0x0c
tlbivax 0,r6
#ifdef CONFIG_SMP
tlbsync
#endif
msync
TLBSYNC
/* 3. Setup a temp mapping and jump to it */
andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
@ -238,10 +233,7 @@ skpinv: addi r6,r6,1 /* Increment */
/* Invalidate TLB1 */
li r9,0x0c
tlbivax 0,r9
#ifdef CONFIG_SMP
tlbsync
#endif
msync
TLBSYNC
/* 6. Setup KERNELBASE mapping in TLB1[0] */
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
@ -283,10 +275,7 @@ skpinv: addi r6,r6,1 /* Increment */
/* Invalidate TLB1 */
li r9,0x0c
tlbivax 0,r9
#ifdef CONFIG_SMP
tlbsync
#endif
msync
TLBSYNC
/* Establish the interrupt vector offsets */
SET_IVOR(0, CriticalInput);
@ -483,90 +472,16 @@ interrupt_base:
/* Data Storage Interrupt */
START_EXCEPTION(DataStorage)
mtspr SPRN_SPRG0, r10 /* Save some working registers */
mtspr SPRN_SPRG1, r11
mtspr SPRN_SPRG4W, r12
mtspr SPRN_SPRG5W, r13
mfcr r11
mtspr SPRN_SPRG7W, r11
/*
* Check if it was a store fault, if not then bail
* because a user tried to access a kernel or
* read-protected page. Otherwise, get the
* offending address and handle it.
*/
mfspr r10, SPRN_ESR
andis. r10, r10, ESR_ST@h
beq 2f
mfspr r10, SPRN_DEAR /* Get faulting address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
lis r11, PAGE_OFFSET@h
cmplw 0, r10, r11
bge 2f
/* Get the PGD for the current thread */
3:
mfspr r11,SPRN_SPRG3
lwz r11,PGDIR(r11)
4:
FIND_PTE
/* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
cmpwi 0, r13, _PAGE_RW|_PAGE_USER
bne 2f /* Bail if not */
/* Update 'changed'. */
ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
/* MAS2 not updated as the entry does exist in the tlb, this
fault taken to detect state transition (eg: COW -> DIRTY)
*/
andi. r11, r11, _PAGE_HWEXEC
rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
/* update search PID in MAS6, AS = 0 */
mfspr r12, SPRN_PID0
slwi r12, r12, 16
mtspr SPRN_MAS6, r12
/* find the TLB index that caused the fault. It has to be here. */
tlbsx 0, r10
/* only update the perm bits, assume the RPN is fine */
mfspr r12, SPRN_MAS3
rlwimi r12, r11, 0, 20, 31
mtspr SPRN_MAS3,r12
tlbwe
/* Done...restore registers and get out of here. */
mfspr r11, SPRN_SPRG7R
mtcr r11
mfspr r13, SPRN_SPRG5R
mfspr r12, SPRN_SPRG4R
mfspr r11, SPRN_SPRG1
mfspr r10, SPRN_SPRG0
rfi /* Force context change */
2:
/*
* The bailout. Restore registers to pre-exception conditions
* and call the heavyweights to help us out.
*/
mfspr r11, SPRN_SPRG7R
mtcr r11
mfspr r13, SPRN_SPRG5R
mfspr r12, SPRN_SPRG4R
mfspr r11, SPRN_SPRG1
mfspr r10, SPRN_SPRG0
b data_access
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
stw r5,_ESR(r11)
mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
andis. r10,r5,(ESR_ILK|ESR_DLK)@h
bne 1f
EXC_XFER_EE_LITE(0x0300, handle_page_fault)
1:
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x0300, CacheLockingException)
/* Instruction Storage Interrupt */
INSTRUCTION_STORAGE_EXCEPTION
@ -645,15 +560,30 @@ interrupt_base:
lwz r11,PGDIR(r11)
4:
/* Mask of required permission bits. Note that while we
* do copy ESR:ST to _PAGE_RW position as trying to write
* to an RO page is pretty common, we don't do it with
* _PAGE_DIRTY. We could do it, but it's a fairly rare
* event so I'd rather take the overhead when it happens
* rather than adding an instruction here. We should measure
* whether the whole thing is worth it in the first place
* as we could avoid loading SPRN_ESR completely in the first
* place...
*
* TODO: Is it worth doing that mfspr & rlwimi in the first
* place or can we save a couple of instructions here ?
*/
mfspr r12,SPRN_ESR
li r13,_PAGE_PRESENT|_PAGE_ACCESSED
rlwimi r13,r12,11,29,29
FIND_PTE
andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
beq 2f /* Bail if not present */
andc. r13,r13,r11 /* Check permission */
bne 2f /* Bail if permission mismach */
#ifdef CONFIG_PTE_64BIT
lwz r13, 0(r12)
#endif
ori r11, r11, _PAGE_ACCESSED
stw r11, PTE_FLAGS_OFFSET(r12)
/* Jump to common tlb load */
b finish_tlb_load
@ -667,7 +597,7 @@ interrupt_base:
mfspr r12, SPRN_SPRG4R
mfspr r11, SPRN_SPRG1
mfspr r10, SPRN_SPRG0
b data_access
b DataStorage
/* Instruction TLB Error Interrupt */
/*
@ -705,15 +635,16 @@ interrupt_base:
lwz r11,PGDIR(r11)
4:
/* Make up the required permissions */
li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
FIND_PTE
andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
beq 2f /* Bail if not present */
andc. r13,r13,r11 /* Check permission */
bne 2f /* Bail if permission mismach */
#ifdef CONFIG_PTE_64BIT
lwz r13, 0(r12)
#endif
ori r11, r11, _PAGE_ACCESSED
stw r11, PTE_FLAGS_OFFSET(r12)
/* Jump to common TLB load point */
b finish_tlb_load
@ -768,29 +699,13 @@ interrupt_base:
* Local functions
*/
/*
* Data TLB exceptions will bail out to this point
* if they can't resolve the lightweight TLB fault.
*/
data_access:
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
stw r5,_ESR(r11)
mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
andis. r10,r5,(ESR_ILK|ESR_DLK)@h
bne 1f
EXC_XFER_EE_LITE(0x0300, handle_page_fault)
1:
addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_EE_LITE(0x0300, CacheLockingException)
/*
* Both the instruction and data TLB miss get to this
* point to load the TLB.
* r10 - EA of fault
* r11 - TLB (info from Linux PTE)
* r12, r13 - available to use
* r12 - available to use
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
* CR5 - results of addr >= PAGE_OFFSET
* MAS0, MAS1 - loaded with proper value when we get here
* MAS2, MAS3 - will need additional info from Linux PTE
@ -812,20 +727,14 @@ finish_tlb_load:
#endif
mtspr SPRN_MAS2, r12
bge 5, 1f
/* is user addr */
andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
and r12, r11, r10
andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
srwi r10, r12, 1
or r12, r12, r10 /* Copy user perms into supervisor */
iseleq r12, 0, r12
b 2f
/* is kernel addr */
1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
ori r12, r12, (MAS3_SX | MAS3_SR)
slwi r10, r12, 1
or r10, r10, r12
iseleq r12, r12, r10
#ifdef CONFIG_PTE_64BIT
2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */

13
arch/powerpc/kernel/iommu.c
View File

@ -186,7 +186,8 @@ static unsigned long iommu_range_alloc(struct device *dev,
static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
void *page, unsigned int npages,
enum dma_data_direction direction,
unsigned long mask, unsigned int align_order)
unsigned long mask, unsigned int align_order,
struct dma_attrs *attrs)
{
unsigned long entry, flags;
dma_addr_t ret = DMA_ERROR_CODE;
@ -205,7 +206,7 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
/* Put the TCEs in the HW table */
ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & IOMMU_PAGE_MASK,
direction);
direction, attrs);
/* Flush/invalidate TLB caches if necessary */
@ -336,7 +337,8 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
npages, entry, dma_addr);
/* Insert into HW table */
ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK, direction);
ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK,
direction, attrs);
/* If we are in an open segment, try merging */
if (segstart != s) {
@ -573,7 +575,8 @@ dma_addr_t iommu_map_single(struct device *dev, struct iommu_table *tbl,
align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
mask >> IOMMU_PAGE_SHIFT, align);
mask >> IOMMU_PAGE_SHIFT, align,
attrs);
if (dma_handle == DMA_ERROR_CODE) {
if (printk_ratelimit()) {
printk(KERN_INFO "iommu_alloc failed, "
@ -642,7 +645,7 @@ void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
nio_pages = size >> IOMMU_PAGE_SHIFT;
io_order = get_iommu_order(size);
mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
mask >> IOMMU_PAGE_SHIFT, io_order);
mask >> IOMMU_PAGE_SHIFT, io_order, NULL);
if (mapping == DMA_ERROR_CODE) {
free_pages((unsigned long)ret, order);
return NULL;

1
arch/powerpc/kernel/pci-common.c
View File

@ -598,6 +598,7 @@ void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
res->start = pci_addr;
break;
case 2: /* PCI Memory space */
case 3: /* PCI 64 bits Memory space */
printk(KERN_INFO
" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
cpu_addr, cpu_addr + size - 1, pci_addr,

54
arch/powerpc/kernel/prom_parse.c
View File

@ -128,31 +128,6 @@ static void of_bus_pci_count_cells(struct device_node *np,
*sizec = 2;
}
static u64 of_bus_pci_map(u32 *addr, const u32 *range, int na, int ns, int pna)
{
u64 cp, s, da;
/* Check address type match */
if ((addr[0] ^ range[0]) & 0x03000000)
return OF_BAD_ADDR;
/* Read address values, skipping high cell */
cp = of_read_number(range + 1, na - 1);
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr + 1, na - 1);
DBG("OF: PCI map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
return da - cp;
}
static int of_bus_pci_translate(u32 *addr, u64 offset, int na)
{
return of_bus_default_translate(addr + 1, offset, na - 1);
}
static unsigned int of_bus_pci_get_flags(const u32 *addr)
{
unsigned int flags = 0;
@ -172,6 +147,35 @@ static unsigned int of_bus_pci_get_flags(const u32 *addr)
return flags;
}
static u64 of_bus_pci_map(u32 *addr, const u32 *range, int na, int ns, int pna)
{
u64 cp, s, da;
unsigned int af, rf;
af = of_bus_pci_get_flags(addr);
rf = of_bus_pci_get_flags(range);
/* Check address type match */
if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO))
return OF_BAD_ADDR;
/* Read address values, skipping high cell */
cp = of_read_number(range + 1, na - 1);
s = of_read_number(range + na + pna, ns);
da = of_read_number(addr + 1, na - 1);
DBG("OF: PCI map, cp="PRu64", s="PRu64", da="PRu64"\n", cp, s, da);
if (da < cp || da >= (cp + s))
return OF_BAD_ADDR;
return da - cp;
}
static int of_bus_pci_translate(u32 *addr, u64 offset, int na)
{
return of_bus_default_translate(addr + 1, offset, na - 1);
}
const u32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size,
unsigned int *flags)
{

2
arch/powerpc/kernel/stacktrace.c
View File

@ -59,6 +59,6 @@ EXPORT_SYMBOL_GPL(save_stack_trace);
void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
{
save_context_stack(trace, tsk->thread.regs->gpr[1], tsk, 0);
save_context_stack(trace, tsk->thread.ksp, tsk, 0);
}
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);

31
arch/powerpc/kernel/vmlinux.lds.S
View File

@ -9,6 +9,25 @@
ENTRY(_stext)
PHDRS {
kernel PT_LOAD FLAGS(7); /* RWX */
notes PT_NOTE FLAGS(0);
dummy PT_NOTE FLAGS(0);
/* binutils < 2.18 has a bug that makes it misbehave when taking an
ELF file with all segments at load address 0 as input. This
happens when running "strip" on vmlinux, because of the AT() magic
in this linker script. People using GCC >= 4.2 won't run into
this problem, because the "build-id" support will put some data
into the "notes" segment (at a non-zero load address).
To work around this, we force some data into both the "dummy"
segment and the kernel segment, so the dummy segment will get a
non-zero load address. It's not enough to always create the
"notes" segment, since if nothing gets assigned to it, its load
address will be zero. */
}
#ifdef CONFIG_PPC64
OUTPUT_ARCH(powerpc:common64)
jiffies = jiffies_64;
@ -50,7 +69,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
_etext = .;
PROVIDE32 (etext = .);
}
} :kernel
/* Read-only data */
RODATA
@ -62,7 +81,13 @@ SECTIONS
__stop___ex_table = .;
}
NOTES
NOTES :kernel :notes
/* The dummy segment contents for the bug workaround mentioned above
near PHDRS. */
.dummy : {
LONG(0xf177)
} :kernel :dummy
/*
* Init sections discarded at runtime
@ -74,7 +99,7 @@ SECTIONS
_sinittext = .;
INIT_TEXT
_einittext = .;
}
} :kernel
/* .exit.text is discarded at runtime, not link time,
* to deal with references from __bug_table

2
arch/powerpc/lib/feature-fixups.c
View File

@ -99,7 +99,7 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
for (; fcur < fend; fcur++) {
if (patch_feature_section(value, fcur)) {
__WARN();
WARN_ON(1);
printk("Unable to patch feature section at %p - %p" \
" with %p - %p\n",
calc_addr(fcur, fcur->start_off),

18
arch/powerpc/lib/string.S
View File

@ -13,13 +13,7 @@
#include <asm/ppc_asm.h>
.section __ex_table,"a"
#ifdef CONFIG_PPC64
.align 3
#define EXTBL .llong
#else
.align 2
#define EXTBL .long
#endif
PPC_LONG_ALIGN
.text
_GLOBAL(strcpy)
@ -160,9 +154,9 @@ _GLOBAL(__clear_user)
blr
.section __ex_table,"a"
EXTBL 11b,90b
EXTBL 1b,91b
EXTBL 8b,92b
PPC_LONG 11b,90b
PPC_LONG 1b,91b
PPC_LONG 8b,92b
.text
_GLOBAL(__strncpy_from_user)
@ -183,7 +177,7 @@ _GLOBAL(__strncpy_from_user)
blr
.section __ex_table,"a"
EXTBL 1b,99b
PPC_LONG 1b,99b
.text
/* r3 = str, r4 = len (> 0), r5 = top (highest addr) */
@ -208,4 +202,4 @@ _GLOBAL(__strnlen_user)
blr
.section __ex_table,"a"
EXTBL 1b,99b
PPC_LONG 1b,99b

1
arch/powerpc/platforms/52xx/Kconfig
View File

@ -3,6 +3,7 @@ config PPC_MPC52xx
depends on PPC_MULTIPLATFORM && PPC32
select FSL_SOC
select PPC_CLOCK
select PPC_PCI_CHOICE
config PPC_MPC5200_SIMPLE
bool "Generic support for simple MPC5200 based boards"

1
arch/powerpc/platforms/82xx/Kconfig
View File

@ -30,6 +30,7 @@ config EP8248E
select 8272
select 8260
select FSL_SOC
select PHYLIB
select MDIO_BITBANG
help
This enables support for the Embedded Planet EP8248E board.

4
arch/powerpc/platforms/82xx/ep8248e.c
View File

@ -59,7 +59,6 @@ static void __init ep8248e_pic_init(void)
of_node_put(np);
}
#ifdef CONFIG_FS_ENET_MDIO_FCC
static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
{
if (level)
@ -165,7 +164,6 @@ static struct of_platform_driver ep8248e_mdio_driver = {
.probe = ep8248e_mdio_probe,
.remove = ep8248e_mdio_remove,
};
#endif
struct cpm_pin {
int port, pin, flags;
@ -298,9 +296,7 @@ static __initdata struct of_device_id of_bus_ids[] = {
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
#ifdef CONFIG_FS_ENET_MDIO_FCC
of_register_platform_driver(&ep8248e_mdio_driver);
#endif
return 0;
}

3
arch/powerpc/platforms/83xx/Kconfig
View File

@ -2,7 +2,8 @@ menuconfig PPC_83xx
bool "83xx-based boards"
depends on 6xx && PPC_MULTIPLATFORM
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select FSL_SOC
select IPIC

2
arch/powerpc/platforms/83xx/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for the PowerPC 83xx linux kernel.
#
obj-y := misc.o usb.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SUSPEND) += suspend.o suspend-asm.o
obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o

1
arch/powerpc/platforms/83xx/mpc831x_rdb.c
View File

@ -19,6 +19,7 @@
#include <asm/time.h>
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc832x_mds.c
View File

@ -36,6 +36,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>

1
arch/powerpc/platforms/83xx/mpc832x_rdb.c
View File

@ -27,6 +27,7 @@
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc834x_itx.c
View File

@ -35,6 +35,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc834x_mds.c
View File

@ -35,6 +35,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc836x_mds.c
View File

@ -42,6 +42,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>

1
arch/powerpc/platforms/83xx/mpc836x_rdk.c
View File

@ -23,6 +23,7 @@
#include <asm/qe.h>
#include <asm/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc837x_mds.c
View File

@ -19,6 +19,7 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <asm/prom.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

1
arch/powerpc/platforms/83xx/mpc837x_rdb.c
View File

@ -17,6 +17,7 @@
#include <asm/time.h>
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

5
arch/powerpc/platforms/83xx/mpc83xx.h
View File

@ -26,6 +26,8 @@
#define MPC834X_SICRL_USB1 0x20000000
#define MPC831X_SICRL_USB_MASK 0x00000c00
#define MPC831X_SICRL_USB_ULPI 0x00000800
#define MPC8315_SICRL_USB_MASK 0x000000fc
#define MPC8315_SICRL_USB_ULPI 0x00000054
#define MPC837X_SICRL_USB_MASK 0xf0000000
#define MPC837X_SICRL_USB_ULPI 0x50000000
@ -34,6 +36,8 @@
#define MPC834X_SICRH_USB_UTMI 0x00020000
#define MPC831X_SICRH_USB_MASK 0x000000e0
#define MPC831X_SICRH_USB_ULPI 0x000000a0
#define MPC8315_SICRH_USB_MASK 0x0000ff00
#define MPC8315_SICRH_USB_ULPI 0x00000000
/* USB Control Register */
#define FSL_USB2_CONTROL_OFFS 0x500
@ -55,7 +59,6 @@
* mpc83xx_* files. Mostly for use by mpc83xx_setup
*/
extern int mpc83xx_add_bridge(struct device_node *dev);
extern void mpc83xx_restart(char *cmd);
extern long mpc83xx_time_init(void);
extern int mpc834x_usb_cfg(void);

91
arch/powerpc/platforms/83xx/pci.c
View File

@ -1,91 +0,0 @@
/*
* FSL SoC setup code
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
int __init mpc83xx_add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 1, has_address = 0;
phys_addr_t immr = get_immrbase();
DBG("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
/* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
* the other at 0x8600, we consider the 0x8500 the primary controller
*/
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
primary = 0;
}
printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}

1
arch/powerpc/platforms/83xx/sbc834x.c
View File

@ -37,6 +37,7 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc83xx.h"

533
arch/powerpc/platforms/83xx/suspend-asm.S Normal file
View File

@ -0,0 +1,533 @@
/*
* Enter and leave deep sleep state on MPC83xx
*
* Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include <asm/asm-offsets.h>
#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
#define SS_HID 0x08 /* 3 HIDs */
#define SS_IABR 0x14 /* 2 IABRs */
#define SS_IBCR 0x1c
#define SS_DABR 0x20 /* 2 DABRs */
#define SS_DBCR 0x28
#define SS_SP 0x2c
#define SS_SR 0x30 /* 16 segment registers */
#define SS_R2 0x70
#define SS_MSR 0x74
#define SS_SDR1 0x78
#define SS_LR 0x7c
#define SS_SPRG 0x80 /* 4 SPRGs */
#define SS_DBAT 0x90 /* 8 DBATs */
#define SS_IBAT 0xd0 /* 8 IBATs */
#define SS_TB 0x110
#define SS_CR 0x118
#define SS_GPREG 0x11c /* r12-r31 */
#define STATE_SAVE_SIZE 0x16c
.section .data
.align 5
mpc83xx_sleep_save_area:
.space STATE_SAVE_SIZE
immrbase:
.long 0
.section .text
.align 5
/* r3 = physical address of IMMR */
_GLOBAL(mpc83xx_enter_deep_sleep)
lis r4, immrbase@ha
stw r3, immrbase@l(r4)
/* The first 2 words of memory are used to communicate with the
* bootloader, to tell it how to resume.
*
* The first word is the magic number 0xf5153ae5, and the second
* is the pointer to mpc83xx_deep_resume.
*
* The original content of these two words is saved in SS_MEMSAVE.
*/
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
lis r4, KERNELBASE@h
lwz r5, 0(r4)
lwz r6, 4(r4)
stw r5, SS_MEMSAVE+0(r3)
stw r6, SS_MEMSAVE+4(r3)
mfspr r5, SPRN_HID0
mfspr r6, SPRN_HID1
mfspr r7, SPRN_HID2
stw r5, SS_HID+0(r3)
stw r6, SS_HID+4(r3)
stw r7, SS_HID+8(r3)
mfspr r4, SPRN_IABR
mfspr r5, SPRN_IABR2
mfspr r6, SPRN_IBCR
mfspr r7, SPRN_DABR
mfspr r8, SPRN_DABR2
mfspr r9, SPRN_DBCR
stw r4, SS_IABR+0(r3)
stw r5, SS_IABR+4(r3)
stw r6, SS_IBCR(r3)
stw r7, SS_DABR+0(r3)
stw r8, SS_DABR+4(r3)
stw r9, SS_DBCR(r3)
mfspr r4, SPRN_SPRG0
mfspr r5, SPRN_SPRG1
mfspr r6, SPRN_SPRG2
mfspr r7, SPRN_SPRG3
mfsdr1 r8
stw r4, SS_SPRG+0(r3)
stw r5, SS_SPRG+4(r3)
stw r6, SS_SPRG+8(r3)
stw r7, SS_SPRG+12(r3)
stw r8, SS_SDR1(r3)
mfspr r4, SPRN_DBAT0U
mfspr r5, SPRN_DBAT0L
mfspr r6, SPRN_DBAT1U
mfspr r7, SPRN_DBAT1L
stw r4, SS_DBAT+0x00(r3)
stw r5, SS_DBAT+0x04(r3)
stw r6, SS_DBAT+0x08(r3)
stw r7, SS_DBAT+0x0c(r3)
mfspr r4, SPRN_DBAT2U
mfspr r5, SPRN_DBAT2L
mfspr r6, SPRN_DBAT3U
mfspr r7, SPRN_DBAT3L
stw r4, SS_DBAT+0x10(r3)
stw r5, SS_DBAT+0x14(r3)
stw r6, SS_DBAT+0x18(r3)
stw r7, SS_DBAT+0x1c(r3)
mfspr r4, SPRN_DBAT4U
mfspr r5, SPRN_DBAT4L
mfspr r6, SPRN_DBAT5U
mfspr r7, SPRN_DBAT5L
stw r4, SS_DBAT+0x20(r3)
stw r5, SS_DBAT+0x24(r3)
stw r6, SS_DBAT+0x28(r3)
stw r7, SS_DBAT+0x2c(r3)
mfspr r4, SPRN_DBAT6U
mfspr r5, SPRN_DBAT6L
mfspr r6, SPRN_DBAT7U
mfspr r7, SPRN_DBAT7L
stw r4, SS_DBAT+0x30(r3)
stw r5, SS_DBAT+0x34(r3)
stw r6, SS_DBAT+0x38(r3)
stw r7, SS_DBAT+0x3c(r3)
mfspr r4, SPRN_IBAT0U
mfspr r5, SPRN_IBAT0L
mfspr r6, SPRN_IBAT1U
mfspr r7, SPRN_IBAT1L
stw r4, SS_IBAT+0x00(r3)
stw r5, SS_IBAT+0x04(r3)
stw r6, SS_IBAT+0x08(r3)
stw r7, SS_IBAT+0x0c(r3)
mfspr r4, SPRN_IBAT2U
mfspr r5, SPRN_IBAT2L
mfspr r6, SPRN_IBAT3U
mfspr r7, SPRN_IBAT3L
stw r4, SS_IBAT+0x10(r3)
stw r5, SS_IBAT+0x14(r3)
stw r6, SS_IBAT+0x18(r3)
stw r7, SS_IBAT+0x1c(r3)
mfspr r4, SPRN_IBAT4U
mfspr r5, SPRN_IBAT4L
mfspr r6, SPRN_IBAT5U
mfspr r7, SPRN_IBAT5L
stw r4, SS_IBAT+0x20(r3)
stw r5, SS_IBAT+0x24(r3)
stw r6, SS_IBAT+0x28(r3)
stw r7, SS_IBAT+0x2c(r3)
mfspr r4, SPRN_IBAT6U
mfspr r5, SPRN_IBAT6L
mfspr r6, SPRN_IBAT7U
mfspr r7, SPRN_IBAT7L
stw r4, SS_IBAT+0x30(r3)
stw r5, SS_IBAT+0x34(r3)
stw r6, SS_IBAT+0x38(r3)
stw r7, SS_IBAT+0x3c(r3)
mfmsr r4
mflr r5
mfcr r6
stw r4, SS_MSR(r3)
stw r5, SS_LR(r3)
stw r6, SS_CR(r3)
stw r1, SS_SP(r3)
stw r2, SS_R2(r3)
1: mftbu r4
mftb r5
mftbu r6
cmpw r4, r6
bne 1b
stw r4, SS_TB+0(r3)
stw r5, SS_TB+4(r3)
stmw r12, SS_GPREG(r3)
li r4, 0
addi r6, r3, SS_SR-4
1: mfsrin r5, r4
stwu r5, 4(r6)
addis r4, r4, 0x1000
cmpwi r4, 0
bne 1b
/* Disable machine checks and critical exceptions */
mfmsr r4
rlwinm r4, r4, 0, ~MSR_CE
rlwinm r4, r4, 0, ~MSR_ME
mtmsr r4
isync
#define TMP_VIRT_IMMR 0xf0000000
#define DEFAULT_IMMR_VALUE 0xff400000
#define IMMRBAR_BASE 0x0000
lis r4, immrbase@ha
lwz r4, immrbase@l(r4)
/* Use DBAT0 to address the current IMMR space */
ori r4, r4, 0x002a
mtspr SPRN_DBAT0L, r4
lis r8, TMP_VIRT_IMMR@h
ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
mtspr SPRN_DBAT0U, r4
isync
/* Use DBAT1 to address the original IMMR space */
lis r4, DEFAULT_IMMR_VALUE@h
ori r4, r4, 0x002a
mtspr SPRN_DBAT1L, r4
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
mtspr SPRN_DBAT1U, r4
isync
/* Use DBAT2 to address the beginning of RAM. This isn't done
* using the normal virtual mapping, because with page debugging
* enabled it will be read-only.
*/
li r4, 0x0002
mtspr SPRN_DBAT2L, r4
lis r4, KERNELBASE@h
ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
mtspr SPRN_DBAT2U, r4
isync
/* Flush the cache with our BAT, as there will be TLB misses
* otherwise if page debugging is enabled, and these misses
* will disturb the PLRU algorithm.
*/
bl __flush_disable_L1
/* Keep the i-cache enabled, so the hack below for low-boot
* flash will work.
*/
mfspr r3, SPRN_HID0
ori r3, r3, HID0_ICE
mtspr SPRN_HID0, r3
isync
lis r6, 0xf515
ori r6, r6, 0x3ae5
lis r7, mpc83xx_deep_resume@h
ori r7, r7, mpc83xx_deep_resume@l
tophys(r7, r7)
lis r5, KERNELBASE@h
stw r6, 0(r5)
stw r7, 4(r5)
/* Reset BARs */
li r4, 0
stw r4, 0x0024(r8)
stw r4, 0x002c(r8)
stw r4, 0x0034(r8)
stw r4, 0x003c(r8)
stw r4, 0x0064(r8)
stw r4, 0x006c(r8)
/* Rev 1 of the 8313 has problems with wakeup events that are
* pending during the transition to deep sleep state (such as if
* the PCI host sets the state to D3 and then D0 in rapid
* succession). This check shrinks the race window somewhat.
*
* See erratum PCI23, though the problem is not limited
* to PCI.
*/
lwz r3, 0x0b04(r8)
andi. r3, r3, 1
bne- mpc83xx_deep_resume
/* Move IMMR back to the default location, following the
* procedure specified in the MPC8313 manual.
*/
lwz r4, IMMRBAR_BASE(r8)
isync
lis r4, DEFAULT_IMMR_VALUE@h
stw r4, IMMRBAR_BASE(r8)
lis r4, KERNELBASE@h
lwz r4, 0(r4)
isync
lwz r4, IMMRBAR_BASE(r9)
mr r8, r9
isync
/* Check the Reset Configuration Word to see whether flash needs
* to be mapped at a low address or a high address.
*/
lwz r4, 0x0904(r8)
andis. r4, r4, 0x0400
li r4, 0
beq boot_low
lis r4, 0xff80
boot_low:
stw r4, 0x0020(r8)
lis r7, 0x8000
ori r7, r7, 0x0016
mfspr r5, SPRN_HID0
rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
oris r5, r5, HID0_SLEEP@h
mtspr SPRN_HID0, r5
isync
mfmsr r5
oris r5, r5, MSR_POW@h
/* Enable the flash mapping at the appropriate address. This
* mapping will override the RAM mapping if booting low, so there's
* no need to disable the latter. This must be done inside the same
* cache line as setting MSR_POW, so that no instruction fetches
* from RAM happen after the flash mapping is turned on.
*/
.align 5
stw r7, 0x0024(r8)
sync
isync
mtmsr r5
isync
1: b 1b
mpc83xx_deep_resume:
lis r4, 1f@h
ori r4, r4, 1f@l
tophys(r4, r4)
mtsrr0 r4
mfmsr r4
rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR)
mtsrr1 r4
rfi
1: tlbia
bl __inval_enable_L1
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
tophys(r3, r3)
lwz r5, SS_MEMSAVE+0(r3)
lwz r6, SS_MEMSAVE+4(r3)
stw r5, 0(0)
stw r6, 4(0)
lwz r5, SS_HID+0(r3)
lwz r6, SS_HID+4(r3)
lwz r7, SS_HID+8(r3)
mtspr SPRN_HID0, r5
mtspr SPRN_HID1, r6
mtspr SPRN_HID2, r7
lwz r4, SS_IABR+0(r3)
lwz r5, SS_IABR+4(r3)
lwz r6, SS_IBCR(r3)
lwz r7, SS_DABR+0(r3)
lwz r8, SS_DABR+4(r3)
lwz r9, SS_DBCR(r3)
mtspr SPRN_IABR, r4
mtspr SPRN_IABR2, r5
mtspr SPRN_IBCR, r6
mtspr SPRN_DABR, r7
mtspr SPRN_DABR2, r8
mtspr SPRN_DBCR, r9
li r4, 0
addi r6, r3, SS_SR-4
1: lwzu r5, 4(r6)
mtsrin r5, r4
addis r4, r4, 0x1000
cmpwi r4, 0
bne 1b
lwz r4, SS_DBAT+0x00(r3)
lwz r5, SS_DBAT+0x04(r3)
lwz r6, SS_DBAT+0x08(r3)
lwz r7, SS_DBAT+0x0c(r3)
mtspr SPRN_DBAT0U, r4
mtspr SPRN_DBAT0L, r5
mtspr SPRN_DBAT1U, r6
mtspr SPRN_DBAT1L, r7
lwz r4, SS_DBAT+0x10(r3)
lwz r5, SS_DBAT+0x14(r3)
lwz r6, SS_DBAT+0x18(r3)
lwz r7, SS_DBAT+0x1c(r3)
mtspr SPRN_DBAT2U, r4
mtspr SPRN_DBAT2L, r5
mtspr SPRN_DBAT3U, r6
mtspr SPRN_DBAT3L, r7
lwz r4, SS_DBAT+0x20(r3)
lwz r5, SS_DBAT+0x24(r3)
lwz r6, SS_DBAT+0x28(r3)
lwz r7, SS_DBAT+0x2c(r3)
mtspr SPRN_DBAT4U, r4
mtspr SPRN_DBAT4L, r5
mtspr SPRN_DBAT5U, r6
mtspr SPRN_DBAT5L, r7
lwz r4, SS_DBAT+0x30(r3)
lwz r5, SS_DBAT+0x34(r3)
lwz r6, SS_DBAT+0x38(r3)
lwz r7, SS_DBAT+0x3c(r3)
mtspr SPRN_DBAT6U, r4
mtspr SPRN_DBAT6L, r5
mtspr SPRN_DBAT7U, r6
mtspr SPRN_DBAT7L, r7
lwz r4, SS_IBAT+0x00(r3)
lwz r5, SS_IBAT+0x04(r3)
lwz r6, SS_IBAT+0x08(r3)
lwz r7, SS_IBAT+0x0c(r3)
mtspr SPRN_IBAT0U, r4
mtspr SPRN_IBAT0L, r5
mtspr SPRN_IBAT1U, r6
mtspr SPRN_IBAT1L, r7
lwz r4, SS_IBAT+0x10(r3)
lwz r5, SS_IBAT+0x14(r3)
lwz r6, SS_IBAT+0x18(r3)
lwz r7, SS_IBAT+0x1c(r3)
mtspr SPRN_IBAT2U, r4
mtspr SPRN_IBAT2L, r5
mtspr SPRN_IBAT3U, r6
mtspr SPRN_IBAT3L, r7
lwz r4, SS_IBAT+0x20(r3)
lwz r5, SS_IBAT+0x24(r3)
lwz r6, SS_IBAT+0x28(r3)
lwz r7, SS_IBAT+0x2c(r3)
mtspr SPRN_IBAT4U, r4
mtspr SPRN_IBAT4L, r5
mtspr SPRN_IBAT5U, r6
mtspr SPRN_IBAT5L, r7
lwz r4, SS_IBAT+0x30(r3)
lwz r5, SS_IBAT+0x34(r3)
lwz r6, SS_IBAT+0x38(r3)
lwz r7, SS_IBAT+0x3c(r3)
mtspr SPRN_IBAT6U, r4
mtspr SPRN_IBAT6L, r5
mtspr SPRN_IBAT7U, r6
mtspr SPRN_IBAT7L, r7
lwz r4, SS_SPRG+0(r3)
lwz r5, SS_SPRG+4(r3)
lwz r6, SS_SPRG+8(r3)
lwz r7, SS_SPRG+12(r3)
lwz r8, SS_SDR1(r3)
mtspr SPRN_SPRG0, r4
mtspr SPRN_SPRG1, r5
mtspr SPRN_SPRG2, r6
mtspr SPRN_SPRG3, r7
mtsdr1 r8
lwz r4, SS_MSR(r3)
lwz r5, SS_LR(r3)
lwz r6, SS_CR(r3)
lwz r1, SS_SP(r3)
lwz r2, SS_R2(r3)
mtsrr1 r4
mtsrr0 r5
mtcr r6
li r4, 0
mtspr SPRN_TBWL, r4
lwz r4, SS_TB+0(r3)
lwz r5, SS_TB+4(r3)
mtspr SPRN_TBWU, r4
mtspr SPRN_TBWL, r5
lmw r12, SS_GPREG(r3)
/* Kick decrementer */
li r0, 1
mtdec r0
rfi

388
arch/powerpc/platforms/83xx/suspend.c Normal file
View File

@ -0,0 +1,388 @@
/*
* MPC83xx suspend support
*
* Author: Scott Wood <scottwood@freescale.com>
*
* Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/types.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <linux/suspend.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <asm/reg.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/mpc6xx.h>
#include <sysdev/fsl_soc.h>
#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
#define PMCCR1_NEXT_STATE_SHIFT 2
#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
#define IMMR_RCW_OFFSET 0x900
#define RCW_PCI_HOST 0x80000000
void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
struct mpc83xx_pmc {
u32 config;
#define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
#define PMCCR_SLPEN 1 /* System low power enable */
u32 event;
u32 mask;
/* All but PMCI are deep-sleep only */
#define PMCER_GPIO 0x100
#define PMCER_PCI 0x080
#define PMCER_USB 0x040
#define PMCER_ETSEC1 0x020
#define PMCER_ETSEC2 0x010
#define PMCER_TIMER 0x008
#define PMCER_INT1 0x004
#define PMCER_INT2 0x002
#define PMCER_PMCI 0x001
#define PMCER_ALL 0x1FF
/* deep-sleep only */
u32 config1;
#define PMCCR1_USE_STATE 0x80000000
#define PMCCR1_PME_EN 0x00000080
#define PMCCR1_ASSERT_PME 0x00000040
#define PMCCR1_POWER_OFF 0x00000020
/* deep-sleep only */
u32 config2;
};
struct mpc83xx_rcw {
u32 rcwlr;
u32 rcwhr;
};
struct mpc83xx_clock {
u32 spmr;
u32 occr;
u32 sccr;
};
struct pmc_type {
int has_deep_sleep;
};
static struct of_device *pmc_dev;
static int has_deep_sleep, deep_sleeping;
static int pmc_irq;
static struct mpc83xx_pmc __iomem *pmc_regs;
static struct mpc83xx_clock __iomem *clock_regs;
static int is_pci_agent, wake_from_pci;
static phys_addr_t immrbase;
static int pci_pm_state;
static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
int fsl_deep_sleep(void)
{
return deep_sleeping;
}
static int mpc83xx_change_state(void)
{
u32 curr_state;
u32 reg_cfg1 = in_be32(&pmc_regs->config1);
if (is_pci_agent) {
pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
PMCCR1_NEXT_STATE_SHIFT;
curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
if (curr_state != pci_pm_state) {
reg_cfg1 &= ~PMCCR1_CURR_STATE;
reg_cfg1 |= pci_pm_state;
out_be32(&pmc_regs->config1, reg_cfg1);
wake_up(&agent_wq);
return 1;
}
}
return 0;
}
static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
{
u32 event = in_be32(&pmc_regs->event);
int ret = IRQ_NONE;
if (mpc83xx_change_state())
ret = IRQ_HANDLED;
if (event) {
out_be32(&pmc_regs->event, event);
ret = IRQ_HANDLED;
}
return ret;
}
static int mpc83xx_suspend_enter(suspend_state_t state)
{
int ret = -EAGAIN;
/* Don't go to sleep if there's a race where pci_pm_state changes
* between the agent thread checking it and the PM code disabling
* interrupts.
*/
if (wake_from_pci) {
if (pci_pm_state != (deep_sleeping ? 3 : 2))
goto out;
out_be32(&pmc_regs->config1,
in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
}
/* Put the system into low-power mode and the RAM
* into self-refresh mode once the core goes to
* sleep.
*/
out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
/* If it has deep sleep (i.e. it's an 831x or compatible),
* disable power to the core upon entering sleep mode. This will
* require going through the boot firmware upon a wakeup event.
*/
if (deep_sleeping) {
out_be32(&pmc_regs->mask, PMCER_ALL);
out_be32(&pmc_regs->config1,
in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
enable_kernel_fp();
mpc83xx_enter_deep_sleep(immrbase);
out_be32(&pmc_regs->config1,
in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
out_be32(&pmc_regs->mask, PMCER_PMCI);
} else {
out_be32(&pmc_regs->mask, PMCER_PMCI);
mpc6xx_enter_standby();
}
ret = 0;
out:
out_be32(&pmc_regs->config1,
in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
return ret;
}
static void mpc83xx_suspend_finish(void)
{
deep_sleeping = 0;
}
static int mpc83xx_suspend_valid(suspend_state_t state)
{
return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
}
static int mpc83xx_suspend_begin(suspend_state_t state)
{
switch (state) {
case PM_SUSPEND_STANDBY:
deep_sleeping = 0;
return 0;
case PM_SUSPEND_MEM:
if (has_deep_sleep)
deep_sleeping = 1;
return 0;
default:
return -EINVAL;
}
}
static int agent_thread_fn(void *data)
{
while (1) {
wait_event_interruptible(agent_wq, pci_pm_state >= 2);
try_to_freeze();
if (signal_pending(current) || pci_pm_state < 2)
continue;
/* With a preemptible kernel (or SMP), this could race with
* a userspace-driven suspend request. It's probably best
* to avoid mixing the two with such a configuration (or
* else fix it by adding a mutex to state_store that we can
* synchronize with).
*/
wake_from_pci = 1;
pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
PM_SUSPEND_STANDBY);
wake_from_pci = 0;
}
return 0;
}
static void mpc83xx_set_agent(void)
{
out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
out_be32(&pmc_regs->mask, PMCER_PMCI);
kthread_run(agent_thread_fn, NULL, "PCI power mgt");
}
static int mpc83xx_is_pci_agent(void)
{
struct mpc83xx_rcw __iomem *rcw_regs;
int ret;
rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
sizeof(struct mpc83xx_rcw));
if (!rcw_regs)
return -ENOMEM;
ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
iounmap(rcw_regs);
return ret;
}
static struct platform_suspend_ops mpc83xx_suspend_ops = {
.valid = mpc83xx_suspend_valid,
.begin = mpc83xx_suspend_begin,
.enter = mpc83xx_suspend_enter,
.finish = mpc83xx_suspend_finish,
};
static int pmc_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct device_node *np = ofdev->node;
struct resource res;
struct pmc_type *type = match->data;
int ret = 0;
if (!of_device_is_available(np))
return -ENODEV;
has_deep_sleep = type->has_deep_sleep;
immrbase = get_immrbase();
pmc_dev = ofdev;
is_pci_agent = mpc83xx_is_pci_agent();
if (is_pci_agent < 0)
return is_pci_agent;
ret = of_address_to_resource(np, 0, &res);
if (ret)
return -ENODEV;
pmc_irq = irq_of_parse_and_map(np, 0);
if (pmc_irq != NO_IRQ) {
ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
"pmc", ofdev);
if (ret)
return -EBUSY;
}
pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
if (!pmc_regs) {
ret = -ENOMEM;
goto out;
}
ret = of_address_to_resource(np, 1, &res);
if (ret) {
ret = -ENODEV;
goto out_pmc;
}
clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
if (!clock_regs) {
ret = -ENOMEM;
goto out_pmc;
}
if (is_pci_agent)
mpc83xx_set_agent();
suspend_set_ops(&mpc83xx_suspend_ops);
return 0;
out_pmc:
iounmap(pmc_regs);
out:
if (pmc_irq != NO_IRQ)
free_irq(pmc_irq, ofdev);
return ret;
}
static int pmc_remove(struct of_device *ofdev)
{
return -EPERM;
};
static struct pmc_type pmc_types[] = {
{
.has_deep_sleep = 1,
},
{
.has_deep_sleep = 0,
}
};
static struct of_device_id pmc_match[] = {
{
.compatible = "fsl,mpc8313-pmc",
.data = &pmc_types[0],
},
{
.compatible = "fsl,mpc8349-pmc",
.data = &pmc_types[1],
},
{}
};
static struct of_platform_driver pmc_driver = {
.name = "mpc83xx-pmc",
.match_table = pmc_match,
.probe = pmc_probe,
.remove = pmc_remove
};
static int pmc_init(void)
{
return of_register_platform_driver(&pmc_driver);
}
module_init(pmc_init);

24
arch/powerpc/platforms/83xx/usb.c
View File

@ -137,15 +137,21 @@ int mpc831x_usb_cfg(void)
/* Configure pin mux for ULPI. There is no pin mux for UTMI */
if (prop && !strcmp(prop, "ulpi")) {
temp = in_be32(immap + MPC83XX_SICRL_OFFS);
temp &= ~MPC831X_SICRL_USB_MASK;
temp |= MPC831X_SICRL_USB_ULPI;
out_be32(immap + MPC83XX_SICRL_OFFS, temp);
temp = in_be32(immap + MPC83XX_SICRH_OFFS);
temp &= ~MPC831X_SICRH_USB_MASK;
temp |= MPC831X_SICRH_USB_ULPI;
out_be32(immap + MPC83XX_SICRH_OFFS, temp);
if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
MPC8315_SICRL_USB_MASK,
MPC8315_SICRL_USB_ULPI);
clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
MPC8315_SICRH_USB_MASK,
MPC8315_SICRH_USB_ULPI);
} else {
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
MPC831X_SICRL_USB_MASK,
MPC831X_SICRL_USB_ULPI);
clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
MPC831X_SICRH_USB_MASK,
MPC831X_SICRH_USB_ULPI);
}
}
iounmap(immap);

3
arch/powerpc/platforms/85xx/Kconfig
View File

@ -2,8 +2,8 @@ menuconfig MPC85xx
bool "Machine Type"
depends on PPC_85xx
select PPC_UDBG_16550
select PPC_INDIRECT_PCI if PCI
select MPIC
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y
@ -86,7 +86,6 @@ config TQM8548
help
This option enables support for the TQ Components TQM8548 board.
select DEFAULT_UIMAGE
select PPC_CPM_NEW_BINDING
select TQM85xx
config TQM8555

2
arch/powerpc/platforms/85xx/mpc85xx_ds.c
View File

@ -115,7 +115,6 @@ void __init mpc85xx_ds_pic_init(void)
#ifdef CONFIG_PCI
static int primary_phb_addr;
extern int uses_fsl_uli_m1575;
extern int uli_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
@ -161,7 +160,6 @@ static void __init mpc85xx_ds_setup_arch(void)
}
}
uses_fsl_uli_m1575 = 1;
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif

3
arch/powerpc/platforms/86xx/Kconfig
View File

@ -27,6 +27,7 @@ config SBC8641D
config MPC8610_HPCD
bool "Freescale MPC8610 HPCD"
select DEFAULT_UIMAGE
select FSL_ULI1575
help
This option enables support for the MPC8610 HPCD board.
@ -34,6 +35,7 @@ endif
config MPC8641
bool
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
@ -41,6 +43,7 @@ config MPC8641
config MPC8610
bool
select PPC_PCI_CHOICE
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC

87
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
View File

@ -58,93 +58,6 @@ static int __init mpc8610_declare_of_platform_devices(void)
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
#ifdef CONFIG_PCI
static void __devinit quirk_uli1575(struct pci_dev *dev)
{
u32 temp32;
/* Disable INTx */
pci_read_config_dword(dev, 0x48, &temp32);
pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
/* Enable sideband interrupt */
pci_read_config_dword(dev, 0x90, &temp32);
pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
}
static void __devinit quirk_uli5288(struct pci_dev *dev)
{
unsigned char c;
unsigned short temp;
/* Interrupt Disable, Needed when SATA disabled */
pci_read_config_word(dev, PCI_COMMAND, &temp);
temp |= 1<<10;
pci_write_config_word(dev, PCI_COMMAND, temp);
pci_read_config_byte(dev, 0x83, &c);
c |= 0x80;
pci_write_config_byte(dev, 0x83, c);
pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
pci_read_config_byte(dev, 0x83, &c);
c &= 0x7f;
pci_write_config_byte(dev, 0x83, c);
}
/*
* Since 8259PIC was disabled on the board, the IDE device can not
* use the legacy IRQ, we need to let the IDE device work under
* native mode and use the interrupt line like other PCI devices.
* IRQ14 is a sideband interrupt from IDE device to CPU and we use this
* as the interrupt for IDE device.
*/
static void __devinit quirk_uli5229(struct pci_dev *dev)
{
unsigned char c;
pci_read_config_byte(dev, 0x4b, &c);
c |= 0x10;
pci_write_config_byte(dev, 0x4b, c);
}
/*
* SATA interrupt pin bug fix
* There's a chip bug for 5288, The interrupt pin should be 2,
* not the read only value 1, So it use INTB#, not INTA# which
* actually used by the IDE device 5229.
* As of this bug, during the PCI initialization, 5288 read the
* irq of IDE device from the device tree, this function fix this
* bug by re-assigning a correct irq to 5288.
*
*/
static void __devinit final_uli5288(struct pci_dev *dev)
{
struct pci_controller *hose = pci_bus_to_host(dev->bus);
struct device_node *hosenode = hose ? hose->dn : NULL;
struct of_irq oirq;
int virq, pin = 2;
u32 laddr[3];
if (!hosenode)
return;
laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
laddr[1] = laddr[2] = 0;
of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
oirq.size);
dev->irq = virq;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
#endif /* CONFIG_PCI */
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
static u32 get_busfreq(void)

2
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
View File

@ -45,7 +45,6 @@
#endif
#ifdef CONFIG_PCI
extern int uses_fsl_uli_m1575;
extern int uli_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
@ -87,7 +86,6 @@ mpc86xx_hpcn_setup_arch(void)
fsl_add_bridge(np, 0);
}
uses_fsl_uli_m1575 = 1;
ppc_md.pci_exclude_device = mpc86xx_exclude_device;
#endif

6
arch/powerpc/platforms/Kconfig
View File

@ -253,17 +253,13 @@ config CPM2
depends on MPC85xx || 8260
select CPM
select PPC_LIB_RHEAP
select PPC_PCI_CHOICE
help
The CPM2 (Communications Processor Module) is a coprocessor on
embedded CPUs made by Freescale. Selecting this option means that
you wish to build a kernel for a machine with a CPM2 coprocessor
on it (826x, 827x, 8560).
config PPC_CPM_NEW_BINDING
bool
depends on CPM1 || CPM2
default y
config AXON_RAM
tristate "Axon DDR2 memory device driver"
depends on PPC_IBM_CELL_BLADE

5
arch/powerpc/platforms/Kconfig.cputype
View File

@ -42,12 +42,14 @@ config 40x
select PPC_DCR_NATIVE
select PPC_UDBG_16550
select 4xx_SOC
select PPC_PCI_CHOICE
config 44x
bool "AMCC 44x"
select PPC_DCR_NATIVE
select PPC_UDBG_16550
select 4xx_SOC
select PPC_PCI_CHOICE
config E200
bool "Freescale e200"
@ -84,9 +86,6 @@ config TUNE_CELL
machines. When building a kernel that is supposed to run only
on Cell, you should also select the POWER4_ONLY option.
config 6xx
bool
# this is temp to handle compat with arch=ppc
config 8xx
bool

25
arch/powerpc/platforms/cell/Kconfig
View File

@ -83,6 +83,22 @@ config CBE_RAS
depends on PPC_CELL_NATIVE
default y
config PPC_IBM_CELL_RESETBUTTON
bool "IBM Cell Blade Pinhole reset button"
depends on CBE_RAS && PPC_IBM_CELL_BLADE
default y
help
Support Pinhole Resetbutton on IBM Cell blades.
This adds a method to trigger system reset via front panel pinhole button.
config PPC_IBM_CELL_POWERBUTTON
tristate "IBM Cell Blade power button"
depends on PPC_IBM_CELL_BLADE && PPC_PMI && INPUT_EVDEV
default y
help
Support Powerbutton on IBM Cell blades.
This will enable the powerbutton as an input device.
config CBE_THERM
tristate "CBE thermal support"
default m
@ -107,6 +123,15 @@ config CBE_CPUFREQ_PMI
processor will not only be able to run at lower speed,
but also at lower core voltage.
config CBE_CPUFREQ_SPU_GOVERNOR
tristate "CBE frequency scaling based on SPU usage"
depends on SPU_FS && CPU_FREQ
default m
help
This governor checks for spu usage to adjust the cpu frequency.
If no spu is running on a given cpu, that cpu will be throttled to
the minimal possible frequency.
endmenu
config OPROFILE_CELL

3
arch/powerpc/platforms/cell/Makefile
View File

@ -8,6 +8,9 @@ obj-$(CONFIG_CBE_THERM) += cbe_thermal.o
obj-$(CONFIG_CBE_CPUFREQ_PMI) += cbe_cpufreq_pmi.o
obj-$(CONFIG_CBE_CPUFREQ) += cbe-cpufreq.o
cbe-cpufreq-y += cbe_cpufreq_pervasive.o cbe_cpufreq.o
obj-$(CONFIG_CBE_CPUFREQ_SPU_GOVERNOR) += cpufreq_spudemand.o
obj-$(CONFIG_PPC_IBM_CELL_POWERBUTTON) += cbe_powerbutton.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_CELL_NATIVE) += smp.o

117
arch/powerpc/platforms/cell/cbe_powerbutton.c Normal file
View File

@ -0,0 +1,117 @@
/*
* driver for powerbutton on IBM cell blades
*
* (C) Copyright IBM Corp. 2005-2008
*
* Author: Christian Krafft <krafft@de.ibm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/input.h>
#include <linux/platform_device.h>
#include <asm/pmi.h>
#include <asm/prom.h>
static struct input_dev *button_dev;
static struct platform_device *button_pdev;
static void cbe_powerbutton_handle_pmi(pmi_message_t pmi_msg)
{
BUG_ON(pmi_msg.type != PMI_TYPE_POWER_BUTTON);
input_report_key(button_dev, KEY_POWER, 1);
input_sync(button_dev);
input_report_key(button_dev, KEY_POWER, 0);
input_sync(button_dev);
}
static struct pmi_handler cbe_pmi_handler = {
.type = PMI_TYPE_POWER_BUTTON,
.handle_pmi_message = cbe_powerbutton_handle_pmi,
};
static int __init cbe_powerbutton_init(void)
{
int ret = 0;
struct input_dev *dev;
if (!machine_is_compatible("IBM,CBPLUS-1.0")) {
printk(KERN_ERR "%s: Not a cell blade.\n", __func__);
ret = -ENODEV;
goto out;
}
dev = input_allocate_device();
if (!dev) {
ret = -ENOMEM;
printk(KERN_ERR "%s: Not enough memory.\n", __func__);
goto out;
}
set_bit(EV_KEY, dev->evbit);
set_bit(KEY_POWER, dev->keybit);
dev->name = "Power Button";
dev->id.bustype = BUS_HOST;
/* this makes the button look like an acpi power button
* no clue whether anyone relies on that though */
dev->id.product = 0x02;
dev->phys = "LNXPWRBN/button/input0";
button_pdev = platform_device_register_simple("power_button", 0, NULL, 0);
if (IS_ERR(button_pdev)) {
ret = PTR_ERR(button_pdev);
goto out_free_input;
}
dev->dev.parent = &button_pdev->dev;
ret = input_register_device(dev);
if (ret) {
printk(KERN_ERR "%s: Failed to register device\n", __func__);
goto out_free_pdev;
}
button_dev = dev;
ret = pmi_register_handler(&cbe_pmi_handler);
if (ret) {
printk(KERN_ERR "%s: Failed to register with pmi.\n", __func__);
goto out_free_pdev;
}
goto out;
out_free_pdev:
platform_device_unregister(button_pdev);
out_free_input:
input_free_device(dev);
out:
return ret;
}
static void __exit cbe_powerbutton_exit(void)
{
pmi_unregister_handler(&cbe_pmi_handler);
platform_device_unregister(button_pdev);
input_free_device(button_dev);
}
module_init(cbe_powerbutton_init);
module_exit(cbe_powerbutton_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");

184
arch/powerpc/platforms/cell/cpufreq_spudemand.c Normal file
View File

@ -0,0 +1,184 @@
/*
* spu aware cpufreq governor for the cell processor
*
* © Copyright IBM Corporation 2006-2008
*
* Author: Christian Krafft <krafft@de.ibm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/cpufreq.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/workqueue.h>
#include <asm/atomic.h>
#include <asm/machdep.h>
#include <asm/spu.h>
#define POLL_TIME 100000 /* in µs */
#define EXP 753 /* exp(-1) in fixed-point */
struct spu_gov_info_struct {
unsigned long busy_spus; /* fixed-point */
struct cpufreq_policy *policy;
struct delayed_work work;
unsigned int poll_int; /* µs */
};
static DEFINE_PER_CPU(struct spu_gov_info_struct, spu_gov_info);
static struct workqueue_struct *kspugov_wq;
static int calc_freq(struct spu_gov_info_struct *info)
{
int cpu;
int busy_spus;
cpu = info->policy->cpu;
busy_spus = atomic_read(&cbe_spu_info[cpu_to_node(cpu)].busy_spus);
CALC_LOAD(info->busy_spus, EXP, busy_spus * FIXED_1);
pr_debug("cpu %d: busy_spus=%d, info->busy_spus=%ld\n",
cpu, busy_spus, info->busy_spus);
return info->policy->max * info->busy_spus / FIXED_1;
}
static void spu_gov_work(struct work_struct *work)
{
struct spu_gov_info_struct *info;
int delay;
unsigned long target_freq;
info = container_of(work, struct spu_gov_info_struct, work.work);
/* after cancel_delayed_work_sync we unset info->policy */
BUG_ON(info->policy == NULL);
target_freq = calc_freq(info);
__cpufreq_driver_target(info->policy, target_freq, CPUFREQ_RELATION_H);
delay = usecs_to_jiffies(info->poll_int);
queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
}
static void spu_gov_init_work(struct spu_gov_info_struct *info)
{
int delay = usecs_to_jiffies(info->poll_int);
INIT_DELAYED_WORK_DEFERRABLE(&info->work, spu_gov_work);
queue_delayed_work_on(info->policy->cpu, kspugov_wq, &info->work, delay);
}
static void spu_gov_cancel_work(struct spu_gov_info_struct *info)
{
cancel_delayed_work_sync(&info->work);
}
static int spu_gov_govern(struct cpufreq_policy *policy, unsigned int event)
{
unsigned int cpu = policy->cpu;
struct spu_gov_info_struct *info, *affected_info;
int i;
int ret = 0;
info = &per_cpu(spu_gov_info, cpu);
switch (event) {
case CPUFREQ_GOV_START:
if (!cpu_online(cpu)) {
printk(KERN_ERR "cpu %d is not online\n", cpu);
ret = -EINVAL;
break;
}
if (!policy->cur) {
printk(KERN_ERR "no cpu specified in policy\n");
ret = -EINVAL;
break;
}
/* initialize spu_gov_info for all affected cpus */
for_each_cpu_mask(i, policy->cpus) {
affected_info = &per_cpu(spu_gov_info, i);
affected_info->policy = policy;
}
info->poll_int = POLL_TIME;
/* setup timer */
spu_gov_init_work(info);
break;
case CPUFREQ_GOV_STOP:
/* cancel timer */
spu_gov_cancel_work(info);
/* clean spu_gov_info for all affected cpus */
for_each_cpu_mask (i, policy->cpus) {
info = &per_cpu(spu_gov_info, i);
info->policy = NULL;
}
break;
}
return ret;
}
static struct cpufreq_governor spu_governor = {
.name = "spudemand",
.governor = spu_gov_govern,
.owner = THIS_MODULE,
};
/*
* module init and destoy
*/
static int __init spu_gov_init(void)
{
int ret;
kspugov_wq = create_workqueue("kspugov");
if (!kspugov_wq) {
printk(KERN_ERR "creation of kspugov failed\n");
ret = -EFAULT;
goto out;
}
ret = cpufreq_register_governor(&spu_governor);
if (ret) {
printk(KERN_ERR "registration of governor failed\n");
destroy_workqueue(kspugov_wq);
goto out;
}
out:
return ret;
}
static void __exit spu_gov_exit(void)
{
cpufreq_unregister_governor(&spu_governor);
destroy_workqueue(kspugov_wq);
}
module_init(spu_gov_init);
module_exit(spu_gov_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");

118
arch/powerpc/platforms/cell/iommu.c
View File

@ -173,7 +173,8 @@ static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
}
static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
unsigned long uaddr, enum dma_data_direction direction)
unsigned long uaddr, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
int i;
unsigned long *io_pte, base_pte;
@ -198,6 +199,8 @@ static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
(window->ioid & IOPTE_IOID_Mask);
#endif
if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
base_pte &= ~IOPTE_SO_RW;
io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
@ -519,7 +522,7 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
__set_bit(0, window->table.it_map);
tce_build_cell(&window->table, window->table.it_offset, 1,
(unsigned long)iommu->pad_page, DMA_TO_DEVICE);
(unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
window->table.it_hint = window->table.it_blocksize;
return window;
@ -538,7 +541,9 @@ static struct cbe_iommu *cell_iommu_for_node(int nid)
static unsigned long cell_dma_direct_offset;
static unsigned long dma_iommu_fixed_base;
struct dma_mapping_ops dma_iommu_fixed_ops;
/* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
static int iommu_fixed_is_weak;
static struct iommu_table *cell_get_iommu_table(struct device *dev)
{
@ -562,6 +567,98 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
return &window->table;
}
/* A coherent allocation implies strong ordering */
static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag)
{
if (iommu_fixed_is_weak)
return iommu_alloc_coherent(dev, cell_get_iommu_table(dev),
size, dma_handle,
device_to_mask(dev), flag,
dev->archdata.numa_node);
else
return dma_direct_ops.alloc_coherent(dev, size, dma_handle,
flag);
}
static void dma_fixed_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
if (iommu_fixed_is_weak)
iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
dma_handle);
else
dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle);
}
static dma_addr_t dma_fixed_map_single(struct device *dev, void *ptr,
size_t size,
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
return dma_direct_ops.map_single(dev, ptr, size, direction,
attrs);
else
return iommu_map_single(dev, cell_get_iommu_table(dev), ptr,
size, device_to_mask(dev), direction,
attrs);
}
static void dma_fixed_unmap_single(struct device *dev, dma_addr_t dma_addr,
size_t size,
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
dma_direct_ops.unmap_single(dev, dma_addr, size, direction,
attrs);
else
iommu_unmap_single(cell_get_iommu_table(dev), dma_addr, size,
direction, attrs);
}
static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
else
return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents,
device_to_mask(dev), direction, attrs);
}
static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
else
iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction,
attrs);
}
static int dma_fixed_dma_supported(struct device *dev, u64 mask)
{
return mask == DMA_64BIT_MASK;
}
static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
struct dma_mapping_ops dma_iommu_fixed_ops = {
.alloc_coherent = dma_fixed_alloc_coherent,
.free_coherent = dma_fixed_free_coherent,
.map_single = dma_fixed_map_single,
.unmap_single = dma_fixed_unmap_single,
.map_sg = dma_fixed_map_sg,
.unmap_sg = dma_fixed_unmap_sg,
.dma_supported = dma_fixed_dma_supported,
.set_dma_mask = dma_set_mask_and_switch,
};
static void cell_dma_dev_setup_fixed(struct device *dev);
static void cell_dma_dev_setup(struct device *dev)
@ -918,9 +1015,16 @@ static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW
base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M
| (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask);
if (iommu_fixed_is_weak)
pr_info("IOMMU: Using weak ordering for fixed mapping\n");
else {
pr_info("IOMMU: Using strong ordering for fixed mapping\n");
base_pte |= IOPTE_SO_RW;
}
for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
/* Don't touch the dynamic region */
ioaddr = uaddr + fbase;
@ -1036,9 +1140,6 @@ static int __init cell_iommu_fixed_mapping_init(void)
cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
}
dma_iommu_fixed_ops = dma_direct_ops;
dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch;
dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
set_pci_dma_ops(&dma_iommu_ops);
@ -1052,6 +1153,9 @@ static int __init setup_iommu_fixed(char *str)
if (strcmp(str, "off") == 0)
iommu_fixed_disabled = 1;
else if (strcmp(str, "weak") == 0)
iommu_fixed_is_weak = 1;
return 1;
}
__setup("iommu_fixed=", setup_iommu_fixed);

27
arch/powerpc/platforms/cell/pervasive.c
View File

@ -38,8 +38,6 @@
#include "pervasive.h"
static int sysreset_hack;
static void cbe_power_save(void)
{
unsigned long ctrl, thread_switch_control;
@ -87,9 +85,6 @@ static void cbe_power_save(void)
static int cbe_system_reset_exception(struct pt_regs *regs)
{
int cpu;
struct cbe_pmd_regs __iomem *pmd;
switch (regs->msr & SRR1_WAKEMASK) {
case SRR1_WAKEEE:
do_IRQ(regs);
@ -98,19 +93,7 @@ static int cbe_system_reset_exception(struct pt_regs *regs)
timer_interrupt(regs);
break;
case SRR1_WAKEMT:
/*
* The BMC can inject user triggered system reset exceptions,
* but cannot set the system reset reason in srr1,
* so check an extra register here.
*/
if (sysreset_hack && (cpu = smp_processor_id()) == 0) {
pmd = cbe_get_cpu_pmd_regs(cpu);
if (in_be64(&pmd->ras_esc_0) & 0xffff) {
out_be64(&pmd->ras_esc_0, 0);
return 0;
}
}
break;
return cbe_sysreset_hack();
#ifdef CONFIG_CBE_RAS
case SRR1_WAKESYSERR:
cbe_system_error_exception(regs);
@ -134,8 +117,6 @@ void __init cbe_pervasive_init(void)
if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
return;
sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
for_each_possible_cpu(cpu) {
struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
if (!regs)
@ -144,12 +125,6 @@ void __init cbe_pervasive_init(void)
/* Enable Pause(0) control bit */
out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
CBE_PMD_PAUSE_ZERO_CONTROL);
/* Enable JTAG system-reset hack */
if (sysreset_hack)
out_be32(&regs->fir_mode_reg,
in_be32(&regs->fir_mode_reg) |
CBE_PMD_FIR_MODE_M8);
}
ppc_md.power_save = cbe_power_save;

9
arch/powerpc/platforms/cell/pervasive.h
View File

@ -30,4 +30,13 @@ extern void cbe_system_error_exception(struct pt_regs *regs);
extern void cbe_maintenance_exception(struct pt_regs *regs);
extern void cbe_thermal_exception(struct pt_regs *regs);
#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
extern int cbe_sysreset_hack(void);
#else
static inline int cbe_sysreset_hack(void)
{
return 1;
}
#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
#endif

46
arch/powerpc/platforms/cell/ras.c
View File

@ -236,6 +236,52 @@ static struct notifier_block cbe_ptcal_reboot_notifier = {
.notifier_call = cbe_ptcal_notify_reboot
};
#ifdef CONFIG_PPC_IBM_CELL_RESETBUTTON
static int sysreset_hack;
static int __init cbe_sysreset_init(void)
{
struct cbe_pmd_regs __iomem *regs;
sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
if (!sysreset_hack)
return 0;
regs = cbe_get_cpu_pmd_regs(0);
if (!regs)
return 0;
/* Enable JTAG system-reset hack */
out_be32(&regs->fir_mode_reg,
in_be32(&regs->fir_mode_reg) |
CBE_PMD_FIR_MODE_M8);
return 0;
}
device_initcall(cbe_sysreset_init);
int cbe_sysreset_hack(void)
{
struct cbe_pmd_regs __iomem *regs;
/*
* The BMC can inject user triggered system reset exceptions,
* but cannot set the system reset reason in srr1,
* so check an extra register here.
*/
if (sysreset_hack && (smp_processor_id() == 0)) {
regs = cbe_get_cpu_pmd_regs(0);
if (!regs)
return 0;
if (in_be64(&regs->ras_esc_0) & 0x0000ffff) {
out_be64(&regs->ras_esc_0, 0);
return 0;
}
}
return 1;
}
#endif /* CONFIG_PPC_IBM_CELL_RESETBUTTON */
int __init cbe_ptcal_init(void)
{
int ret;

117
arch/powerpc/platforms/fsl_uli1575.c
View File

@ -51,15 +51,13 @@ u8 uli_pirq_to_irq[8] = {
ULI_8259_NONE, /* PIRQH */
};
/* set in board code if you want this quirks to do something */
int uses_fsl_uli_m1575;
/* Bridge */
static void __devinit early_uli5249(struct pci_dev *dev)
{
unsigned char temp;
if (!uses_fsl_uli_m1575)
if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
!machine_is(mpc8572_ds))
return;
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
@ -82,7 +80,8 @@ static void __devinit quirk_uli1575(struct pci_dev *dev)
{
int i;
if (!uses_fsl_uli_m1575)
if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
!machine_is(mpc8572_ds))
return;
/*
@ -150,7 +149,8 @@ static void __devinit quirk_final_uli1575(struct pci_dev *dev)
* IRQ 14: Edge
* IRQ 15: Edge
*/
if (!uses_fsl_uli_m1575)
if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
!machine_is(mpc8572_ds))
return;
outb(0xfa, 0x4d0);
@ -176,7 +176,8 @@ static void __devinit quirk_uli5288(struct pci_dev *dev)
unsigned char c;
unsigned int d;
if (!uses_fsl_uli_m1575)
if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
!machine_is(mpc8572_ds))
return;
/* read/write lock */
@ -200,7 +201,8 @@ static void __devinit quirk_uli5229(struct pci_dev *dev)
{
unsigned short temp;
if (!uses_fsl_uli_m1575)
if (!machine_is(mpc86xx_hpcn) && !machine_is(mpc8544_ds) &&
!machine_is(mpc8572_ds))
return;
pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
@ -221,7 +223,7 @@ static void __devinit quirk_final_uli5249(struct pci_dev *dev)
for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
if ((bus->resource[i]) &&
(bus->resource[i]->flags & IORESOURCE_MEM)) {
dummy = ioremap(bus->resource[i]->start, 0x4);
dummy = ioremap(bus->resource[i]->end - 3, 0x4);
if (dummy) {
in_8(dummy);
iounmap(dummy);
@ -238,6 +240,103 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
static void __devinit hpcd_quirk_uli1575(struct pci_dev *dev)
{
u32 temp32;
if (!machine_is(mpc86xx_hpcd))
return;
/* Disable INTx */
pci_read_config_dword(dev, 0x48, &temp32);
pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
/* Enable sideband interrupt */
pci_read_config_dword(dev, 0x90, &temp32);
pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
}
static void __devinit hpcd_quirk_uli5288(struct pci_dev *dev)
{
unsigned char c;
unsigned short temp;
if (!machine_is(mpc86xx_hpcd))
return;
/* Interrupt Disable, Needed when SATA disabled */
pci_read_config_word(dev, PCI_COMMAND, &temp);
temp |= 1<<10;
pci_write_config_word(dev, PCI_COMMAND, temp);
pci_read_config_byte(dev, 0x83, &c);
c |= 0x80;
pci_write_config_byte(dev, 0x83, c);
pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
pci_read_config_byte(dev, 0x83, &c);
c &= 0x7f;
pci_write_config_byte(dev, 0x83, c);
}
/*
* Since 8259PIC was disabled on the board, the IDE device can not
* use the legacy IRQ, we need to let the IDE device work under
* native mode and use the interrupt line like other PCI devices.
* IRQ14 is a sideband interrupt from IDE device to CPU and we use this
* as the interrupt for IDE device.
*/
static void __devinit hpcd_quirk_uli5229(struct pci_dev *dev)
{
unsigned char c;
if (!machine_is(mpc86xx_hpcd))
return;
pci_read_config_byte(dev, 0x4b, &c);
c |= 0x10;
pci_write_config_byte(dev, 0x4b, c);
}
/*
* SATA interrupt pin bug fix
* There's a chip bug for 5288, The interrupt pin should be 2,
* not the read only value 1, So it use INTB#, not INTA# which
* actually used by the IDE device 5229.
* As of this bug, during the PCI initialization, 5288 read the
* irq of IDE device from the device tree, this function fix this
* bug by re-assigning a correct irq to 5288.
*
*/
static void __devinit hpcd_final_uli5288(struct pci_dev *dev)
{
struct pci_controller *hose = pci_bus_to_host(dev->bus);
struct device_node *hosenode = hose ? hose->dn : NULL;
struct of_irq oirq;
int virq, pin = 2;
u32 laddr[3];
if (!machine_is(mpc86xx_hpcd))
return;
if (!hosenode)
return;
laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
laddr[1] = laddr[2] = 0;
of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
oirq.size);
dev->irq = virq;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
int uli_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn)
{

1
arch/powerpc/platforms/iseries/Kconfig
View File

@ -2,6 +2,7 @@ config PPC_ISERIES
bool "IBM Legacy iSeries"
depends on PPC_MULTIPLATFORM && PPC64
select PPC_INDIRECT_IO
select PPC_PCI_CHOICE if EMBEDDED
menu "iSeries device drivers"
depends on PPC_ISERIES

3
arch/powerpc/platforms/iseries/iommu.c
View File

@ -42,7 +42,8 @@
#include <asm/iseries/iommu.h>
static void tce_build_iSeries(struct iommu_table *tbl, long index, long npages,
unsigned long uaddr, enum dma_data_direction direction)
unsigned long uaddr, enum dma_data_direction direction,
struct dma_attrs *attrs)
{
u64 rc;
u64 tce, rpn;

3
arch/powerpc/platforms/pasemi/iommu.c
View File

@ -85,7 +85,8 @@ static int iommu_table_iobmap_inited;
static void iobmap_build(struct iommu_table *tbl, long index,
long npages, unsigned long uaddr,
enum dma_data_direction direction)
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
u32 *ip;
u32 rpn;

1
arch/powerpc/platforms/ps3/Kconfig
View File

@ -8,6 +8,7 @@ config PPC_PS3
select USB_ARCH_HAS_EHCI
select USB_EHCI_BIG_ENDIAN_MMIO
select MEMORY_HOTPLUG
select PPC_PCI_CHOICE
help
This option enables support for the Sony PS3 game console
and other platforms using the PS3 hypervisor. Enabling this

1
arch/powerpc/platforms/ps3/device-init.c
View File

@ -486,6 +486,7 @@ static int __init ps3_register_graphics_devices(void)
return -ENOMEM;
p->dev.match_id = PS3_MATCH_ID_GRAPHICS;
p->dev.match_sub_id = PS3_MATCH_SUB_ID_FB;
p->dev.dev_type = PS3_DEVICE_TYPE_IOC0;
result = ps3_system_bus_device_register(&p->dev);

21
arch/powerpc/platforms/ps3/system-bus.c
View File

@ -347,16 +347,23 @@ static int ps3_system_bus_match(struct device *_dev,
struct ps3_system_bus_driver *drv = ps3_drv_to_system_bus_drv(_drv);
struct ps3_system_bus_device *dev = ps3_dev_to_system_bus_dev(_dev);
result = dev->match_id == drv->match_id;
if (!dev->match_sub_id)
result = dev->match_id == drv->match_id;
else
result = dev->match_sub_id == drv->match_sub_id &&
dev->match_id == drv->match_id;
if (result)
pr_info("%s:%d: dev=%u(%s), drv=%u(%s): match\n", __func__,
__LINE__, dev->match_id, dev->core.bus_id,
drv->match_id, drv->core.name);
pr_info("%s:%d: dev=%u.%u(%s), drv=%u.%u(%s): match\n",
__func__, __LINE__,
dev->match_id, dev->match_sub_id, dev->core.bus_id,
drv->match_id, drv->match_sub_id, drv->core.name);
else
pr_debug("%s:%d: dev=%u(%s), drv=%u(%s): miss\n", __func__,
__LINE__, dev->match_id, dev->core.bus_id,
drv->match_id, drv->core.name);
pr_debug("%s:%d: dev=%u.%u(%s), drv=%u.%u(%s): miss\n",
__func__, __LINE__,
dev->match_id, dev->match_sub_id, dev->core.bus_id,
drv->match_id, drv->match_sub_id, drv->core.name);
return result;
}

1
arch/powerpc/platforms/pseries/Kconfig
View File

@ -7,6 +7,7 @@ config PPC_PSERIES
select RTAS_ERROR_LOGGING
select PPC_UDBG_16550
select PPC_NATIVE
select PPC_PCI_CHOICE if EMBEDDED
default y
config PPC_SPLPAR

26
arch/powerpc/platforms/pseries/eeh.c
View File

@ -75,9 +75,9 @@
*/
/* If a device driver keeps reading an MMIO register in an interrupt
* handler after a slot isolation event has occurred, we assume it
* is broken and panic. This sets the threshold for how many read
* attempts we allow before panicking.
* handler after a slot isolation event, it might be broken.
* This sets the threshold for how many read attempts we allow
* before printing an error message.
*/
#define EEH_MAX_FAILS 2100000
@ -470,6 +470,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
unsigned long flags;
struct pci_dn *pdn;
int rc = 0;
const char *location;
total_mmio_ffs++;
@ -509,18 +510,15 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
rc = 1;
if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
pdn->eeh_check_count ++;
if (pdn->eeh_check_count >= EEH_MAX_FAILS) {
printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n",
pdn->eeh_check_count);
if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
location = of_get_property(dn, "ibm,loc-code", NULL);
printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
"location=%s driver=%s pci addr=%s\n",
pdn->eeh_check_count, location,
dev->driver->name, pci_name(dev));
printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
dev->driver->name);
dump_stack();
msleep(5000);
/* re-read the slot reset state */
if (read_slot_reset_state(pdn, rets) != 0)
rets[0] = -1; /* reset state unknown */
/* If we are here, then we hit an infinite loop. Stop. */
panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev));
}
goto dn_unlock;
}

14
arch/powerpc/platforms/pseries/iommu.c
View File

@ -50,7 +50,8 @@
static void tce_build_pSeries(struct iommu_table *tbl, long index,
long npages, unsigned long uaddr,
enum dma_data_direction direction)
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
u64 proto_tce;
u64 *tcep;
@ -95,7 +96,8 @@ static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
long npages, unsigned long uaddr,
enum dma_data_direction direction)
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
u64 rc;
u64 proto_tce, tce;
@ -127,7 +129,8 @@ static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
long npages, unsigned long uaddr,
enum dma_data_direction direction)
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
u64 rc;
u64 proto_tce;
@ -136,7 +139,8 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
long l, limit;
if (npages == 1) {
tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, direction);
tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
direction, attrs);
return;
}
@ -150,7 +154,7 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
/* If allocation fails, fall back to the loop implementation */
if (!tcep) {
tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
direction);
direction, attrs);
return;
}
__get_cpu_var(tce_page) = tcep;

28
arch/powerpc/sysdev/axonram.c
View File

@ -57,6 +57,8 @@
#define AXON_RAM_SECTOR_SIZE 1 << AXON_RAM_SECTOR_SHIFT
#define AXON_RAM_IRQ_FLAGS IRQF_SHARED | IRQF_TRIGGER_RISING
static int azfs_major, azfs_minor;
struct axon_ram_bank {
struct of_device *device;
struct gendisk *disk;
@ -148,7 +150,10 @@ axon_ram_direct_access(struct block_device *device, sector_t sector,
struct axon_ram_bank *bank = device->bd_disk->private_data;
loff_t offset;
offset = sector << AXON_RAM_SECTOR_SHIFT;
offset = sector;
if (device->bd_part != NULL)
offset += device->bd_part->start_sect;
offset <<= AXON_RAM_SECTOR_SHIFT;
if (offset >= bank->size) {
dev_err(&bank->device->dev, "Access outside of address space\n");
return -ERANGE;
@ -227,19 +232,14 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id)
goto failed;
}
bank->disk->first_minor = 0;
bank->disk->major = azfs_major;
bank->disk->first_minor = azfs_minor;
bank->disk->fops = &axon_ram_devops;
bank->disk->private_data = bank;
bank->disk->driverfs_dev = &device->dev;
sprintf(bank->disk->disk_name, "%s%d",
AXON_RAM_DEVICE_NAME, axon_ram_bank_id);
bank->disk->major = register_blkdev(0, bank->disk->disk_name);
if (bank->disk->major < 0) {
dev_err(&device->dev, "Cannot register block device\n");
rc = -EFAULT;
goto failed;
}
bank->disk->queue = blk_alloc_queue(GFP_KERNEL);
if (bank->disk->queue == NULL) {
@ -276,6 +276,8 @@ axon_ram_probe(struct of_device *device, const struct of_device_id *device_id)
goto failed;
}
azfs_minor += bank->disk->minors;
return 0;
failed:
@ -310,7 +312,6 @@ axon_ram_remove(struct of_device *device)
device_remove_file(&device->dev, &dev_attr_ecc);
free_irq(bank->irq_id, device);
unregister_blkdev(bank->disk->major, bank->disk->disk_name);
del_gendisk(bank->disk);
iounmap((void __iomem *) bank->io_addr);
kfree(bank);
@ -341,6 +342,14 @@ static struct of_platform_driver axon_ram_driver = {
static int __init
axon_ram_init(void)
{
azfs_major = register_blkdev(azfs_major, AXON_RAM_DEVICE_NAME);
if (azfs_major < 0) {
printk(KERN_ERR "%s cannot become block device major number\n",
AXON_RAM_MODULE_NAME);
return -EFAULT;
}
azfs_minor = 0;
return of_register_platform_driver(&axon_ram_driver);
}
@ -351,6 +360,7 @@ static void __exit
axon_ram_exit(void)
{
of_unregister_platform_driver(&axon_ram_driver);
unregister_blkdev(azfs_major, AXON_RAM_DEVICE_NAME);
}
module_init(axon_ram_init);

3
arch/powerpc/sysdev/dart_iommu.c
View File

@ -149,7 +149,8 @@ static void dart_flush(struct iommu_table *tbl)
static void dart_build(struct iommu_table *tbl, long index,
long npages, unsigned long uaddr,
enum dma_data_direction direction)
enum dma_data_direction direction,
struct dma_attrs *attrs)
{
unsigned int *dp;
unsigned int rpn;

61
arch/powerpc/sysdev/fsl_pci.c
View File

@ -27,6 +27,7 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
/* atmu setup for fsl pci/pcie controller */
void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
{
@ -248,3 +249,63 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
#if defined(CONFIG_PPC_83xx)
int __init mpc83xx_add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 1, has_address = 0;
phys_addr_t immr = get_immrbase();
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
/* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
* the other at 0x8600, we consider the 0x8500 the primary controller
*/
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
primary = 0;
}
printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
#endif /* CONFIG_PPC_83xx */

1
arch/powerpc/sysdev/fsl_pci.h
View File

@ -83,6 +83,7 @@ struct ccsr_pci {
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */

92
arch/powerpc/sysdev/fsl_soc.c
View File

@ -207,68 +207,60 @@ static int __init of_add_fixed_phys(void)
arch_initcall(of_add_fixed_phys);
#endif /* CONFIG_FIXED_PHY */
static int __init gfar_mdio_of_init(void)
static int gfar_mdio_of_init_one(struct device_node *np)
{
struct device_node *np = NULL;
int k;
struct device_node *child = NULL;
struct gianfar_mdio_data mdio_data;
struct platform_device *mdio_dev;
struct resource res;
int ret;
np = of_find_compatible_node(np, NULL, "fsl,gianfar-mdio");
memset(&res, 0, sizeof(res));
memset(&mdio_data, 0, sizeof(mdio_data));
/* try the deprecated version */
if (!np)
np = of_find_compatible_node(np, "mdio", "gianfar");
ret = of_address_to_resource(np, 0, &res);
if (ret)
return ret;
if (np) {
int k;
struct device_node *child = NULL;
struct gianfar_mdio_data mdio_data;
mdio_dev = platform_device_register_simple("fsl-gianfar_mdio",
res.start&0xfffff, &res, 1);
if (IS_ERR(mdio_dev))
return PTR_ERR(mdio_dev);
memset(&res, 0, sizeof(res));
memset(&mdio_data, 0, sizeof(mdio_data));
for (k = 0; k < 32; k++)
mdio_data.irq[k] = PHY_POLL;
ret = of_address_to_resource(np, 0, &res);
if (ret)
goto err;
mdio_dev =
platform_device_register_simple("fsl-gianfar_mdio",
res.start, &res, 1);
if (IS_ERR(mdio_dev)) {
ret = PTR_ERR(mdio_dev);
goto err;
while ((child = of_get_next_child(np, child)) != NULL) {
int irq = irq_of_parse_and_map(child, 0);
if (irq != NO_IRQ) {
const u32 *id = of_get_property(child, "reg", NULL);
mdio_data.irq[*id] = irq;
}
for (k = 0; k < 32; k++)
mdio_data.irq[k] = PHY_POLL;
while ((child = of_get_next_child(np, child)) != NULL) {
int irq = irq_of_parse_and_map(child, 0);
if (irq != NO_IRQ) {
const u32 *id = of_get_property(child,
"reg", NULL);
mdio_data.irq[*id] = irq;
}
}
ret =
platform_device_add_data(mdio_dev, &mdio_data,
sizeof(struct gianfar_mdio_data));
if (ret)
goto unreg;
}
of_node_put(np);
return 0;
ret = platform_device_add_data(mdio_dev, &mdio_data,
sizeof(struct gianfar_mdio_data));
if (ret)
platform_device_unregister(mdio_dev);
unreg:
platform_device_unregister(mdio_dev);
err:
of_node_put(np);
return ret;
}
static int __init gfar_mdio_of_init(void)
{
struct device_node *np = NULL;
for_each_compatible_node(np, NULL, "fsl,gianfar-mdio")
gfar_mdio_of_init_one(np);
/* try the deprecated version */
for_each_compatible_node(np, "mdio", "gianfar");
gfar_mdio_of_init_one(np);
return 0;
}
arch_initcall(gfar_mdio_of_init);
static const char *gfar_tx_intr = "tx";
@ -296,6 +288,9 @@ static int __init gfar_of_init(void)
const phandle *ph;
int n_res = 2;
if (!of_device_is_available(np))
continue;
memset(r, 0, sizeof(r));
memset(&gfar_data, 0, sizeof(gfar_data));
@ -357,6 +352,9 @@ static int __init gfar_of_init(void)
else
gfar_data.interface = PHY_INTERFACE_MODE_MII;
if (of_get_property(np, "fsl,magic-packet", NULL))
gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
ph = of_get_property(np, "phy-handle", NULL);
if (ph == NULL) {
u32 *fixed_link;
@ -390,7 +388,7 @@ static int __init gfar_of_init(void)
gfar_data.phy_id = *id;
snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "%llx",
(unsigned long long)res.start);
(unsigned long long)res.start&0xfffff);
of_node_put(phy);
of_node_put(mdio);

1
arch/powerpc/sysdev/fsl_soc.h
View File

@ -10,6 +10,7 @@ extern u32 get_baudrate(void);
extern u32 fsl_get_sys_freq(void);
struct spi_board_info;
struct device_node;
extern int fsl_spi_init(struct spi_board_info *board_infos,
unsigned int num_board_infos,

71
arch/powerpc/sysdev/ipic.c
View File

@ -22,6 +22,7 @@
#include <linux/device.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/fsl_devices.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/prom.h>
@ -889,8 +890,78 @@ unsigned int ipic_get_irq(void)
return irq_linear_revmap(primary_ipic->irqhost, irq);
}
#ifdef CONFIG_PM
static struct {
u32 sicfr;
u32 siprr[2];
u32 simsr[2];
u32 sicnr;
u32 smprr[2];
u32 semsr;
u32 secnr;
u32 sermr;
u32 sercr;
} ipic_saved_state;
static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
{
struct ipic *ipic = primary_ipic;
ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
if (fsl_deep_sleep()) {
/* In deep sleep, make sure there can be no
* pending interrupts, as this can cause
* problems on 831x.
*/
ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
ipic_write(ipic->regs, IPIC_SEMSR, 0);
ipic_write(ipic->regs, IPIC_SERMR, 0);
}
return 0;
}
static int ipic_resume(struct sys_device *sdev)
{
struct ipic *ipic = primary_ipic;
ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
return 0;
}
#else
#define ipic_suspend NULL
#define ipic_resume NULL
#endif
static struct sysdev_class ipic_sysclass = {
.name = "ipic",
.suspend = ipic_suspend,
.resume = ipic_resume,
};
static struct sys_device device_ipic = {

6
arch/powerpc/sysdev/qe_lib/qe.c
View File

@ -64,7 +64,7 @@ static phys_addr_t qebase = -1;
phys_addr_t get_qe_base(void)
{
struct device_node *qe;
unsigned int size;
int size;
const u32 *prop;
if (qebase != -1)
@ -158,7 +158,7 @@ static unsigned int brg_clk = 0;
unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
unsigned int size;
int size;
const u32 *prop;
if (brg_clk)
@ -305,7 +305,7 @@ EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
struct sdma *sdma = &qe_immr->sdma;
struct sdma __iomem *sdma = &qe_immr->sdma;
unsigned long sdma_buf_offset;
if (!sdma)

6
arch/powerpc/sysdev/qe_lib/ucc.c
View File

@ -88,7 +88,7 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
return 0;
}
static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
static void get_cmxucr_reg(unsigned int ucc_num, __be32 __iomem **cmxucr,
unsigned int *reg_num, unsigned int *shift)
{
unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
@ -100,7 +100,7 @@ static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
{
__be32 *cmxucr;
__be32 __iomem *cmxucr;
unsigned int reg_num;
unsigned int shift;
@ -121,7 +121,7 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
enum comm_dir mode)
{
__be32 *cmxucr;
__be32 __iomem *cmxucr;
unsigned int reg_num;
unsigned int shift;
u32 clock_bits = 0;

16
arch/powerpc/sysdev/qe_lib/ucc_fast.c
View File

@ -46,7 +46,7 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
&uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
&uccf->uf_regs->uccs, uccf->uf_regs->uccs);
&uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
&uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
@ -68,7 +68,7 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
&uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
&uccf->uf_regs->guemr, uccf->uf_regs->guemr);
&uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
}
EXPORT_SYMBOL(ucc_fast_dump_regs);
@ -96,7 +96,7 @@ EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
struct ucc_fast *uf_regs;
struct ucc_fast __iomem *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
@ -117,7 +117,7 @@ EXPORT_SYMBOL(ucc_fast_enable);
void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
struct ucc_fast *uf_regs;
struct ucc_fast __iomem *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
@ -139,7 +139,7 @@ EXPORT_SYMBOL(ucc_fast_disable);
int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
{
struct ucc_fast_private *uccf;
struct ucc_fast *uf_regs;
struct ucc_fast __iomem *uf_regs;
u32 gumr;
int ret;
@ -216,10 +216,10 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
uccf->stopped_tx = 0;
uccf->stopped_rx = 0;
uf_regs = uccf->uf_regs;
uccf->p_ucce = (u32 *) & (uf_regs->ucce);
uccf->p_uccm = (u32 *) & (uf_regs->uccm);
uccf->p_ucce = &uf_regs->ucce;
uccf->p_uccm = &uf_regs->uccm;
#ifdef CONFIG_UGETH_TX_ON_DEMAND
uccf->p_utodr = (u16 *) & (uf_regs->utodr);
uccf->p_utodr = &uf_regs->utodr;
#endif
#ifdef STATISTICS
uccf->tx_frames = 0;

5
drivers/edac/cell_edac.c
View File

@ -33,7 +33,7 @@ static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
{
struct cell_edac_priv *priv = mci->pvt_info;
struct csrow_info *csrow = &mci->csrows[0];
unsigned long address, pfn, offset;
unsigned long address, pfn, offset, syndrome;
dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016lx\n",
priv->node, chan, ar);
@ -44,10 +44,11 @@ static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
address = (address << 1) | chan;
pfn = address >> PAGE_SHIFT;
offset = address & ~PAGE_MASK;
syndrome = (ar & 0x000000001fe00000ul) >> 21;
/* TODO: Decoding of the error addresss */
edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
0, 0, chan, "");
syndrome, 0, chan, "");
}
static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)

5
drivers/net/fs_enet/Makefile
View File

@ -8,12 +8,7 @@ fs_enet-$(CONFIG_FS_ENET_HAS_SCC) += mac-scc.o
fs_enet-$(CONFIG_FS_ENET_HAS_FEC) += mac-fec.o
fs_enet-$(CONFIG_FS_ENET_HAS_FCC) += mac-fcc.o
ifeq ($(CONFIG_PPC_CPM_NEW_BINDING),y)
obj-$(CONFIG_FS_ENET_MDIO_FEC) += mii-fec.o
obj-$(CONFIG_FS_ENET_MDIO_FCC) += mii-bitbang.o
else
fs_enet-$(CONFIG_FS_ENET_MDIO_FEC) += mii-fec.o
fs_enet-$(CONFIG_FS_ENET_MDIO_FCC) += mii-bitbang.o
endif
fs_enet-objs := fs_enet-main.o $(fs_enet-m)

312
drivers/net/fs_enet/fs_enet-main.c
View File

@ -36,26 +36,18 @@
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/vmalloc.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#endif
#include "fs_enet.h"
/*************************************************/
#ifndef CONFIG_PPC_CPM_NEW_BINDING
static char version[] __devinitdata =
DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")" "\n";
#endif
MODULE_AUTHOR("Pantelis Antoniou <panto@intracom.gr>");
MODULE_DESCRIPTION("Freescale Ethernet Driver");
MODULE_LICENSE("GPL");
@ -958,190 +950,6 @@ static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
extern int fs_mii_connect(struct net_device *dev);
extern void fs_mii_disconnect(struct net_device *dev);
#ifndef CONFIG_PPC_CPM_NEW_BINDING
static struct net_device *fs_init_instance(struct device *dev,
struct fs_platform_info *fpi)
{
struct net_device *ndev = NULL;
struct fs_enet_private *fep = NULL;
int privsize, i, r, err = 0, registered = 0;
fpi->fs_no = fs_get_id(fpi);
/* guard */
if ((unsigned int)fpi->fs_no >= FS_MAX_INDEX)
return ERR_PTR(-EINVAL);
privsize = sizeof(*fep) + (sizeof(struct sk_buff **) *
(fpi->rx_ring + fpi->tx_ring));
ndev = alloc_etherdev(privsize);
if (!ndev) {
err = -ENOMEM;
goto err;
}
fep = netdev_priv(ndev);
fep->dev = dev;
dev_set_drvdata(dev, ndev);
fep->fpi = fpi;
if (fpi->init_ioports)
fpi->init_ioports((struct fs_platform_info *)fpi);
#ifdef CONFIG_FS_ENET_HAS_FEC
if (fs_get_fec_index(fpi->fs_no) >= 0)
fep->ops = &fs_fec_ops;
#endif
#ifdef CONFIG_FS_ENET_HAS_SCC
if (fs_get_scc_index(fpi->fs_no) >=0)
fep->ops = &fs_scc_ops;
#endif
#ifdef CONFIG_FS_ENET_HAS_FCC
if (fs_get_fcc_index(fpi->fs_no) >= 0)
fep->ops = &fs_fcc_ops;
#endif
if (fep->ops == NULL) {
printk(KERN_ERR DRV_MODULE_NAME
": %s No matching ops found (%d).\n",
ndev->name, fpi->fs_no);
err = -EINVAL;
goto err;
}
r = (*fep->ops->setup_data)(ndev);
if (r != 0) {
printk(KERN_ERR DRV_MODULE_NAME
": %s setup_data failed\n",
ndev->name);
err = r;
goto err;
}
/* point rx_skbuff, tx_skbuff */
fep->rx_skbuff = (struct sk_buff **)&fep[1];
fep->tx_skbuff = fep->rx_skbuff + fpi->rx_ring;
/* init locks */
spin_lock_init(&fep->lock);
spin_lock_init(&fep->tx_lock);
/*
* Set the Ethernet address.
*/
for (i = 0; i < 6; i++)
ndev->dev_addr[i] = fpi->macaddr[i];
r = (*fep->ops->allocate_bd)(ndev);
if (fep->ring_base == NULL) {
printk(KERN_ERR DRV_MODULE_NAME
": %s buffer descriptor alloc failed (%d).\n", ndev->name, r);
err = r;
goto err;
}
/*
* Set receive and transmit descriptor base.
*/
fep->rx_bd_base = fep->ring_base;
fep->tx_bd_base = fep->rx_bd_base + fpi->rx_ring;
/* initialize ring size variables */
fep->tx_ring = fpi->tx_ring;
fep->rx_ring = fpi->rx_ring;
/*
* The FEC Ethernet specific entries in the device structure.
*/
ndev->open = fs_enet_open;
ndev->hard_start_xmit = fs_enet_start_xmit;
ndev->tx_timeout = fs_timeout;
ndev->watchdog_timeo = 2 * HZ;
ndev->stop = fs_enet_close;
ndev->get_stats = fs_enet_get_stats;
ndev->set_multicast_list = fs_set_multicast_list;
#ifdef CONFIG_NET_POLL_CONTROLLER
ndev->poll_controller = fs_enet_netpoll;
#endif
netif_napi_add(ndev, &fep->napi,
fs_enet_rx_napi, fpi->napi_weight);
ndev->ethtool_ops = &fs_ethtool_ops;
ndev->do_ioctl = fs_ioctl;
init_timer(&fep->phy_timer_list);
netif_carrier_off(ndev);
err = register_netdev(ndev);
if (err != 0) {
printk(KERN_ERR DRV_MODULE_NAME
": %s register_netdev failed.\n", ndev->name);
goto err;
}
registered = 1;
return ndev;
err:
if (ndev != NULL) {
if (registered)
unregister_netdev(ndev);
if (fep && fep->ops) {
(*fep->ops->free_bd)(ndev);
(*fep->ops->cleanup_data)(ndev);
}
free_netdev(ndev);
}
dev_set_drvdata(dev, NULL);
return ERR_PTR(err);
}
static int fs_cleanup_instance(struct net_device *ndev)
{
struct fs_enet_private *fep;
const struct fs_platform_info *fpi;
struct device *dev;
if (ndev == NULL)
return -EINVAL;
fep = netdev_priv(ndev);
if (fep == NULL)
return -EINVAL;
fpi = fep->fpi;
unregister_netdev(ndev);
dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
(void __force *)fep->ring_base, fep->ring_mem_addr);
/* reset it */
(*fep->ops->cleanup_data)(ndev);
dev = fep->dev;
if (dev != NULL) {
dev_set_drvdata(dev, NULL);
fep->dev = NULL;
}
free_netdev(ndev);
return 0;
}
#endif
/**************************************************************************************/
/* handy pointer to the immap */
@ -1168,7 +976,6 @@ static void cleanup_immap(void)
/**************************************************************************************/
#ifdef CONFIG_PPC_CPM_NEW_BINDING
static int __devinit find_phy(struct device_node *np,
struct fs_platform_info *fpi)
{
@ -1408,121 +1215,6 @@ static void __exit fs_cleanup(void)
of_unregister_platform_driver(&fs_enet_driver);
cleanup_immap();
}
#else
static int __devinit fs_enet_probe(struct device *dev)
{
struct net_device *ndev;
/* no fixup - no device */
if (dev->platform_data == NULL) {
printk(KERN_INFO "fs_enet: "
"probe called with no platform data; "
"remove unused devices\n");
return -ENODEV;
}
ndev = fs_init_instance(dev, dev->platform_data);
if (IS_ERR(ndev))
return PTR_ERR(ndev);
return 0;
}
static int fs_enet_remove(struct device *dev)
{
return fs_cleanup_instance(dev_get_drvdata(dev));
}
static struct device_driver fs_enet_fec_driver = {
.name = "fsl-cpm-fec",
.bus = &platform_bus_type,
.probe = fs_enet_probe,
.remove = fs_enet_remove,
#ifdef CONFIG_PM
/* .suspend = fs_enet_suspend, TODO */
/* .resume = fs_enet_resume, TODO */
#endif
};
static struct device_driver fs_enet_scc_driver = {
.name = "fsl-cpm-scc",
.bus = &platform_bus_type,
.probe = fs_enet_probe,
.remove = fs_enet_remove,
#ifdef CONFIG_PM
/* .suspend = fs_enet_suspend, TODO */
/* .resume = fs_enet_resume, TODO */
#endif
};
static struct device_driver fs_enet_fcc_driver = {
.name = "fsl-cpm-fcc",
.bus = &platform_bus_type,
.probe = fs_enet_probe,
.remove = fs_enet_remove,
#ifdef CONFIG_PM
/* .suspend = fs_enet_suspend, TODO */
/* .resume = fs_enet_resume, TODO */
#endif
};
static int __init fs_init(void)
{
int r;
printk(KERN_INFO
"%s", version);
r = setup_immap();
if (r != 0)
return r;
#ifdef CONFIG_FS_ENET_HAS_FCC
/* let's insert mii stuff */
r = fs_enet_mdio_bb_init();
if (r != 0) {
printk(KERN_ERR DRV_MODULE_NAME
"BB PHY init failed.\n");
return r;
}
r = driver_register(&fs_enet_fcc_driver);
if (r != 0)
goto err;
#endif
#ifdef CONFIG_FS_ENET_HAS_FEC
r = fs_enet_mdio_fec_init();
if (r != 0) {
printk(KERN_ERR DRV_MODULE_NAME
"FEC PHY init failed.\n");
return r;
}
r = driver_register(&fs_enet_fec_driver);
if (r != 0)
goto err;
#endif
#ifdef CONFIG_FS_ENET_HAS_SCC
r = driver_register(&fs_enet_scc_driver);
if (r != 0)
goto err;
#endif
return 0;
err:
cleanup_immap();
return r;
}
static void __exit fs_cleanup(void)
{
driver_unregister(&fs_enet_fec_driver);
driver_unregister(&fs_enet_fcc_driver);
driver_unregister(&fs_enet_scc_driver);
cleanup_immap();
}
#endif
#ifdef CONFIG_NET_POLL_CONTROLLER
static void fs_enet_netpoll(struct net_device *dev)

4
drivers/net/fs_enet/fs_enet.h
View File

@ -138,10 +138,6 @@ struct fs_enet_private {
};
/***************************************************************************/
#ifndef CONFIG_PPC_CPM_NEW_BINDING
int fs_enet_mdio_bb_init(void);
int fs_enet_mdio_fec_init(void);
#endif
void fs_init_bds(struct net_device *dev);
void fs_cleanup_bds(struct net_device *dev);

67
drivers/net/fs_enet/mac-fcc.c
View File

@ -33,6 +33,7 @@
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/phy.h>
#include <linux/of_device.h>
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
@ -42,10 +43,6 @@
#include <asm/irq.h>
#include <asm/uaccess.h>
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <asm/of_device.h>
#endif
#include "fs_enet.h"
/*************************************************/
@ -87,7 +84,6 @@ static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
static int do_pd_setup(struct fs_enet_private *fep)
{
#ifdef CONFIG_PPC_CPM_NEW_BINDING
struct of_device *ofdev = to_of_device(fep->dev);
struct fs_platform_info *fpi = fep->fpi;
int ret = -EINVAL;
@ -125,44 +121,6 @@ out_fccp:
iounmap(fep->fcc.fccp);
out:
return ret;
#else
struct platform_device *pdev = to_platform_device(fep->dev);
struct resource *r;
/* Fill out IRQ field */
fep->interrupt = platform_get_irq(pdev, 0);
if (fep->interrupt < 0)
return -EINVAL;
/* Attach the memory for the FCC Parameter RAM */
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
fep->fcc.ep = ioremap(r->start, r->end - r->start + 1);
if (fep->fcc.ep == NULL)
return -EINVAL;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
fep->fcc.fccp = ioremap(r->start, r->end - r->start + 1);
if (fep->fcc.fccp == NULL)
return -EINVAL;
if (fep->fpi->fcc_regs_c) {
fep->fcc.fcccp = (void __iomem *)fep->fpi->fcc_regs_c;
} else {
r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"fcc_regs_c");
fep->fcc.fcccp = ioremap(r->start,
r->end - r->start + 1);
}
if (fep->fcc.fcccp == NULL)
return -EINVAL;
fep->fcc.mem = (void __iomem *)fep->fpi->mem_offset;
if (fep->fcc.mem == NULL)
return -EINVAL;
return 0;
#endif
}
#define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
@ -173,17 +131,6 @@ out:
static int setup_data(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
#ifndef CONFIG_PPC_CPM_NEW_BINDING
struct fs_platform_info *fpi = fep->fpi;
fpi->cp_command = (fpi->cp_page << 26) |
(fpi->cp_block << 21) |
(12 << 6);
fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
return -EINVAL;
#endif
if (do_pd_setup(fep) != 0)
return -EINVAL;
@ -304,9 +251,6 @@ static void restart(struct net_device *dev)
fcc_enet_t __iomem *ep = fep->fcc.ep;
dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
u16 paddrh, paddrm, paddrl;
#ifndef CONFIG_PPC_CPM_NEW_BINDING
u16 mem_addr;
#endif
const unsigned char *mac;
int i;
@ -338,19 +282,10 @@ static void restart(struct net_device *dev)
* this area.
*/
#ifdef CONFIG_PPC_CPM_NEW_BINDING
W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
W16(ep, fen_padptr, fpi->dpram_offset + 64);
#else
mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
W16(ep, fen_padptr, mem_addr + 64);
#endif
/* fill with special symbol... */
memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);

23
drivers/net/fs_enet/mac-fec.c
View File

@ -32,6 +32,7 @@
#include <linux/bitops.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
@ -43,10 +44,6 @@
#include <asm/cpm1.h>
#endif
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <asm/of_device.h>
#endif
#include "fs_enet.h"
#include "fec.h"
@ -99,7 +96,6 @@ static int whack_reset(fec_t __iomem *fecp)
static int do_pd_setup(struct fs_enet_private *fep)
{
#ifdef CONFIG_PPC_CPM_NEW_BINDING
struct of_device *ofdev = to_of_device(fep->dev);
fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
@ -111,23 +107,6 @@ static int do_pd_setup(struct fs_enet_private *fep)
return -EINVAL;
return 0;
#else
struct platform_device *pdev = to_platform_device(fep->dev);
struct resource *r;
/* Fill out IRQ field */
fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
if (fep->interrupt < 0)
return -EINVAL;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
fep->fec.fecp = ioremap(r->start, r->end - r->start + 1);
if(fep->fec.fecp == NULL)
return -EINVAL;
return 0;
#endif
}
#define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)

37
drivers/net/fs_enet/mac-scc.c
View File

@ -32,6 +32,7 @@
#include <linux/bitops.h>
#include <linux/fs.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
@ -43,10 +44,6 @@
#include <asm/cpm1.h>
#endif
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <linux/of_platform.h>
#endif
#include "fs_enet.h"
/*************************************************/
@ -99,7 +96,6 @@ static inline int scc_cr_cmd(struct fs_enet_private *fep, u32 op)
static int do_pd_setup(struct fs_enet_private *fep)
{
#ifdef CONFIG_PPC_CPM_NEW_BINDING
struct of_device *ofdev = to_of_device(fep->dev);
fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
@ -115,27 +111,6 @@ static int do_pd_setup(struct fs_enet_private *fep)
iounmap(fep->scc.sccp);
return -EINVAL;
}
#else
struct platform_device *pdev = to_platform_device(fep->dev);
struct resource *r;
/* Fill out IRQ field */
fep->interrupt = platform_get_irq_byname(pdev, "interrupt");
if (fep->interrupt < 0)
return -EINVAL;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
fep->scc.sccp = ioremap(r->start, r->end - r->start + 1);
if (fep->scc.sccp == NULL)
return -EINVAL;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram");
fep->scc.ep = ioremap(r->start, r->end - r->start + 1);
if (fep->scc.ep == NULL)
return -EINVAL;
#endif
return 0;
}
@ -149,16 +124,6 @@ static int setup_data(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
#ifndef CONFIG_PPC_CPM_NEW_BINDING
struct fs_platform_info *fpi = fep->fpi;
fep->scc.idx = fs_get_scc_index(fpi->fs_no);
if ((unsigned int)fep->fcc.idx >= 4) /* max 4 SCCs */
return -EINVAL;
fpi->cp_command = fep->fcc.idx << 6;
#endif
do_pd_setup(fep);
fep->scc.hthi = 0;

107
drivers/net/fs_enet/mii-bitbang.c
View File

@ -22,10 +22,7 @@
#include <linux/mii.h>
#include <linux/platform_device.h>
#include <linux/mdio-bitbang.h>
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <linux/of_platform.h>
#endif
#include "fs_enet.h"
@ -110,7 +107,6 @@ static struct mdiobb_ops bb_ops = {
.get_mdio_data = mdio_read,
};
#ifdef CONFIG_PPC_CPM_NEW_BINDING
static int __devinit fs_mii_bitbang_init(struct mii_bus *bus,
struct device_node *np)
{
@ -271,106 +267,3 @@ static void fs_enet_mdio_bb_exit(void)
module_init(fs_enet_mdio_bb_init);
module_exit(fs_enet_mdio_bb_exit);
#else
static int __devinit fs_mii_bitbang_init(struct bb_info *bitbang,
struct fs_mii_bb_platform_info *fmpi)
{
bitbang->dir = (u32 __iomem *)fmpi->mdio_dir.offset;
bitbang->dat = (u32 __iomem *)fmpi->mdio_dat.offset;
bitbang->mdio_msk = 1U << (31 - fmpi->mdio_dat.bit);
bitbang->mdc_msk = 1U << (31 - fmpi->mdc_dat.bit);
return 0;
}
static int __devinit fs_enet_mdio_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct fs_mii_bb_platform_info *pdata;
struct mii_bus *new_bus;
struct bb_info *bitbang;
int err = 0;
if (NULL == dev)
return -EINVAL;
bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
if (NULL == bitbang)
return -ENOMEM;
bitbang->ctrl.ops = &bb_ops;
new_bus = alloc_mdio_bitbang(&bitbang->ctrl);
if (NULL == new_bus)
return -ENOMEM;
new_bus->name = "BB MII Bus",
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
new_bus->phy_mask = ~0x9;
pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
if (NULL == pdata) {
printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
return -ENODEV;
}
/*set up workspace*/
fs_mii_bitbang_init(bitbang, pdata);
new_bus->priv = bitbang;
new_bus->irq = pdata->irq;
new_bus->dev = dev;
dev_set_drvdata(dev, new_bus);
err = mdiobus_register(new_bus);
if (0 != err) {
printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
new_bus->name);
goto bus_register_fail;
}
return 0;
bus_register_fail:
free_mdio_bitbang(new_bus);
kfree(bitbang);
return err;
}
static int fs_enet_mdio_remove(struct device *dev)
{
struct mii_bus *bus = dev_get_drvdata(dev);
mdiobus_unregister(bus);
dev_set_drvdata(dev, NULL);
free_mdio_bitbang(bus);
return 0;
}
static struct device_driver fs_enet_bb_mdio_driver = {
.name = "fsl-bb-mdio",
.bus = &platform_bus_type,
.probe = fs_enet_mdio_probe,
.remove = fs_enet_mdio_remove,
};
int fs_enet_mdio_bb_init(void)
{
return driver_register(&fs_enet_bb_mdio_driver);
}
void fs_enet_mdio_bb_exit(void)
{
driver_unregister(&fs_enet_bb_mdio_driver);
}
#endif

144
drivers/net/fs_enet/mii-fec.c
View File

@ -31,15 +31,12 @@
#include <linux/ethtool.h>
#include <linux/bitops.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#ifdef CONFIG_PPC_CPM_NEW_BINDING
#include <linux/of_platform.h>
#endif
#include "fs_enet.h"
#include "fec.h"
@ -51,52 +48,6 @@
#define FEC_MII_LOOPS 10000
#ifndef CONFIG_PPC_CPM_NEW_BINDING
static int match_has_phy (struct device *dev, void* data)
{
struct platform_device* pdev = container_of(dev, struct platform_device, dev);
struct fs_platform_info* fpi;
if(strcmp(pdev->name, (char*)data))
{
return 0;
}
fpi = pdev->dev.platform_data;
if((fpi)&&(fpi->has_phy))
return 1;
return 0;
}
static int fs_mii_fec_init(struct fec_info* fec, struct fs_mii_fec_platform_info *fmpi)
{
struct resource *r;
fec_t __iomem *fecp;
char* name = "fsl-cpm-fec";
/* we need fec in order to be useful */
struct platform_device *fec_pdev =
container_of(bus_find_device(&platform_bus_type, NULL, name, match_has_phy),
struct platform_device, dev);
if(fec_pdev == NULL) {
printk(KERN_ERR"Unable to find PHY for %s", name);
return -ENODEV;
}
r = platform_get_resource_byname(fec_pdev, IORESOURCE_MEM, "regs");
fec->fecp = fecp = ioremap(r->start,sizeof(fec_t));
fec->mii_speed = fmpi->mii_speed;
setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
setbits32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
out_be32(&fecp->fec_ievent, FEC_ENET_MII);
out_be32(&fecp->fec_mii_speed, fec->mii_speed);
return 0;
}
#endif
static int fs_enet_fec_mii_read(struct mii_bus *bus , int phy_id, int location)
{
struct fec_info* fec = bus->priv;
@ -151,7 +102,6 @@ static int fs_enet_fec_mii_reset(struct mii_bus *bus)
return 0;
}
#ifdef CONFIG_PPC_CPM_NEW_BINDING
static void __devinit add_phy(struct mii_bus *bus, struct device_node *np)
{
const u32 *data;
@ -286,95 +236,3 @@ static void fs_enet_mdio_fec_exit(void)
module_init(fs_enet_mdio_fec_init);
module_exit(fs_enet_mdio_fec_exit);
#else
static int __devinit fs_enet_fec_mdio_probe(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct fs_mii_fec_platform_info *pdata;
struct mii_bus *new_bus;
struct fec_info *fec;
int err = 0;
if (NULL == dev)
return -EINVAL;
new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
if (NULL == new_bus)
return -ENOMEM;
fec = kzalloc(sizeof(struct fec_info), GFP_KERNEL);
if (NULL == fec)
return -ENOMEM;
new_bus->name = "FEC MII Bus",
new_bus->read = &fs_enet_fec_mii_read,
new_bus->write = &fs_enet_fec_mii_write,
new_bus->reset = &fs_enet_fec_mii_reset,
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
pdata = (struct fs_mii_fec_platform_info *)pdev->dev.platform_data;
if (NULL == pdata) {
printk(KERN_ERR "fs_enet FEC mdio %d: Missing platform data!\n", pdev->id);
return -ENODEV;
}
/*set up workspace*/
fs_mii_fec_init(fec, pdata);
new_bus->priv = fec;
new_bus->irq = pdata->irq;
new_bus->dev = dev;
dev_set_drvdata(dev, new_bus);
err = mdiobus_register(new_bus);
if (0 != err) {
printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
new_bus->name);
goto bus_register_fail;
}
return 0;
bus_register_fail:
kfree(new_bus);
return err;
}
static int fs_enet_fec_mdio_remove(struct device *dev)
{
struct mii_bus *bus = dev_get_drvdata(dev);
mdiobus_unregister(bus);
dev_set_drvdata(dev, NULL);
kfree(bus->priv);
bus->priv = NULL;
kfree(bus);
return 0;
}
static struct device_driver fs_enet_fec_mdio_driver = {
.name = "fsl-cpm-fec-mdio",
.bus = &platform_bus_type,
.probe = fs_enet_fec_mdio_probe,
.remove = fs_enet_fec_mdio_remove,
};
int fs_enet_mdio_fec_init(void)
{
return driver_register(&fs_enet_fec_mdio_driver);
}
void fs_enet_mdio_fec_exit(void)
{
driver_unregister(&fs_enet_fec_mdio_driver);
}
#endif

122
drivers/net/gianfar.c
View File

@ -134,6 +134,9 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int l
static void gfar_vlan_rx_register(struct net_device *netdev,
struct vlan_group *grp);
void gfar_halt(struct net_device *dev);
#ifdef CONFIG_PM
static void gfar_halt_nodisable(struct net_device *dev);
#endif
void gfar_start(struct net_device *dev);
static void gfar_clear_exact_match(struct net_device *dev);
static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
@ -207,6 +210,7 @@ static int gfar_probe(struct platform_device *pdev)
spin_lock_init(&priv->txlock);
spin_lock_init(&priv->rxlock);
spin_lock_init(&priv->bflock);
platform_set_drvdata(pdev, dev);
@ -378,6 +382,103 @@ static int gfar_remove(struct platform_device *pdev)
return 0;
}
#ifdef CONFIG_PM
static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct gfar_private *priv = netdev_priv(dev);
unsigned long flags;
u32 tempval;
int magic_packet = priv->wol_en &&
(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
netif_device_detach(dev);
if (netif_running(dev)) {
spin_lock_irqsave(&priv->txlock, flags);
spin_lock(&priv->rxlock);
gfar_halt_nodisable(dev);
/* Disable Tx, and Rx if wake-on-LAN is disabled. */
tempval = gfar_read(&priv->regs->maccfg1);
tempval &= ~MACCFG1_TX_EN;
if (!magic_packet)
tempval &= ~MACCFG1_RX_EN;
gfar_write(&priv->regs->maccfg1, tempval);
spin_unlock(&priv->rxlock);
spin_unlock_irqrestore(&priv->txlock, flags);
#ifdef CONFIG_GFAR_NAPI
napi_disable(&priv->napi);
#endif
if (magic_packet) {
/* Enable interrupt on Magic Packet */
gfar_write(&priv->regs->imask, IMASK_MAG);
/* Enable Magic Packet mode */
tempval = gfar_read(&priv->regs->maccfg2);
tempval |= MACCFG2_MPEN;
gfar_write(&priv->regs->maccfg2, tempval);
} else {
phy_stop(priv->phydev);
}
}
return 0;
}
static int gfar_resume(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct gfar_private *priv = netdev_priv(dev);
unsigned long flags;
u32 tempval;
int magic_packet = priv->wol_en &&
(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
if (!netif_running(dev)) {
netif_device_attach(dev);
return 0;
}
if (!magic_packet && priv->phydev)
phy_start(priv->phydev);
/* Disable Magic Packet mode, in case something
* else woke us up.
*/
spin_lock_irqsave(&priv->txlock, flags);
spin_lock(&priv->rxlock);
tempval = gfar_read(&priv->regs->maccfg2);
tempval &= ~MACCFG2_MPEN;
gfar_write(&priv->regs->maccfg2, tempval);
gfar_start(dev);
spin_unlock(&priv->rxlock);
spin_unlock_irqrestore(&priv->txlock, flags);
netif_device_attach(dev);
#ifdef CONFIG_GFAR_NAPI
napi_enable(&priv->napi);
#endif
return 0;
}
#else
#define gfar_suspend NULL
#define gfar_resume NULL
#endif
/* Reads the controller's registers to determine what interface
* connects it to the PHY.
@ -534,8 +635,9 @@ static void init_registers(struct net_device *dev)
}
#ifdef CONFIG_PM
/* Halt the receive and transmit queues */
void gfar_halt(struct net_device *dev)
static void gfar_halt_nodisable(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
struct gfar __iomem *regs = priv->regs;
@ -558,6 +660,15 @@ void gfar_halt(struct net_device *dev)
(IEVENT_GRSC | IEVENT_GTSC)))
cpu_relax();
}
}
#endif
/* Halt the receive and transmit queues */
void gfar_halt(struct net_device *dev)
{
struct gfar_private *priv = netdev_priv(dev);
struct gfar __iomem *regs = priv->regs;
u32 tempval;
/* Disable Rx and Tx */
tempval = gfar_read(&regs->maccfg1);
@ -1909,7 +2020,12 @@ static irqreturn_t gfar_error(int irq, void *dev_id)
u32 events = gfar_read(&priv->regs->ievent);
/* Clear IEVENT */
gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
/* Magic Packet is not an error. */
if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
(events & IEVENT_MAG))
events &= ~IEVENT_MAG;
/* Hmm... */
if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
@ -1977,6 +2093,8 @@ MODULE_ALIAS("platform:fsl-gianfar");
static struct platform_driver gfar_driver = {
.probe = gfar_probe,
.remove = gfar_remove,
.suspend = gfar_suspend,
.resume = gfar_resume,
.driver = {
.name = "fsl-gianfar",
.owner = THIS_MODULE,

12
drivers/net/gianfar.h
View File

@ -157,6 +157,7 @@ extern const char gfar_driver_version[];
#define MACCFG2_GMII 0x00000200
#define MACCFG2_HUGEFRAME 0x00000020
#define MACCFG2_LENGTHCHECK 0x00000010
#define MACCFG2_MPEN 0x00000008
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
@ -229,6 +230,7 @@ extern const char gfar_driver_version[];
#define IEVENT_CRL 0x00020000
#define IEVENT_XFUN 0x00010000
#define IEVENT_RXB0 0x00008000
#define IEVENT_MAG 0x00000800
#define IEVENT_GRSC 0x00000100
#define IEVENT_RXF0 0x00000080
#define IEVENT_FIR 0x00000008
@ -241,7 +243,8 @@ extern const char gfar_driver_version[];
#define IEVENT_ERR_MASK \
(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
| IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
| IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
| IEVENT_MAG)
#define IMASK_INIT_CLEAR 0x00000000
#define IMASK_BABR 0x80000000
@ -259,6 +262,7 @@ extern const char gfar_driver_version[];
#define IMASK_CRL 0x00020000
#define IMASK_XFUN 0x00010000
#define IMASK_RXB0 0x00008000
#define IMASK_MAG 0x00000800
#define IMASK_GTSC 0x00000100
#define IMASK_RXFEN0 0x00000080
#define IMASK_FIR 0x00000008
@ -726,10 +730,14 @@ struct gfar_private {
unsigned int fifo_starve;
unsigned int fifo_starve_off;
/* Bitfield update lock */
spinlock_t bflock;
unsigned char vlan_enable:1,
rx_csum_enable:1,
extended_hash:1,
bd_stash_en:1;
bd_stash_en:1,
wol_en:1; /* Wake-on-LAN enabled */
unsigned short padding;
unsigned int interruptTransmit;

41
drivers/net/gianfar_ethtool.c
View File

@ -479,14 +479,13 @@ static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rva
static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
{
struct gfar_private *priv = netdev_priv(dev);
unsigned long flags;
int err = 0;
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
return -EOPNOTSUPP;
if (dev->flags & IFF_UP) {
unsigned long flags;
/* Halt TX and RX, and process the frames which
* have already been received */
spin_lock_irqsave(&priv->txlock, flags);
@ -502,7 +501,9 @@ static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
stop_gfar(dev);
}
spin_lock_irqsave(&priv->bflock, flags);
priv->rx_csum_enable = data;
spin_unlock_irqrestore(&priv->bflock, flags);
if (dev->flags & IFF_UP)
err = startup_gfar(dev);
@ -564,6 +565,38 @@ static void gfar_set_msglevel(struct net_device *dev, uint32_t data)
priv->msg_enable = data;
}
#ifdef CONFIG_PM
static void gfar_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct gfar_private *priv = netdev_priv(dev);
if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) {
wol->supported = WAKE_MAGIC;
wol->wolopts = priv->wol_en ? WAKE_MAGIC : 0;
} else {
wol->supported = wol->wolopts = 0;
}
}
static int gfar_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct gfar_private *priv = netdev_priv(dev);
unsigned long flags;
if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
wol->wolopts != 0)
return -EINVAL;
if (wol->wolopts & ~WAKE_MAGIC)
return -EINVAL;
spin_lock_irqsave(&priv->bflock, flags);
priv->wol_en = wol->wolopts & WAKE_MAGIC ? 1 : 0;
spin_unlock_irqrestore(&priv->bflock, flags);
return 0;
}
#endif
const struct ethtool_ops gfar_ethtool_ops = {
.get_settings = gfar_gsettings,
@ -585,4 +618,8 @@ const struct ethtool_ops gfar_ethtool_ops = {
.set_tx_csum = gfar_set_tx_csum,
.get_msglevel = gfar_get_msglevel,
.set_msglevel = gfar_set_msglevel,
#ifdef CONFIG_PM
.get_wol = gfar_get_wol,
.set_wol = gfar_set_wol,
#endif
};

192
drivers/video/offb.c
View File

@ -47,6 +47,7 @@ enum {
cmap_M3B, /* ATI Rage Mobility M3 Head B */
cmap_radeon, /* ATI Radeon */
cmap_gxt2000, /* IBM GXT2000 */
cmap_avivo, /* ATI R5xx */
};
struct offb_par {
@ -58,26 +59,36 @@ struct offb_par {
struct offb_par default_par;
/*
* Interface used by the world
*/
static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int offb_blank(int blank, struct fb_info *info);
#ifdef CONFIG_PPC32
extern boot_infos_t *boot_infos;
#endif
static struct fb_ops offb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = offb_setcolreg,
.fb_blank = offb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
/* Definitions used by the Avivo palette hack */
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LUTB_CONTROL 0x6cc0
#define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4
#define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8
#define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc
#define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0
#define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4
#define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8
/*
* Set a single color register. The values supplied are already
@ -160,6 +171,17 @@ static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
out_le32(((unsigned __iomem *) par->cmap_adr) + regno,
(red << 16 | green << 8 | blue));
break;
case cmap_avivo:
/* Write to both LUTs for now */
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
break;
}
return 0;
@ -216,12 +238,59 @@ static int offb_blank(int blank, struct fb_info *info)
out_le32(((unsigned __iomem *) par->cmap_adr) + i,
0);
break;
case cmap_avivo:
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
break;
}
} else
fb_set_cmap(&info->cmap, info);
return 0;
}
static int offb_set_par(struct fb_info *info)
{
struct offb_par *par = (struct offb_par *) info->par;
/* On avivo, initialize palette control */
if (par->cmap_type == cmap_avivo) {
writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED);
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
}
return 0;
}
static struct fb_ops offb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = offb_setcolreg,
.fb_set_par = offb_set_par,
.fb_blank = offb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static void __iomem *offb_map_reg(struct device_node *np, int index,
unsigned long offset, unsigned long size)
@ -245,6 +314,59 @@ static void __iomem *offb_map_reg(struct device_node *np, int index,
return ioremap(taddr + offset, size);
}
static void offb_init_palette_hacks(struct fb_info *info, struct device_node *dp,
const char *name, unsigned long address)
{
struct offb_par *par = (struct offb_par *) info->par;
if (dp && !strncmp(name, "ATY,Rage128", 11)) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_r128;
} else if (dp && (!strncmp(name, "ATY,RageM3pA", 12)
|| !strncmp(name, "ATY,RageM3p12A", 14))) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3A;
} else if (dp && !strncmp(name, "ATY,RageM3pB", 12)) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3B;
} else if (dp && !strncmp(name, "ATY,Rage6", 9)) {
par->cmap_adr = offb_map_reg(dp, 1, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_radeon;
} else if (!strncmp(name, "ATY,", 4)) {
unsigned long base = address & 0xff000000UL;
par->cmap_adr =
ioremap(base + 0x7ff000, 0x1000) + 0xcc0;
par->cmap_data = par->cmap_adr + 1;
par->cmap_type = cmap_m64;
} else if (dp && (of_device_is_compatible(dp, "pci1014,b7") ||
of_device_is_compatible(dp, "pci1014,21c"))) {
par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000);
if (par->cmap_adr)
par->cmap_type = cmap_gxt2000;
} else if (dp && !strncmp(name, "vga,Display-", 12)) {
/* Look for AVIVO initialized by SLOF */
struct device_node *pciparent = of_get_parent(dp);
const u32 *vid, *did;
vid = of_get_property(pciparent, "vendor-id", NULL);
did = of_get_property(pciparent, "device-id", NULL);
/* This will match most R5xx */
if (vid && did && *vid == 0x1002 &&
((*did >= 0x7100 && *did < 0x7800) ||
(*did >= 0x9400))) {
par->cmap_adr = offb_map_reg(pciparent, 2, 0, 0x10000);
if (par->cmap_adr)
par->cmap_type = cmap_avivo;
}
of_node_put(pciparent);
}
info->fix.visual = (par->cmap_type != cmap_unknown) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR;
}
static void __init offb_init_fb(const char *name, const char *full_name,
int width, int height, int depth,
int pitch, unsigned long address,
@ -283,6 +405,7 @@ static void __init offb_init_fb(const char *name, const char *full_name,
fix = &info->fix;
var = &info->var;
info->par = par;
strcpy(fix->id, "OFfb ");
strncat(fix->id, name, sizeof(fix->id) - sizeof("OFfb "));
@ -298,39 +421,9 @@ static void __init offb_init_fb(const char *name, const char *full_name,
fix->type_aux = 0;
par->cmap_type = cmap_unknown;
if (depth == 8) {
if (dp && !strncmp(name, "ATY,Rage128", 11)) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_r128;
} else if (dp && (!strncmp(name, "ATY,RageM3pA", 12)
|| !strncmp(name, "ATY,RageM3p12A", 14))) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3A;
} else if (dp && !strncmp(name, "ATY,RageM3pB", 12)) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3B;
} else if (dp && !strncmp(name, "ATY,Rage6", 9)) {
par->cmap_adr = offb_map_reg(dp, 1, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_radeon;
} else if (!strncmp(name, "ATY,", 4)) {
unsigned long base = address & 0xff000000UL;
par->cmap_adr =
ioremap(base + 0x7ff000, 0x1000) + 0xcc0;
par->cmap_data = par->cmap_adr + 1;
par->cmap_type = cmap_m64;
} else if (dp && (of_device_is_compatible(dp, "pci1014,b7") ||
of_device_is_compatible(dp, "pci1014,21c"))) {
par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000);
if (par->cmap_adr)
par->cmap_type = cmap_gxt2000;
}
fix->visual = (par->cmap_type != cmap_unknown) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR;
} else
if (depth == 8)
offb_init_palette_hacks(info, dp, name, address);
else
fix->visual = FB_VISUAL_TRUECOLOR;
var->xoffset = var->yoffset = 0;
@ -395,7 +488,6 @@ static void __init offb_init_fb(const char *name, const char *full_name,
info->fbops = &offb_ops;
info->screen_base = ioremap(address, fix->smem_len);
info->par = par;
info->pseudo_palette = (void *) (info + 1);
info->flags = FBINFO_DEFAULT | foreign_endian;

1
drivers/video/ps3fb.c
View File

@ -1297,6 +1297,7 @@ static int ps3fb_shutdown(struct ps3_system_bus_device *dev)
static struct ps3_system_bus_driver ps3fb_driver = {
.match_id = PS3_MATCH_ID_GRAPHICS,
.match_sub_id = PS3_MATCH_SUB_ID_FB,
.core.name = DEVICE_NAME,
.core.owner = THIS_MODULE,
.probe = ps3fb_probe,

2
include/asm-powerpc/asm-compat.h
View File

@ -22,6 +22,7 @@
#define PPC_STL stringify_in_c(std)
#define PPC_LCMPI stringify_in_c(cmpdi)
#define PPC_LONG stringify_in_c(.llong)
#define PPC_LONG_ALIGN stringify_in_c(.balign 8)
#define PPC_TLNEI stringify_in_c(tdnei)
#define PPC_LLARX stringify_in_c(ldarx)
#define PPC_STLCX stringify_in_c(stdcx.)
@ -43,6 +44,7 @@
#define PPC_STL stringify_in_c(stw)
#define PPC_LCMPI stringify_in_c(cmpwi)
#define PPC_LONG stringify_in_c(.long)
#define PPC_LONG_ALIGN stringify_in_c(.balign 4)
#define PPC_TLNEI stringify_in_c(twnei)
#define PPC_LLARX stringify_in_c(lwarx)
#define PPC_STLCX stringify_in_c(stwcx.)

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