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clk: xgene: Don't call __pa on ioremaped address 

ioremaped addresses are not linearly mapped so the physical
address can not be figured out via __pa. More generally, there
is no guarantee that backing value of an ioremapped address
is a physical address at all. The value here is only used
for debugging so just drop the call to __pa on the ioremapped
address.

Fixes: 6ae5fd3812 ("clk: xgene: Silence sparse warnings")
Signed-off-by: Laura Abbott <labbott@redhat.com>
Acked-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Laura Abbott 2016-10-28 09:59:38 -07:00 committed by Stephen Boyd
parent 5c4a9129b8
commit 06b113e9f2
1 changed files with 4 additions and 6 deletions
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10
drivers/clk/clk-xgene.c
View File

@ -463,22 +463,20 @@ static int xgene_clk_enable(struct clk_hw *hw)
struct xgene_clk *pclk = to_xgene_clk(hw); struct xgene_clk *pclk = to_xgene_clk(hw);
unsigned long flags = 0; unsigned long flags = 0;
u32 data; u32 data;
phys_addr_t reg;
if (pclk->lock) if (pclk->lock)
spin_lock_irqsave(pclk->lock, flags); spin_lock_irqsave(pclk->lock, flags);
if (pclk->param.csr_reg != NULL) { if (pclk->param.csr_reg != NULL) {
pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
reg = __pa(pclk->param.csr_reg);
/* First enable the clock */ /* First enable the clock */
data = xgene_clk_read(pclk->param.csr_reg + data = xgene_clk_read(pclk->param.csr_reg +
pclk->param.reg_clk_offset); pclk->param.reg_clk_offset);
data |= pclk->param.reg_clk_mask; data |= pclk->param.reg_clk_mask;
xgene_clk_write(data, pclk->param.csr_reg + xgene_clk_write(data, pclk->param.csr_reg +
pclk->param.reg_clk_offset); pclk->param.reg_clk_offset);
pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n", pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",
clk_hw_get_name(hw), &reg, clk_hw_get_name(hw),
pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
data); data);
@ -488,8 +486,8 @@ static int xgene_clk_enable(struct clk_hw *hw)
data &= ~pclk->param.reg_csr_mask; data &= ~pclk->param.reg_csr_mask;
xgene_clk_write(data, pclk->param.csr_reg + xgene_clk_write(data, pclk->param.csr_reg +
pclk->param.reg_csr_offset); pclk->param.reg_csr_offset);
pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n", pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",
clk_hw_get_name(hw), &reg, clk_hw_get_name(hw),
pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
data); data);
} }