x86/platform/intel-mid: Make vertical indentation consistent
The vertical indentation is kinda chaotic in intel-mid.h. Let's be consistent with it. Suggested-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1465992260-29897-1-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -88,7 +88,7 @@ struct intel_mid_ops {
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* For every new cpu addition, a weak get_<cpuname>_ops() function needs be
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* declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
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*/
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#define INTEL_MID_OPS_INIT {\
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#define INTEL_MID_OPS_INIT { \
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DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
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DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
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DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
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@ -108,8 +108,8 @@ static inline bool intel_mid_has_msic(void)
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#else /* !CONFIG_X86_INTEL_MID */
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#define intel_mid_identify_cpu() (0)
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#define intel_mid_has_msic() (0)
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#define intel_mid_identify_cpu() 0
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#define intel_mid_has_msic() 0
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#endif /* !CONFIG_X86_INTEL_MID */
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@ -137,9 +137,12 @@ extern enum intel_mid_timer_options intel_mid_timer_options;
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/* Bus Select SoC Fuse value */
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#define BSEL_SOC_FUSE_MASK 0x7
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#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
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#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
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#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
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/* FSB 133MHz */
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#define BSEL_SOC_FUSE_001 0x1
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/* FSB 100MHz */
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#define BSEL_SOC_FUSE_101 0x5
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/* FSB 83MHz */
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#define BSEL_SOC_FUSE_111 0x7
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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@ -148,12 +151,12 @@ extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ (1024)
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/*#define MRST_VRTC_PGOFFSET (0xc00) */
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#define MRST_VRTC_MAP_SZ 1024
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/* #define MRST_VRTC_PGOFFSET 0xc00 */
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extern void intel_mid_rtc_init(void);
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/* the offset for the mapping of global gpio pin to irq */
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/* The offset for the mapping of global gpio pin to irq */
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#define INTEL_MID_IRQ_OFFSET 0x100
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#endif /* _ASM_X86_INTEL_MID_H */
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