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drm/nvc0/gr: add initial support for nvd9, not quite there yet.. 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2011-07-11 15:57:54 +10:00
parent be7f2615d7
commit 06784090ec
8 changed files with 326 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/nouveau/nouveau_state.c
View File

@ -655,6 +655,7 @@ nouveau_card_init(struct drm_device *dev)
nv50_graph_create(dev);
break;
case NV_C0:
case NV_D0:
nvc0_graph_create(dev);
break;
default:
@ -1111,13 +1112,11 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
dev_priv->noaccel = !!nouveau_noaccel;
if (nouveau_noaccel == -1) {
switch (dev_priv->chipset) {
#if 0
case 0xXX: /* known broken */
case 0xd9: /* known broken */
NV_INFO(dev, "acceleration disabled by default, pass "
"noaccel=0 to force enable\n");
dev_priv->noaccel = true;
break;
#endif
default:
dev_priv->noaccel = false;
break;

6
drivers/gpu/drm/nouveau/nvc0_graph.c
View File

@ -875,14 +875,16 @@ nvc0_graph_create(struct drm_device *dev)
case 0xcf: /* 4/0/0/0, 3 */
priv->magic_not_rop_nr = 0x03;
break;
case 0xd9: /* 1/0/0/0, 1 */
priv->magic_not_rop_nr = 0x01;
break;
}
if (!priv->magic_not_rop_nr) {
NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
priv->tp_nr[3], priv->rop_nr);
/* use 0xc3's values... */
priv->magic_not_rop_nr = 0x03;
priv->magic_not_rop_nr = 0x00;
}
NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */

1
drivers/gpu/drm/nouveau/nvc0_graph.h
View File

@ -87,6 +87,7 @@ nvc0_graph_class(struct drm_device *dev)
case 0xc1:
return 0x9197;
case 0xc8:
case 0xd9:
return 0x9297;
default:
return 0;

127
drivers/gpu/drm/nouveau/nvc0_grctx.c
View File

@ -1268,6 +1268,17 @@ nvc0_grctx_generate_9039(struct drm_device *dev)
static void
nvc0_grctx_generate_90c0(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
for (i = 0; dev_priv->chipset == 0xd9 && i < 4; i++) {
nv_mthd(dev, 0x90c0, 0x2700 + (i * 0x40), 0x00000000);
nv_mthd(dev, 0x90c0, 0x2720 + (i * 0x40), 0x00000000);
nv_mthd(dev, 0x90c0, 0x2704 + (i * 0x40), 0x00000000);
nv_mthd(dev, 0x90c0, 0x2724 + (i * 0x40), 0x00000000);
nv_mthd(dev, 0x90c0, 0x2708 + (i * 0x40), 0x00000000);
nv_mthd(dev, 0x90c0, 0x2728 + (i * 0x40), 0x00000000);
}
nv_mthd(dev, 0x90c0, 0x270c, 0x00000000);
nv_mthd(dev, 0x90c0, 0x272c, 0x00000000);
nv_mthd(dev, 0x90c0, 0x274c, 0x00000000);
@ -1276,6 +1287,12 @@ nvc0_grctx_generate_90c0(struct drm_device *dev)
nv_mthd(dev, 0x90c0, 0x27ac, 0x00000000);
nv_mthd(dev, 0x90c0, 0x27cc, 0x00000000);
nv_mthd(dev, 0x90c0, 0x27ec, 0x00000000);
for (i = 0; dev_priv->chipset == 0xd9 && i < 4; i++) {
nv_mthd(dev, 0x90c0, 0x2710 + (i * 0x40), 0x00014000);
nv_mthd(dev, 0x90c0, 0x2730 + (i * 0x40), 0x00014000);
nv_mthd(dev, 0x90c0, 0x2714 + (i * 0x40), 0x00000040);
nv_mthd(dev, 0x90c0, 0x2734 + (i * 0x40), 0x00000040);
}
nv_mthd(dev, 0x90c0, 0x030c, 0x00000001);
nv_mthd(dev, 0x90c0, 0x1944, 0x00000000);
nv_mthd(dev, 0x90c0, 0x0758, 0x00000100);
@ -1471,14 +1488,20 @@ nvc0_grctx_generate_shaders(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
if (dev_priv->chipset != 0xc1) {
nv_wr32(dev, 0x405800, 0x078000bf);
nv_wr32(dev, 0x405830, 0x02180000);
} else {
if (dev_priv->chipset == 0xd9) {
nv_wr32(dev, 0x405800, 0x0f8000bf);
nv_wr32(dev, 0x405830, 0x02180218);
nv_wr32(dev, 0x405834, 0x08000000);
} else
if (dev_priv->chipset == 0xc1) {
nv_wr32(dev, 0x405800, 0x0f8000bf);
nv_wr32(dev, 0x405830, 0x02180218);
nv_wr32(dev, 0x405834, 0x00000000);
} else {
nv_wr32(dev, 0x405800, 0x078000bf);
nv_wr32(dev, 0x405830, 0x02180000);
nv_wr32(dev, 0x405834, 0x00000000);
}
nv_wr32(dev, 0x405834, 0x00000000);
nv_wr32(dev, 0x405838, 0x00000000);
nv_wr32(dev, 0x405854, 0x00000000);
nv_wr32(dev, 0x405870, 0x00000001);
@ -1509,7 +1532,10 @@ nvc0_grctx_generate_unk64xx(struct drm_device *dev)
nv_wr32(dev, 0x4064ac, 0x00003fff);
nv_wr32(dev, 0x4064b4, 0x00000000);
nv_wr32(dev, 0x4064b8, 0x00000000);
if (dev_priv->chipset == 0xc1) {
if (dev_priv->chipset == 0xd9)
nv_wr32(dev, 0x4064bc, 0x00000000);
if (dev_priv->chipset == 0xc1 ||
dev_priv->chipset == 0xd9) {
nv_wr32(dev, 0x4064c0, 0x80140078);
nv_wr32(dev, 0x4064c4, 0x0086ffff);
}
@ -1550,10 +1576,23 @@ nvc0_grctx_generate_rop(struct drm_device *dev)
/* ROPC_BROADCAST */
nv_wr32(dev, 0x408800, 0x02802a3c);
nv_wr32(dev, 0x408804, 0x00000040);
nv_wr32(dev, 0x408808, chipset != 0xc1 ? 0x0003e00d : 0x1003e005);
nv_wr32(dev, 0x408900, 0x3080b801);
nv_wr32(dev, 0x408904, chipset != 0xc1 ? 0x02000001 : 0x62000001);
nv_wr32(dev, 0x408908, 0x00c80929);
if (chipset == 0xd9) {
nv_wr32(dev, 0x408808, 0x1043e005);
nv_wr32(dev, 0x408900, 0x3080b801);
nv_wr32(dev, 0x408904, 0x1043e005);
nv_wr32(dev, 0x408908, 0x00c8102f);
} else
if (chipset == 0xc1) {
nv_wr32(dev, 0x408808, 0x1003e005);
nv_wr32(dev, 0x408900, 0x3080b801);
nv_wr32(dev, 0x408904, 0x62000001);
nv_wr32(dev, 0x408908, 0x00c80929);
} else {
nv_wr32(dev, 0x408808, 0x0003e00d);
nv_wr32(dev, 0x408900, 0x3080b801);
nv_wr32(dev, 0x408904, 0x02000001);
nv_wr32(dev, 0x408908, 0x00c80929);
}
nv_wr32(dev, 0x40890c, 0x00000000);
nv_wr32(dev, 0x408980, 0x0000011d);
}
@ -1572,7 +1611,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
nv_wr32(dev, 0x418408, 0x00000000);
nv_wr32(dev, 0x41840c, 0x00001008);
nv_wr32(dev, 0x418410, 0x0fff0fff);
nv_wr32(dev, 0x418414, 0x00200fff);
nv_wr32(dev, 0x418414, chipset != 0xd9 ? 0x00200fff : 0x02200fff);
nv_wr32(dev, 0x418450, 0x00000000);
nv_wr32(dev, 0x418454, 0x00000000);
nv_wr32(dev, 0x418458, 0x00000000);
@ -1587,14 +1626,17 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
nv_wr32(dev, 0x418700, 0x00000002);
nv_wr32(dev, 0x418704, 0x00000080);
nv_wr32(dev, 0x418708, 0x00000000);
nv_wr32(dev, 0x41870c, 0x07c80000);
nv_wr32(dev, 0x41870c, chipset != 0xd9 ? 0x07c80000 : 0x00000000);
nv_wr32(dev, 0x418710, 0x00000000);
nv_wr32(dev, 0x418800, 0x0006860a);
nv_wr32(dev, 0x418800, chipset != 0xd9 ? 0x0006860a : 0x7006860a);
nv_wr32(dev, 0x418808, 0x00000000);
nv_wr32(dev, 0x41880c, 0x00000000);
nv_wr32(dev, 0x418810, 0x00000000);
nv_wr32(dev, 0x418828, 0x00008442);
nv_wr32(dev, 0x418830, chipset != 0xc1 ? 0x00000001 : 0x10000001);
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x418830, 0x10000001);
else
nv_wr32(dev, 0x418830, 0x00000001);
nv_wr32(dev, 0x4188d8, 0x00000008);
nv_wr32(dev, 0x4188e0, 0x01000000);
nv_wr32(dev, 0x4188e8, 0x00000000);
@ -1602,7 +1644,12 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
nv_wr32(dev, 0x4188f0, 0x00000000);
nv_wr32(dev, 0x4188f4, 0x00000000);
nv_wr32(dev, 0x4188f8, 0x00000000);
nv_wr32(dev, 0x4188fc, chipset != 0xc1 ? 0x00100000 : 0x00100018);
if (chipset == 0xd9)
nv_wr32(dev, 0x4188fc, 0x20100008);
else if (chipset == 0xc1)
nv_wr32(dev, 0x4188fc, 0x00100018);
else
nv_wr32(dev, 0x4188fc, 0x00100000);
nv_wr32(dev, 0x41891c, 0x00ff00ff);
nv_wr32(dev, 0x418924, 0x00000000);
nv_wr32(dev, 0x418928, 0x00ffff00);
@ -1616,7 +1663,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
nv_wr32(dev, 0x418a14 + (i * 0x20), 0x00000000);
nv_wr32(dev, 0x418a18 + (i * 0x20), 0x00000000);
}
nv_wr32(dev, 0x418b00, 0x00000000);
nv_wr32(dev, 0x418b00, chipset != 0xd9 ? 0x00000000 : 0x00000006);
nv_wr32(dev, 0x418b08, 0x0a418820);
nv_wr32(dev, 0x418b0c, 0x062080e6);
nv_wr32(dev, 0x418b10, 0x020398a4);
@ -1633,7 +1680,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
nv_wr32(dev, 0x418c24, 0x00000000);
nv_wr32(dev, 0x418c28, 0x00000000);
nv_wr32(dev, 0x418c2c, 0x00000000);
if (chipset == 0xc1)
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x418c6c, 0x00000001);
nv_wr32(dev, 0x418c80, 0x20200004);
nv_wr32(dev, 0x418c8c, 0x00000001);
@ -1653,7 +1700,10 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
nv_wr32(dev, 0x419818, 0x00000000);
nv_wr32(dev, 0x41983c, 0x00038bc7);
nv_wr32(dev, 0x419848, 0x00000000);
nv_wr32(dev, 0x419864, chipset != 0xc1 ? 0x0000012a : 0x00000129);
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x419864, 0x00000129);
else
nv_wr32(dev, 0x419864, 0x0000012a);
nv_wr32(dev, 0x419888, 0x00000000);
nv_wr32(dev, 0x419a00, 0x000001f0);
nv_wr32(dev, 0x419a04, 0x00000001);
@ -1663,7 +1713,9 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
nv_wr32(dev, 0x419a14, 0x00000200);
nv_wr32(dev, 0x419a1c, 0x00000000);
nv_wr32(dev, 0x419a20, 0x00000800);
if (chipset != 0xc0 && chipset != 0xc8)
if (chipset == 0xd9)
nv_wr32(dev, 0x00419ac4, 0x0017f440);
else if (chipset != 0xc0 && chipset != 0xc8)
nv_wr32(dev, 0x00419ac4, 0x0007f440);
nv_wr32(dev, 0x419b00, 0x0a418820);
nv_wr32(dev, 0x419b04, 0x062080e6);
@ -1672,21 +1724,33 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
nv_wr32(dev, 0x419b10, 0x0a418820);
nv_wr32(dev, 0x419b14, 0x000000e6);
nv_wr32(dev, 0x419bd0, 0x00900103);
nv_wr32(dev, 0x419be0, chipset != 0xc1 ? 0x00000001 : 0x00400001);
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x419be0, 0x00400001);
else
nv_wr32(dev, 0x419be0, 0x00000001);
nv_wr32(dev, 0x419be4, 0x00000000);
nv_wr32(dev, 0x419c00, 0x00000002);
nv_wr32(dev, 0x419c00, chipset != 0xd9 ? 0x00000002 : 0x0000000a);
nv_wr32(dev, 0x419c04, 0x00000006);
nv_wr32(dev, 0x419c08, 0x00000002);
nv_wr32(dev, 0x419c20, 0x00000000);
if (chipset == 0xce || chipset == 0xcf)
if (dev_priv->chipset == 0xd9) {
nv_wr32(dev, 0x419c24, 0x00084210);
nv_wr32(dev, 0x419c28, 0x3cf3cf3c);
nv_wr32(dev, 0x419cb0, 0x00020048);
else
} else
if (chipset == 0xce || chipset == 0xcf) {
nv_wr32(dev, 0x419cb0, 0x00020048);
} else {
nv_wr32(dev, 0x419cb0, 0x00060048);
}
nv_wr32(dev, 0x419ce8, 0x00000000);
nv_wr32(dev, 0x419cf4, 0x00000183);
nv_wr32(dev, 0x419d20, chipset != 0xc1 ? 0x02180000 : 0x12180000);
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x419d20, 0x12180000);
else
nv_wr32(dev, 0x419d20, 0x02180000);
nv_wr32(dev, 0x419d24, 0x00001fff);
if (chipset == 0xc1)
if (chipset == 0xc1 || chipset == 0xd9)
nv_wr32(dev, 0x419d44, 0x02180218);
nv_wr32(dev, 0x419e04, 0x00000000);
nv_wr32(dev, 0x419e08, 0x00000000);
@ -1986,6 +2050,10 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
nv_icmd(dev, 0x00000215, 0x00000040);
nv_icmd(dev, 0x00000216, 0x00000040);
nv_icmd(dev, 0x00000217, 0x00000040);
if (dev_priv->chipset == 0xd9) {
for (i = 0x0400; i <= 0x0417; i++)
nv_icmd(dev, i, 0x00000040);
}
nv_icmd(dev, 0x00000218, 0x0000c080);
nv_icmd(dev, 0x00000219, 0x0000c080);
nv_icmd(dev, 0x0000021a, 0x0000c080);
@ -1994,6 +2062,10 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
nv_icmd(dev, 0x0000021d, 0x0000c080);
nv_icmd(dev, 0x0000021e, 0x0000c080);
nv_icmd(dev, 0x0000021f, 0x0000c080);
if (dev_priv->chipset == 0xd9) {
for (i = 0x0440; i <= 0x0457; i++)
nv_icmd(dev, i, 0x0000c080);
}
nv_icmd(dev, 0x000000ad, 0x0000013e);
nv_icmd(dev, 0x000000e1, 0x00000010);
nv_icmd(dev, 0x00000290, 0x00000000);
@ -2556,7 +2628,8 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
nv_icmd(dev, 0x0000053f, 0xffff0000);
nv_icmd(dev, 0x00000585, 0x0000003f);
nv_icmd(dev, 0x00000576, 0x00000003);
if (dev_priv->chipset == 0xc1)
if (dev_priv->chipset == 0xc1 ||
dev_priv->chipset == 0xd9)
nv_icmd(dev, 0x0000057b, 0x00000059);
nv_icmd(dev, 0x00000586, 0x00000040);
nv_icmd(dev, 0x00000582, 0x00000080);
@ -2658,6 +2731,8 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
nv_icmd(dev, 0x00000957, 0x00000003);
nv_icmd(dev, 0x0000095e, 0x20164010);
nv_icmd(dev, 0x0000095f, 0x00000020);
if (dev_priv->chipset == 0xd9)
nv_icmd(dev, 0x0000097d, 0x00000020);
nv_icmd(dev, 0x00000683, 0x00000006);
nv_icmd(dev, 0x00000685, 0x003fffff);
nv_icmd(dev, 0x00000687, 0x00000c48);

59
drivers/gpu/drm/nouveau/nvc0_grgpc.fuc
View File

@ -82,6 +82,11 @@ chipsets:
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvcf_tpc_mmio_tail
.b8 0xd9 0 0 0
.b16 #nvd9_gpc_mmio_head
.b16 #nvd9_gpc_mmio_tail
.b16 #nvd9_tpc_mmio_head
.b16 #nvd9_tpc_mmio_tail
.b8 0 0 0 0
// GPC mmio lists
@ -114,6 +119,35 @@ nvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1);
nvc1_gpc_mmio_tail:
nvd9_gpc_mmio_head:
mmctx_data(0x000380, 1)
mmctx_data(0x000400, 2)
mmctx_data(0x00040c, 3)
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
mmctx_data(0x000700, 5)
mmctx_data(0x000800, 1)
mmctx_data(0x000808, 3)
mmctx_data(0x000828, 1)
mmctx_data(0x000830, 1)
mmctx_data(0x0008d8, 1)
mmctx_data(0x0008e0, 1)
mmctx_data(0x0008e8, 6)
mmctx_data(0x00091c, 1)
mmctx_data(0x000924, 3)
mmctx_data(0x000b00, 1)
mmctx_data(0x000b08, 6)
mmctx_data(0x000bb8, 1)
mmctx_data(0x000c08, 1)
mmctx_data(0x000c10, 8)
mmctx_data(0x000c6c, 1)
mmctx_data(0x000c80, 1)
mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvd9_gpc_mmio_tail:
// TPC mmio lists
nvc0_tpc_mmio_head:
mmctx_data(0x000018, 1)
@ -146,6 +180,31 @@ nvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1)
nvc1_tpc_mmio_tail:
nvd9_tpc_mmio_head:
mmctx_data(0x000018, 1)
mmctx_data(0x00003c, 1)
mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
mmctx_data(0x00021c, 2)
mmctx_data(0x0002c4, 1)
mmctx_data(0x000300, 6)
mmctx_data(0x0003d0, 1)
mmctx_data(0x0003e0, 2)
mmctx_data(0x000400, 3)
mmctx_data(0x000420, 3)
mmctx_data(0x0004b0, 1)
mmctx_data(0x0004e8, 1)
mmctx_data(0x0004f4, 1)
mmctx_data(0x000520, 2)
mmctx_data(0x000544, 1)
mmctx_data(0x000604, 4)
mmctx_data(0x000644, 20)
mmctx_data(0x000698, 1)
mmctx_data(0x0006e0, 1)
mmctx_data(0x000750, 3)
nvd9_tpc_mmio_tail:
.section #nvc0_grgpc_code
bra #init

80
drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h
View File

@ -25,26 +25,29 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000,
0x00000000,
0x000000c0,
0x011c00bc,
0x01700120,
0x012800c8,
0x01e40194,
0x000000c1,
0x012000bc,
0x01840120,
0x012c00c8,
0x01f80194,
0x000000c3,
0x011c00bc,
0x01800120,
0x012800c8,
0x01f40194,
0x000000c4,
0x011c00bc,
0x01800120,
0x012800c8,
0x01f40194,
0x000000c8,
0x011c00bc,
0x01700120,
0x012800c8,
0x01e40194,
0x000000ce,
0x011c00bc,
0x01800120,
0x012800c8,
0x01f40194,
0x000000cf,
0x011c00bc,
0x017c0120,
0x012800c8,
0x01f00194,
0x000000d9,
0x0194012c,
0x025401f8,
0x00000000,
0x00000380,
0x14000400,
@ -71,6 +74,32 @@ uint32_t nvc0_grgpc_data[] = {
0x08001000,
0x00001014,
0x00000c6c,
0x00000380,
0x04000400,
0x0800040c,
0x20000450,
0x00000600,
0x00000684,
0x10000700,
0x00000800,
0x08000808,
0x00000828,
0x00000830,
0x000008d8,
0x000008e0,
0x140008e8,
0x0000091c,
0x08000924,
0x00000b00,
0x14000b08,
0x00000bb8,
0x00000c08,
0x1c000c10,
0x00000c6c,
0x00000c80,
0x00000c8c,
0x08001000,
0x00001014,
0x00000018,
0x0000003c,
0x00000048,
@ -96,6 +125,29 @@ uint32_t nvc0_grgpc_data[] = {
0x000006e0,
0x000004bc,
0x00000544,
0x00000018,
0x0000003c,
0x00000048,
0x00000064,
0x00000088,
0x14000200,
0x0400021c,
0x000002c4,
0x14000300,
0x000003d0,
0x040003e0,
0x08000400,
0x08000420,
0x000004b0,
0x000004e8,
0x000004f4,
0x04000520,
0x00000544,
0x0c000604,
0x4c000644,
0x00000698,
0x000006e0,
0x08000750,
};
uint32_t nvc0_grgpc_code[] = {

45
drivers/gpu/drm/nouveau/nvc0_grhub.fuc
View File

@ -59,6 +59,9 @@ chipsets:
.b8 0xcf 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b8 0xd9 0 0 0
.b16 #nvd9_hub_mmio_head
.b16 #nvd9_hub_mmio_tail
.b8 0 0 0 0
nvc0_hub_mmio_head:
@ -105,6 +108,48 @@ nvc0_hub_mmio_tail:
mmctx_data(0x4064c0, 2)
nvc1_hub_mmio_tail:
nvd9_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
mmctx_data(0x404004, 10)
mmctx_data(0x404044, 1)
mmctx_data(0x404094, 14)
mmctx_data(0x4040d0, 7)
mmctx_data(0x4040f8, 1)
mmctx_data(0x404130, 3)
mmctx_data(0x404150, 3)
mmctx_data(0x404164, 2)
mmctx_data(0x404178, 2)
mmctx_data(0x404200, 8)
mmctx_data(0x404404, 14)
mmctx_data(0x404460, 4)
mmctx_data(0x404480, 1)
mmctx_data(0x404498, 1)
mmctx_data(0x404604, 4)
mmctx_data(0x404618, 32)
mmctx_data(0x404698, 21)
mmctx_data(0x4046f0, 2)
mmctx_data(0x404700, 22)
mmctx_data(0x405800, 1)
mmctx_data(0x405830, 3)
mmctx_data(0x405854, 1)
mmctx_data(0x405870, 4)
mmctx_data(0x405a00, 2)
mmctx_data(0x405a18, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 2)
mmctx_data(0x4064b4, 5)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
mmctx_data(0x408000, 7)
mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408900, 4)
mmctx_data(0x408980, 1)
nvd9_hub_mmio_tail:
.align 256
chan_data:
chan_mmio_count: .b32 0

96
drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h
View File

@ -23,19 +23,21 @@ uint32_t nvc0_grhub_data[] = {
0x00000000,
0x00000000,
0x000000c0,
0x01340098,
0x013c00a0,
0x000000c1,
0x01380098,
0x014000a0,
0x000000c3,
0x01340098,
0x013c00a0,
0x000000c4,
0x01340098,
0x013c00a0,
0x000000c8,
0x01340098,
0x013c00a0,
0x000000ce,
0x01340098,
0x013c00a0,
0x000000cf,
0x01340098,
0x013c00a0,
0x000000d9,
0x01dc0140,
0x00000000,
0x0417e91c,
0x04400204,
@ -77,47 +79,45 @@ uint32_t nvc0_grhub_data[] = {
0x0c408900,
0x00408980,
0x044064c0,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x0417e91c,
0x04400204,
0x24404004,
0x00404044,
0x34404094,
0x184040d0,
0x004040f8,
0x08404130,
0x08404150,
0x04404164,
0x04404178,
0x1c404200,
0x34404404,
0x0c404460,
0x00404480,
0x00404498,
0x0c404604,
0x7c404618,
0x50404698,
0x044046f0,
0x54404700,
0x00405800,
0x08405830,
0x00405854,
0x0c405870,
0x04405a00,
0x00405a18,
0x00406020,
0x0c406028,
0x044064a8,
0x104064b4,
0x00407804,
0x1440780c,
0x004078bc,
0x18408000,
0x00408064,
0x08408800,
0x0c408900,
0x00408980,
0x00000000,
0x00000000,
0x00000000,