Devicetree updates for v5.1:
- Fix a unittest failure on UML. Preparation for converting to kunit test framework. - Add annotations to dtx_diff output - Fix unittest reporting of expected error - Move DMA configuration for virtual devices into the driver that needs it (s5p-mfc) - Vendor prefixes for feiyang and techstar - Convert ARM GIC, GICv3, and L2x0 to DT schema - Add r8a7778/9 HSCIF serial bindings -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAlyC0hoQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhwzMdD/93737AUFqQNfMXlsrZs/OS9dGTQdYtuFOw Z2643O1l5QTPAleBqQWVGpxph67pQf3uZ+7zAsknJkweysMaDG1Ej22sFnyIM+Hh +IeLBYOtB7hd6FSCX40apT6Jlw2KG7Lqk0JvXVv7yXJRptsf7R6oUw8GoxxUBbsp 4fL1IwuAyq3TrMtGETl7MW4QJma9A8zo9ngQSiRQr9yflROmE1dXjge+KPHOsTRr 9PU6NSgsuUG0eBw9stL4bDZwXXGb3sEcXaItY5A37JTI6bLgPuk8cA4lp+gTL5RK 77uGs8rbe8WqFPWeMmDwRdbSDasb52NDfGBG5Dj7n7tHVP7rubyA1XK3fVK5udjZ hHhQa0G5gLBnd9/7Je8udkvwH9ef/BjnHp1KFOBrCMLCgYX+QZQZUNwuTI5/l6E3 A/dOo6JG+rshtI3P3Up69XOu1KMhacNVu/TTHVGkUeq5vf+iKr1BYu2VsVIHdQh7 hdJ6syheq3qHBAOOuB5Z+yyFzwh1w98gpqlG8lUSYjnochej4YSgNTMef9vhdWZg vTdP/XNnYvH9XTqxSAhfIxUWeaggrngYQCQhci8F57DskKkPKeyFhxo7ODGD4bI6 hXcUgk2OtEF2Sgk+X9XCtI5vJXuXvGxmlpZpdUe7LiVE3CnOwfFxvLfIhpw+2AIp /7S2Khwnsg== =CnTd -----END PGP SIGNATURE----- Merge tag 'devicetree-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree updates from Rob Herring: - Fix a unittest failure on UML. Preparation for converting to kunit test framework. - Add annotations to dtx_diff output - Fix unittest reporting of expected error - Move DMA configuration for virtual devices into the driver that needs it (s5p-mfc) - Vendor prefixes for feiyang and techstar - Convert ARM GIC, GICv3, and L2x0 to DT schema - Add r8a7778/9 HSCIF serial bindings * tag 'devicetree-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: of: unittest: unflatten device tree on UML when testing dt-bindings: Add vendor prefix for feiyang dt-bindings: Add vendor prefix for techstar dt-bindings: display: add missing semicolon in example of: mark early_init_dt_alloc_reserved_memory_arch static of: add dtc annotations functionality to dtx_diff of: unittest: add caution to function header comment of: unittest: remove report of expected error dt-bindings: interrupt-controller: Convert ARM GICv3 to json-schema dt-bindings: interrupt-controller: Convert ARM GIC to json-schema dt-bindings: arm: l2x0: Convert L2 cache to json-schema media: s5p-mfc: Fix memdev DMA configuration dt-bindings: serial: sh-sci: Document r8a7778/9 HSCIF bindings
This commit is contained in:
Linus Torvalds
commit
065b6c4c91
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@ -1,114 +0,0 @@
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* ARM L2 Cache Controller
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||||
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ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
|
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PL310 and variants) based level 2 cache controller. All these various implementations
|
||||
of the L2 cache controller have compatible programming models (Note 1).
|
||||
Some of the properties that are just prefixed "cache-*" are taken from section
|
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3.7.3 of the Devicetree Specification which can be found at:
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https://www.devicetree.org/specifications/
|
||||
|
||||
The ARM L2 cache representation in the device tree should be done as follows:
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Required properties:
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- compatible : should be one of:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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"bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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"brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
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offset needs to be added to the address before passing down to the L2
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cache controller
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"marvell,aurora-system-cache": Marvell Controller designed to be
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compatible with the ARM one, with system cache mode (meaning
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maintenance operations on L1 are broadcasted to the L2 and L2
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performs the same operation).
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"marvell,aurora-outer-cache": Marvell Controller designed to be
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||||
compatible with the ARM one with outer cache mode.
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"marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
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with arm,pl310-cache controller.
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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registers.
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Optional properties:
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Minimum valid values are 1. Controllers
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without setup latency control should use a value of 0.
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- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Controllers without setup latency control
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should use 0. Controllers without separate read and write Tag RAM latency
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values should only use the first cell.
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- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
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- arm,filter-ranges : <start length> Starting address and length of window to
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||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
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- arm,io-coherent : indicates that the system is operating in an hardware
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I/O coherent mode. Valid only when the arm,pl310-cache compatible
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string is used.
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- interrupts : 1 combined interrupt.
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- cache-size : specifies the size in bytes of the cache
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- cache-sets : specifies the number of associativity sets of the cache
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- cache-block-size : specifies the size in bytes of a cache block
|
||||
- cache-line-size : specifies the size in bytes of a line in the cache,
|
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if this is not specified, the line size is assumed to be equal to the
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cache block size
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- cache-id-part: cache id part number to be used if it is not present
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||||
on hardware
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- wt-override: If present then L2 is forced to Write through mode
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- arm,double-linefill : Override double linefill enable setting. Enable if
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non-zero, disable if zero.
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- arm,double-linefill-incr : Override double linefill on INCR read. Enable
|
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if non-zero, disable if zero.
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- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
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- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
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disable if zero.
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||||
- arm,prefetch-offset : Override prefetch offset value. Valid values are
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0-7, 15, 23, and 31.
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- arm,shared-override : The default behavior of the L220 or PL310 cache
|
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controllers with respect to the shareable attribute is to transform "normal
|
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memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
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or "write through no write allocate" (for writes).
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On systems where this may cause DMA buffer corruption, this property must be
|
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specified to indicate that such transforms are precluded.
|
||||
- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
|
||||
- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
|
||||
- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
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- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
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(forcibly enable), property absent (retain settings set by firmware)
|
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- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
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<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
|
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- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
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write (PL310)
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Example:
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x80000000 0x8000000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <45>;
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};
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Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
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integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
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||||
in the kernel at all.
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|
|
@ -0,0 +1,248 @@
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|||
# SPDX-License-Identifier: GPL-2.0
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||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: ARM L2 Cache Controller
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||||
|
||||
maintainers:
|
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- Rob Herring <robh@kernel.org>
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|
||||
description: |+
|
||||
ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
|
||||
PL220/PL310 and variants) based level 2 cache controller. All these various
|
||||
implementations of the L2 cache controller have compatible programming
|
||||
models (Note 1). Some of the properties that are just prefixed "cache-*" are
|
||||
taken from section 3.7.3 of the Devicetree Specification which can be found
|
||||
at:
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
Note 1: The description in this document doesn't apply to integrated L2
|
||||
cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
|
||||
integrated L2 controllers are assumed to be all preconfigured by
|
||||
early secure boot code. Thus no need to deal with their configuration
|
||||
in the kernel at all.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- arm,pl310-cache
|
||||
- arm,l220-cache
|
||||
- arm,l210-cache
|
||||
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
|
||||
- bcm,bcm11351-a2-pl310-cache
|
||||
# For Broadcom bcm11351 chipset where an
|
||||
# offset needs to be added to the address before passing down to the L2
|
||||
# cache controller
|
||||
- brcm,bcm11351-a2-pl310-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one, with system cache mode (meaning
|
||||
# maintenance operations on L1 are broadcasted to the L2 and L2
|
||||
# performs the same operation).
|
||||
- marvell,aurora-system-cache
|
||||
# Marvell Controller designed to be
|
||||
# compatible with the ARM one with outer cache mode.
|
||||
- marvell,aurora-outer-cache
|
||||
# Marvell Tauros3 cache controller, compatible
|
||||
# with arm,pl310-cache controller.
|
||||
- marvell,tauros3-cache
|
||||
|
||||
cache-level:
|
||||
const: 2
|
||||
|
||||
cache-unified: true
|
||||
cache-size: true
|
||||
cache-sets: true
|
||||
cache-block-size: true
|
||||
cache-line-size: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
arm,data-latency:
|
||||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,tag-latency:
|
||||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,dirty-latency:
|
||||
description: Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
maximum: 8
|
||||
|
||||
arm,filter-ranges:
|
||||
description: <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
I/O coherent mode. Valid only when the arm,pl310-cache compatible
|
||||
string is used.
|
||||
type: boolean
|
||||
|
||||
interrupts:
|
||||
# Either a single combined interrupt or up to 9 individual interrupts
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
cache-id-part:
|
||||
description: cache id part number to be used if it is not present
|
||||
on hardware
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
wt-override:
|
||||
description: If present then L2 is forced to Write through mode
|
||||
type: boolean
|
||||
|
||||
arm,double-linefill:
|
||||
description: Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,double-linefill-incr:
|
||||
description: Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,double-linefill-wrap:
|
||||
description: Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,prefetch-drop:
|
||||
description: Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,prefetch-offset:
|
||||
description: Override prefetch offset value.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
|
||||
|
||||
arm,shared-override:
|
||||
description: The default behavior of the L220 or PL310 cache
|
||||
controllers with respect to the shareable attribute is to transform "normal
|
||||
memory non-cacheable transactions" into "cacheable no allocate" (for reads)
|
||||
or "write through no write allocate" (for writes).
|
||||
On systems where this may cause DMA buffer corruption, this property must
|
||||
be specified to indicate that such transforms are precluded.
|
||||
type: boolean
|
||||
|
||||
arm,parity-enable:
|
||||
description: enable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,parity-disable:
|
||||
description: disable parity checking on the L2 cache (L220 or PL310).
|
||||
type: boolean
|
||||
|
||||
arm,outer-sync-disable:
|
||||
description: disable the outer sync operation on the L2 cache.
|
||||
Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
|
||||
will randomly hang unless outer sync operations are disabled.
|
||||
type: boolean
|
||||
|
||||
prefetch-data:
|
||||
description: |
|
||||
Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
prefetch-instr:
|
||||
description: |
|
||||
Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,dynamic-clock-gating:
|
||||
description: |
|
||||
L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,standby-mode:
|
||||
description: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
|
||||
arm,early-bresp-disable:
|
||||
description: Disable the CA9 optimization Early BRESP (PL310)
|
||||
type: boolean
|
||||
|
||||
arm,full-line-zero-disable:
|
||||
description: Disable the CA9 optimization Full line of zero
|
||||
write (PL310)
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cache-unified
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cache-controller@fff12000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfff12000 0x1000>;
|
||||
arm,data-latency = <1 1 1>;
|
||||
arm,tag-latency = <2 2 2>;
|
||||
arm,filter-ranges = <0x80000000 0x8000000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
interrupts = <45>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -20,7 +20,7 @@ Example:
|
|||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
|
||||
}
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,175 +0,0 @@
|
|||
* ARM Generic Interrupt Controller, version 3
|
||||
|
||||
AArch64 SMP cores are often associated with a GICv3, providing Private
|
||||
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
|
||||
Software Generated Interrupts (SGI), and Locality-specific Peripheral
|
||||
Interrupts (LPI).
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should at least contain "arm,gic-v3" or either
|
||||
"qcom,msm8996-gic-v3", "arm,gic-v3" for msm8996 SoCs
|
||||
to address SoC specific bugs/quirks
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. Must be a single cell with a value of at least 3.
|
||||
If the system requires describing PPI affinity, then the value must
|
||||
be at least 4.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts. Other values are reserved for future use.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = edge triggered
|
||||
4 = level triggered
|
||||
|
||||
The 4th cell is a phandle to a node describing a set of CPUs this
|
||||
interrupt is affine to. The interrupt must be a PPI, and the node
|
||||
pointed must be a subnode of the "ppi-partitions" subnode. For
|
||||
interrupt types other than PPI or PPIs that are not partitionned,
|
||||
this cell must be zero. See the "ppi-partitions" node description
|
||||
below.
|
||||
|
||||
Cells 5 and beyond are reserved for future use and must have a value
|
||||
of 0 if present.
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC
|
||||
registers, in the following order:
|
||||
- GIC Distributor interface (GICD)
|
||||
- GIC Redistributors (GICR), one range per redistributor region
|
||||
- GIC CPU interface (GICC)
|
||||
- GIC Hypervisor interface (GICH)
|
||||
- GIC Virtual CPU interface (GICV)
|
||||
|
||||
GICC, GICH and GICV are optional.
|
||||
|
||||
- interrupts : Interrupt source of the VGIC maintenance interrupt.
|
||||
|
||||
Optional
|
||||
|
||||
- redistributor-stride : If using padding pages, specifies the stride
|
||||
of consecutive redistributors. Must be a multiple of 64kB.
|
||||
|
||||
- #redistributor-regions: The number of independent contiguous regions
|
||||
occupied by the redistributors. Required if more than one such
|
||||
region is present.
|
||||
|
||||
- msi-controller: Boolean property. Identifies the node as an MSI
|
||||
controller. Only present if the Message Based Interrupt
|
||||
functionnality is being exposed by the HW, and the mbi-ranges
|
||||
property present.
|
||||
|
||||
- mbi-ranges: A list of pairs <intid span>, where "intid" is the first
|
||||
SPI of a range that can be used an MBI, and "span" the size of that
|
||||
range. Multiple ranges can be provided. Requires "msi-controller" to
|
||||
be set.
|
||||
|
||||
- mbi-alias: Address property. Base address of an alias of the GICD
|
||||
region containing only the {SET,CLR}SPI registers to be used if
|
||||
isolation is required, and if supported by the HW.
|
||||
|
||||
Sub-nodes:
|
||||
|
||||
PPI affinity can be expressed as a single "ppi-partitions" node,
|
||||
containing a set of sub-nodes, each with the following property:
|
||||
- affinity: Should be a list of phandles to CPU nodes (as described in
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml).
|
||||
|
||||
GICv3 has one or more Interrupt Translation Services (ITS) that are
|
||||
used to route Message Signalled Interrupts (MSI) to the CPUs.
|
||||
|
||||
These nodes must have the following properties:
|
||||
- compatible : Should at least contain "arm,gic-v3-its".
|
||||
- msi-controller : Boolean property. Identifies the node as an MSI controller
|
||||
- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
|
||||
which will generate the MSI.
|
||||
- reg: Specifies the base physical address and size of the ITS
|
||||
registers.
|
||||
|
||||
Optional:
|
||||
- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
|
||||
address and size of the pre-ITS window.
|
||||
|
||||
The main GIC node must contain the appropriate #address-cells,
|
||||
#size-cells and ranges properties for the reg property of all ITS
|
||||
nodes.
|
||||
|
||||
Examples:
|
||||
|
||||
gic: interrupt-controller@2cf00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x2f000000 0 0x10000>, // GICD
|
||||
<0x0 0x2f100000 0 0x200000>, // GICR
|
||||
<0x0 0x2c000000 0 0x2000>, // GICC
|
||||
<0x0 0x2c010000 0 0x2000>, // GICH
|
||||
<0x0 0x2c020000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
|
||||
msi-controller;
|
||||
mbi-ranges = <256 128>;
|
||||
|
||||
gic-its@2c200000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x0 0x2c200000 0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c010000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
redistributor-stride = <0x0 0x40000>; // 256kB stride
|
||||
#redistributor-regions = <2>;
|
||||
reg = <0x0 0x2c010000 0 0x10000>, // GICD
|
||||
<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
|
||||
<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
|
||||
<0x0 0x2c040000 0 0x2000>, // GICC
|
||||
<0x0 0x2c060000 0 0x2000>, // GICH
|
||||
<0x0 0x2c080000 0 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
|
||||
gic-its@2c200000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x0 0x2c200000 0 0x20000>;
|
||||
};
|
||||
|
||||
gic-its@2c400000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x0 0x2c400000 0 0x20000>;
|
||||
};
|
||||
|
||||
ppi-partitions {
|
||||
part0: interrupt-partition-0 {
|
||||
affinity = <&cpu0 &cpu2>;
|
||||
};
|
||||
|
||||
part1: interrupt-partition-1 {
|
||||
affinity = <&cpu1 &cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
device@0 {
|
||||
reg = <0 0 0 4>;
|
||||
interrupts = <1 1 4 &part0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Generic Interrupt Controller, version 3
|
||||
|
||||
maintainers:
|
||||
- Marc Zyngier <marc.zyngier@arm.com>
|
||||
|
||||
description: |
|
||||
AArch64 SMP cores are often associated with a GICv3, providing Private
|
||||
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
|
||||
Software Generated Interrupts (SGI), and Locality-specific Peripheral
|
||||
Interrupts (LPI).
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8996-gic-v3
|
||||
- const: arm,gic-v3
|
||||
- const: arm,gic-v3
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells":
|
||||
enum: [ 0, 1, 2 ]
|
||||
"#size-cells":
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
ranges: true
|
||||
|
||||
"#interrupt-cells":
|
||||
description: |
|
||||
Specifies the number of cells needed to encode an interrupt source.
|
||||
Must be a single cell with a value of at least 3.
|
||||
If the system requires describing PPI affinity, then the value must
|
||||
be at least 4.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts. Other values are reserved for future use.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = edge triggered
|
||||
4 = level triggered
|
||||
|
||||
The 4th cell is a phandle to a node describing a set of CPUs this
|
||||
interrupt is affine to. The interrupt must be a PPI, and the node
|
||||
pointed must be a subnode of the "ppi-partitions" subnode. For
|
||||
interrupt types other than PPI or PPIs that are not partitionned,
|
||||
this cell must be zero. See the "ppi-partitions" node description
|
||||
below.
|
||||
|
||||
Cells 5 and beyond are reserved for future use and must have a value
|
||||
of 0 if present.
|
||||
enum: [ 3, 4 ]
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Specifies base physical address(s) and size of the GIC
|
||||
registers, in the following order:
|
||||
- GIC Distributor interface (GICD)
|
||||
- GIC Redistributors (GICR), one range per redistributor region
|
||||
- GIC CPU interface (GICC)
|
||||
- GIC Hypervisor interface (GICH)
|
||||
- GIC Virtual CPU interface (GICV)
|
||||
|
||||
GICC, GICH and GICV are optional.
|
||||
minItems: 2
|
||||
maxItems: 4096 # Should be enough?
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Interrupt source of the VGIC maintenance interrupt.
|
||||
maxItems: 1
|
||||
|
||||
redistributor-stride:
|
||||
description:
|
||||
If using padding pages, specifies the stride of consecutive
|
||||
redistributors. Must be a multiple of 64kB.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint64
|
||||
- multipleOf: 0x10000
|
||||
exclusiveMinimum: 0
|
||||
|
||||
"#redistributor-regions":
|
||||
description:
|
||||
The number of independent contiguous regions occupied by the
|
||||
redistributors. Required if more than one such region is present.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- maximum: 4096 # Should be enough?
|
||||
|
||||
msi-controller:
|
||||
description:
|
||||
Only present if the Message Based Interrupt functionnality is
|
||||
being exposed by the HW, and the mbi-ranges property present.
|
||||
|
||||
mbi-ranges:
|
||||
description:
|
||||
A list of pairs <intid span>, where "intid" is the first SPI of a range
|
||||
that can be used an MBI, and "span" the size of that range. Multiple
|
||||
ranges can be provided.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
- items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
mbi-alias:
|
||||
description:
|
||||
Address property. Base address of an alias of the GICD region containing
|
||||
only the {SET,CLR}SPI registers to be used if isolation is required,
|
||||
and if supported by the HW.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
ppi-partitions:
|
||||
type: object
|
||||
description:
|
||||
PPI affinity can be expressed as a single "ppi-partitions" node,
|
||||
containing a set of sub-nodes.
|
||||
patternProperties:
|
||||
"^interrupt-partition-[0-9]+$":
|
||||
properties:
|
||||
affinity:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should be a list of phandles to CPU nodes (as described in
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml).
|
||||
|
||||
required:
|
||||
- affinity
|
||||
|
||||
dependencies:
|
||||
mbi-ranges: [ msi-controller ]
|
||||
msi-controller: [ mbi-ranges ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- interrupts
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^gic-its@": false
|
||||
"^interrupt-controller@[0-9a-f]+$": false
|
||||
# msi-controller is preferred, but allow other names
|
||||
"^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
|
||||
type: object
|
||||
description:
|
||||
GICv3 has one or more Interrupt Translation Services (ITS) that are
|
||||
used to route Message Signalled Interrupts (MSI) to the CPUs.
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,gic-v3-its
|
||||
|
||||
msi-controller: true
|
||||
|
||||
"#msi-cells":
|
||||
description:
|
||||
The single msi-cell is the DeviceID of the device which will generate
|
||||
the MSI.
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
description:
|
||||
Specifies the base physical address and size of the ITS registers.
|
||||
maxItems: 1
|
||||
|
||||
socionext,synquacer-pre-its:
|
||||
description:
|
||||
(u32, u32) tuple describing the untranslated
|
||||
address and size of the pre-ITS window.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- msi-controller
|
||||
- "#msi-cells"
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
gic: interrupt-controller@2cf00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
reg = <0x2f000000 0x10000>, // GICD
|
||||
<0x2f100000 0x200000>, // GICR
|
||||
<0x2c000000 0x2000>, // GICC
|
||||
<0x2c010000 0x2000>, // GICH
|
||||
<0x2c020000 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
|
||||
msi-controller;
|
||||
mbi-ranges = <256 128>;
|
||||
|
||||
msi-controller@2c200000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x2c200000 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
interrupt-controller@2c010000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
redistributor-stride = <0x0 0x40000>; // 256kB stride
|
||||
#redistributor-regions = <2>;
|
||||
reg = <0x2c010000 0x10000>, // GICD
|
||||
<0x2d000000 0x800000>, // GICR 1: CPUs 0-31
|
||||
<0x2e000000 0x800000>, // GICR 2: CPUs 32-63
|
||||
<0x2c040000 0x2000>, // GICC
|
||||
<0x2c060000 0x2000>, // GICH
|
||||
<0x2c080000 0x2000>; // GICV
|
||||
interrupts = <1 9 4>;
|
||||
|
||||
msi-controller@2c200000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x2c200000 0x20000>;
|
||||
};
|
||||
|
||||
msi-controller@2c400000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
reg = <0x2c400000 0x20000>;
|
||||
};
|
||||
|
||||
ppi-partitions {
|
||||
part0: interrupt-partition-0 {
|
||||
affinity = <&cpu0 &cpu2>;
|
||||
};
|
||||
|
||||
part1: interrupt-partition-1 {
|
||||
affinity = <&cpu1 &cpu3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
device@0 {
|
||||
reg = <0 4>;
|
||||
interrupts = <1 1 4 &part0>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,171 +0,0 @@
|
|||
* ARM Generic Interrupt Controller
|
||||
|
||||
ARM SMP cores are often associated with a GIC, providing per processor
|
||||
interrupts (PPI), shared processor interrupts (SPI) and software
|
||||
generated interrupts (SGI).
|
||||
|
||||
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
|
||||
Secondary GICs are cascaded into the upward interrupt controller and do not
|
||||
have PPIs or SGIs.
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"arm,arm1176jzf-devchip-gic"
|
||||
"arm,arm11mp-gic"
|
||||
"arm,cortex-a15-gic"
|
||||
"arm,cortex-a7-gic"
|
||||
"arm,cortex-a9-gic"
|
||||
"arm,eb11mp-gic"
|
||||
"arm,gic-400"
|
||||
"arm,pl390"
|
||||
"arm,tc11mp-gic"
|
||||
"brcm,brahma-b15-gic"
|
||||
"nvidia,tegra210-agic"
|
||||
"qcom,msm-8660-qgic"
|
||||
"qcom,msm-qgic2"
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The type shall be a <u32> and the value shall be 3.
|
||||
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = low-to-high edge triggered
|
||||
2 = high-to-low edge triggered (invalid for SPIs)
|
||||
4 = active high level-sensitive
|
||||
8 = active low level-sensitive (invalid for SPIs).
|
||||
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
|
||||
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
|
||||
the interrupt is wired to that CPU. Only valid for PPI interrupts.
|
||||
Also note that the configurability of PPI interrupts is IMPLEMENTATION
|
||||
DEFINED and as such not guaranteed to be present (most SoC available
|
||||
in 2014 seem to ignore the setting of this flag and use the hardware
|
||||
default value).
|
||||
|
||||
- reg : Specifies base physical address(s) and size of the GIC registers. The
|
||||
first region is the GIC distributor register base and size. The 2nd region is
|
||||
the GIC cpu interface register base and size.
|
||||
|
||||
Optional
|
||||
- interrupts : Interrupt source of the parent interrupt controller on
|
||||
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
|
||||
below).
|
||||
|
||||
- cpu-offset : per-cpu offset within the distributor and cpu interface
|
||||
regions, used when the GIC doesn't have banked registers. The offset is
|
||||
cpu-offset * cpu-nr.
|
||||
|
||||
- clocks : List of phandle and clock-specific pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names : List of names for the GIC clock input(s). Valid clock names
|
||||
depend on the GIC variant:
|
||||
"ic_clk" (for "arm,arm11mp-gic")
|
||||
"PERIPHCLKEN" (for "arm,cortex-a15-gic")
|
||||
"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
|
||||
"clk" (for "arm,gic-400" and "nvidia,tegra210")
|
||||
"gclk" (for "arm,pl390")
|
||||
|
||||
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
||||
the power controller specified by phandle, used when the GIC
|
||||
is part of a Power or Clock Domain.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff10100 0x100>;
|
||||
};
|
||||
|
||||
|
||||
* GIC virtualization extensions (VGIC)
|
||||
|
||||
For ARM cores that support the virtualization extensions, additional
|
||||
properties must be described (they only exist if the GIC is the
|
||||
primary interrupt controller).
|
||||
|
||||
Required properties:
|
||||
|
||||
- reg : Additional regions specifying the base physical address and
|
||||
size of the VGIC registers. The first additional region is the GIC
|
||||
virtual interface control register base and size. The 2nd additional
|
||||
region is the GIC virtual cpu interface register base and size.
|
||||
|
||||
- interrupts : VGIC maintenance interrupt.
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c002000 0x2000>,
|
||||
<0x2c004000 0x2000>,
|
||||
<0x2c006000 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
|
||||
* GICv2m extension for MSI/MSI-x support (Optional)
|
||||
|
||||
Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
|
||||
This is enabled by specifying v2m sub-node(s).
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : The value here should contain "arm,gic-v2m-frame".
|
||||
|
||||
- msi-controller : Identifies the node as an MSI controller.
|
||||
|
||||
- reg : GICv2m MSI interface register base and size
|
||||
|
||||
Optional properties:
|
||||
|
||||
- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
|
||||
value, this property should contain the SPI base of
|
||||
the MSI frame, overriding the HW value.
|
||||
|
||||
- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
|
||||
value, this property should contain the number of
|
||||
SPIs assigned to the frame, overriding the HW value.
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@e1101000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 8 0xf04>;
|
||||
ranges = <0 0 0 0xe1100000 0 0x100000>;
|
||||
reg = <0x0 0xe1110000 0 0x01000>,
|
||||
<0x0 0xe112f000 0 0x02000>,
|
||||
<0x0 0xe1140000 0 0x10000>,
|
||||
<0x0 0xe1160000 0 0x10000>;
|
||||
v2m0: v2m@8000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x80000 0 0x1000>;
|
||||
};
|
||||
|
||||
....
|
||||
|
||||
v2mN: v2m@9000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x90000 0 0x1000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM Generic Interrupt Controller v1 and v2
|
||||
|
||||
maintainers:
|
||||
- Marc Zyngier <marc.zyngier@arm.com>
|
||||
|
||||
description: |+
|
||||
ARM SMP cores are often associated with a GIC, providing per processor
|
||||
interrupts (PPI), shared processor interrupts (SPI) and software
|
||||
generated interrupts (SGI).
|
||||
|
||||
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
|
||||
Secondary GICs are cascaded into the upward interrupt controller and do not
|
||||
have PPIs or SGIs.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- arm,arm11mp-gic
|
||||
- arm,cortex-a15-gic
|
||||
- arm,cortex-a7-gic
|
||||
- arm,cortex-a5-gic
|
||||
- arm,cortex-a9-gic
|
||||
- arm,eb11mp-gic
|
||||
- arm,gic-400
|
||||
- arm,pl390
|
||||
- arm,tc11mp-gic
|
||||
- nvidia,tegra210-agic
|
||||
- qcom,msm-8660-qgic
|
||||
- qcom,msm-qgic2
|
||||
|
||||
- items:
|
||||
- const: arm,arm1176jzf-devchip-gic
|
||||
- const: arm,arm11mp-gic
|
||||
|
||||
- items:
|
||||
- const: brcm,brahma-b15-gic
|
||||
- const: arm,cortex-a15-gic
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells":
|
||||
enum: [ 0, 1 ]
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 3
|
||||
description: |
|
||||
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
||||
interrupts.
|
||||
|
||||
The 2nd cell contains the interrupt number for the interrupt type.
|
||||
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
||||
range [0-15].
|
||||
|
||||
The 3rd cell is the flags, encoded as follows:
|
||||
bits[3:0] trigger type and level flags.
|
||||
1 = low-to-high edge triggered
|
||||
2 = high-to-low edge triggered (invalid for SPIs)
|
||||
4 = active high level-sensitive
|
||||
8 = active low level-sensitive (invalid for SPIs).
|
||||
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
|
||||
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
|
||||
the interrupt is wired to that CPU. Only valid for PPI interrupts.
|
||||
Also note that the configurability of PPI interrupts is IMPLEMENTATION
|
||||
DEFINED and as such not guaranteed to be present (most SoC available
|
||||
in 2014 seem to ignore the setting of this flag and use the hardware
|
||||
default value).
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Specifies base physical address(s) and size of the GIC registers. The
|
||||
first region is the GIC distributor register base and size. The 2nd region
|
||||
is the GIC cpu interface register base and size.
|
||||
|
||||
For GICv2 with virtualization extensions, additional regions are
|
||||
required for specifying the base physical address and size of the VGIC
|
||||
registers. The first additional region is the GIC virtual interface
|
||||
control register base and size. The 2nd additional region is the GIC
|
||||
virtual cpu interface register base and size.
|
||||
minItems: 2
|
||||
maxItems: 4
|
||||
|
||||
interrupts:
|
||||
description: Interrupt source of the parent interrupt controller on
|
||||
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
|
||||
below).
|
||||
maxItems: 1
|
||||
|
||||
cpu-offset:
|
||||
description: per-cpu offset within the distributor and cpu interface
|
||||
regions, used when the GIC doesn't have banked registers. The offset
|
||||
is cpu-offset * cpu-nr.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
description: List of names for the GIC clock input(s). Valid clock names
|
||||
depend on the GIC variant.
|
||||
oneOf:
|
||||
- const: ic_clk # for "arm,arm11mp-gic"
|
||||
- const: PERIPHCLKEN # for "arm,cortex-a15-gic"
|
||||
- items: # for "arm,cortex-a9-gic"
|
||||
- const: PERIPHCLK
|
||||
- const: PERIPHCLKEN
|
||||
- const: clk # for "arm,gic-400" and "nvidia,tegra210"
|
||||
- const: gclk #for "arm,pl390"
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^v2m@[0-9a-f]+$":
|
||||
description: |
|
||||
* GICv2m extension for MSI/MSI-x support (Optional)
|
||||
|
||||
Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
|
||||
This is enabled by specifying v2m sub-node(s).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,gic-v2m-frame
|
||||
|
||||
msi-controller: true
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: GICv2m MSI interface register base and size
|
||||
|
||||
arm,msi-base-spi:
|
||||
description: When the MSI_TYPER register contains an incorrect value,
|
||||
this property should contain the SPI base of the MSI frame, overriding
|
||||
the HW value.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
arm,msi-num-spis:
|
||||
description: When the MSI_TYPER register contains an incorrect value,
|
||||
this property should contain the number of SPIs assigned to the
|
||||
frame, overriding the HW value.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- msi-controller
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// GICv1
|
||||
intc: interrupt-controller@fff11000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xfff11000 0x1000>,
|
||||
<0xfff10100 0x100>;
|
||||
};
|
||||
|
||||
- |
|
||||
// GICv2
|
||||
interrupt-controller@2c001000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c002000 0x2000>,
|
||||
<0x2c004000 0x2000>,
|
||||
<0x2c006000 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
- |
|
||||
// GICv2m extension for MSI/MSI-x support
|
||||
interrupt-controller@e1101000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-controller;
|
||||
interrupts = <1 8 0xf04>;
|
||||
ranges = <0 0 0 0xe1100000 0 0x100000>;
|
||||
reg = <0x0 0xe1110000 0 0x01000>,
|
||||
<0x0 0xe112f000 0 0x02000>,
|
||||
<0x0 0xe1140000 0 0x10000>,
|
||||
<0x0 0xe1160000 0 0x10000>;
|
||||
|
||||
v2m0: v2m@8000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x80000 0 0x1000>;
|
||||
};
|
||||
|
||||
//...
|
||||
|
||||
v2mN: v2m@9000 {
|
||||
compatible = "arm,gic-v2m-frame";
|
||||
msi-controller;
|
||||
reg = <0x0 0x90000 0 0x1000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -140,6 +140,7 @@ fairphone Fairphone B.V.
|
|||
faraday Faraday Technology Corporation
|
||||
fastrax Fastrax Oy
|
||||
fcs Fairchild Semiconductor
|
||||
feiyang Shenzhen Fly Young Technology Co.,LTD.
|
||||
firefly Firefly
|
||||
focaltech FocalTech Systems Co.,Ltd
|
||||
friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd
|
||||
|
|
@ -400,6 +401,7 @@ tcl Toby Churchill Ltd.
|
|||
technexion TechNexion
|
||||
technologic Technologic Systems
|
||||
tempo Tempo Semiconductor
|
||||
techstar Shenzhen Techstar Electronics Co., Ltd.
|
||||
terasic Terasic Inc.
|
||||
thine THine Electronics, Inc.
|
||||
ti Texas Instruments
|
||||
|
|
|
|||
|
|
@ -1093,6 +1093,13 @@ static struct device *s5p_mfc_alloc_memdev(struct device *dev,
|
|||
child->dma_mask = dev->dma_mask;
|
||||
child->release = s5p_mfc_memdev_release;
|
||||
|
||||
/*
|
||||
* The memdevs are not proper OF platform devices, so in order for them
|
||||
* to be treated as valid DMA masters we need a bit of a hack to force
|
||||
* them to inherit the MFC node's DMA configuration.
|
||||
*/
|
||||
of_dma_configure(child, dev->of_node, true);
|
||||
|
||||
if (device_add(child) == 0) {
|
||||
ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
|
||||
idx);
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS];
|
||||
static int reserved_mem_count;
|
||||
|
||||
int __init __weak early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
|
||||
static int __init early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
|
||||
phys_addr_t align, phys_addr_t start, phys_addr_t end, bool nomap,
|
||||
phys_addr_t *res_base)
|
||||
{
|
||||
|
|
@ -340,10 +340,6 @@ int of_reserved_mem_device_init_by_idx(struct device *dev,
|
|||
mutex_lock(&of_rmem_assigned_device_mutex);
|
||||
list_add(&rd->list, &of_rmem_assigned_device_list);
|
||||
mutex_unlock(&of_rmem_assigned_device_mutex);
|
||||
/* ensure that dma_ops is set for virtual devices
|
||||
* using reserved memory
|
||||
*/
|
||||
of_dma_configure(dev, np, true);
|
||||
|
||||
dev_info(dev, "assigned reserved memory node %s\n", rmem->name);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -1116,15 +1116,22 @@ static void update_node_properties(struct device_node *np,
|
|||
for (prop = np->properties; prop != NULL; prop = save_next) {
|
||||
save_next = prop->next;
|
||||
ret = of_add_property(dup, prop);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
if (ret == -EEXIST && !strcmp(prop->name, "name"))
|
||||
continue;
|
||||
pr_err("unittest internal error: unable to add testdata property %pOF/%s",
|
||||
np, prop->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* attach_node_and_children - attaches nodes
|
||||
* and its children to live tree
|
||||
* and its children to live tree.
|
||||
* CAUTION: misleading function name - if node @np already exists in
|
||||
* the live tree then children of @np are *not* attached to the live
|
||||
* tree. This works for the current test devicetree nodes because such
|
||||
* nodes do not have child nodes.
|
||||
*
|
||||
* @np: Node to attach to live tree
|
||||
*/
|
||||
|
|
@ -2514,6 +2521,10 @@ static int __init of_unittest(void)
|
|||
int res;
|
||||
|
||||
/* adding data for unittest */
|
||||
|
||||
if (IS_ENABLED(CONFIG_UML))
|
||||
unittest_unflatten_overlay_base();
|
||||
|
||||
res = unittest_data_add();
|
||||
if (res)
|
||||
return res;
|
||||
|
|
|
|||
|
|
@ -35,13 +35,6 @@ int of_reserved_mem_device_init_by_idx(struct device *dev,
|
|||
struct device_node *np, int idx);
|
||||
void of_reserved_mem_device_release(struct device *dev);
|
||||
|
||||
int early_init_dt_alloc_reserved_memory_arch(phys_addr_t size,
|
||||
phys_addr_t align,
|
||||
phys_addr_t start,
|
||||
phys_addr_t end,
|
||||
bool nomap,
|
||||
phys_addr_t *res_base);
|
||||
|
||||
void fdt_init_reserved_mem(void);
|
||||
void fdt_reserved_mem_save_node(unsigned long node, const char *uname,
|
||||
phys_addr_t base, phys_addr_t size);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ Usage:
|
|||
diff DTx_1 and DTx_2
|
||||
|
||||
|
||||
--annotate synonym for -T
|
||||
-f print full dts in diff (--unified=99999)
|
||||
-h synonym for --help
|
||||
-help synonym for --help
|
||||
|
|
@ -28,6 +29,7 @@ Usage:
|
|||
-s SRCTREE linux kernel source tree is at path SRCTREE
|
||||
(default is current directory)
|
||||
-S linux kernel source tree is at root of current git repo
|
||||
-T Annotate output .dts with input source file and line (-T -T for more details)
|
||||
-u unsorted, do not sort DTx
|
||||
|
||||
|
||||
|
|
@ -174,6 +176,7 @@ compile_to_dts() {
|
|||
|
||||
# ----- start of script
|
||||
|
||||
annotate=""
|
||||
cmd_diff=0
|
||||
diff_flags="-u"
|
||||
dtx_file_1=""
|
||||
|
|
@ -208,6 +211,14 @@ while [ $# -gt 0 ] ; do
|
|||
shift
|
||||
;;
|
||||
|
||||
-T | --annotate )
|
||||
if [ "${annotate}" = "" ] ; then
|
||||
annotate="-T"
|
||||
elif [ "${annotate}" = "-T" ] ; then
|
||||
annotate="-T -T"
|
||||
fi
|
||||
shift
|
||||
;;
|
||||
-u )
|
||||
dtc_sort=""
|
||||
shift
|
||||
|
|
@ -327,7 +338,7 @@ cpp_flags="\
|
|||
DTC="\
|
||||
${DTC} \
|
||||
-i ${srctree}/scripts/dtc/include-prefixes \
|
||||
-O dts -qq -f ${dtc_sort} -o -"
|
||||
-O dts -qq -f ${dtc_sort} ${annotate} -o -"
|
||||
|
||||
|
||||
# ----- do the diff or decompile
|
||||
|
|
|
|||
Loading…
Reference in New Issue