ARM: orion5x: convert RD-88F5182 to Device Tree
This commit converts the RD-88F5182 platform to the Device Tree. All devices except the PCI are converted to the Device Tree. It is worth noting that: * The PCI description for the DT case is kept in board-rd88f5182.c. * The existing non-DT support in rd88f5182-setup.c is kept as is, in order to allow testing of a given platform in both DT and non-DT cases. It will ultimately be removed, once we no longer care about non-DT support for Orion5x. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-35-git-send-email-thomas.petazzoni@free-electrons.com Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Petazzoni
Jason Cooper
parent
aeba696478
commit
065194a06b
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@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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am43x-epos-evm.dtb \
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am437x-gp-evm.dtb \
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dra7-evm.dtb
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dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
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dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \
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orion5x-rd88f5182-nas.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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@ -0,0 +1,177 @@
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/*
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* Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "orion5x-mv88f5182.dtsi"
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/ {
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model = "Marvell Reference Design 88F5182 NAS";
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compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
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memory {
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reg = <0x00000000 0x4000000>; /* 64 MB */
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};
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chosen {
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bootargs = "console=ttyS0,115200n8 earlyprintk";
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linux,stdout-path = &uart0;
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
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<MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
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<MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
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<MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pmx_debug_led>;
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pinctrl-names = "default";
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led@0 {
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label = "rd88f5182:cpu";
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linux,default-trigger = "heartbeat";
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&devbus_bootcs {
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status = "okay";
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <90000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <186000>;
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devbus,acc-next-ps = <186000>;
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/* Write parameters */
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devbus,wr-high-ps = <90000>;
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devbus,wr-low-ps = <90000>;
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devbus,ale-wr-ps = <90000>;
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flash@0 {
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compatible = "cfi-flash";
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reg = <0 0x80000>;
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bank-width = <1>;
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};
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};
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&devbus_cs1 {
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status = "okay";
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <90000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <186000>;
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devbus,acc-next-ps = <186000>;
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/* Write parameters */
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devbus,wr-high-ps = <90000>;
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devbus,wr-low-ps = <90000>;
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devbus,ale-wr-ps = <90000>;
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flash@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <1>;
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};
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};
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&ehci0 {
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status = "okay";
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};
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&ehci1 {
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status = "okay";
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};
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ð {
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status = "okay";
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ethernet-port@0 {
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phy-handle = <ðphy>;
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};
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};
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&i2c {
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status = "okay";
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clock-frequency = <100000>;
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#address-cells = <1>;
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rtc@68 {
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pinctrl-0 = <&pmx_rtc>;
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pinctrl-names = "default";
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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};
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&mdio {
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status = "okay";
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ethphy: ethernet-phy {
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reg = <8>;
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};
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};
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&pinctrl {
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pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
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&pmx_pci_gpios>;
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pinctrl-names = "default";
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/*
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* MPP[20] PCI Clock to MV88F5182
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* MPP[21] PCI Clock to mini PCI CON11
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* MPP[22] USB 0 over current indication
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* MPP[23] USB 1 over current indication
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* MPP[24] USB 1 over current enable
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* MPP[25] USB 0 over current enable
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*/
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pmx_debug_led: pmx-debug_led {
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marvell,pins = "mpp0";
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marvell,function = "gpio";
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};
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pmx_reset_switch: pmx-reset-switch {
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marvell,pins = "mpp1";
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marvell,function = "gpio";
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};
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pmx_rtc: pmx-rtc {
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marvell,pins = "mpp3";
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marvell,function = "gpio";
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};
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pmx_misc_gpios: pmx-misc-gpios {
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marvell,pins = "mpp4", "mpp5";
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marvell,function = "gpio";
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};
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pmx_pci_gpios: pmx-pci-gpios {
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marvell,pins = "mpp6", "mpp7";
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marvell,function = "gpio";
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};
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};
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&sata {
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pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
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pinctrl-names = "default";
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status = "okay";
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nr-ports = <2>;
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};
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&uart0 {
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status = "okay";
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};
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@ -28,6 +28,14 @@ config MACH_RD88F5182
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Say 'Y' here if you want your kernel to support the
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Marvell Orion-NAS (88F5182) RD2
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config MACH_RD88F5182_DT
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bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)"
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select ARCH_ORION5X_DT
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select I2C_BOARDINFO
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help
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Say 'Y' here if you want your kernel to support the Marvell
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Orion-NAS (88F5182) RD2, Flattened Device Tree.
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config MACH_KUROBOX_PRO
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bool "KuroBox Pro"
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select I2C_BOARDINFO
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@ -23,3 +23,4 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o
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obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o
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obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o
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obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o
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@ -0,0 +1,116 @@
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/*
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* arch/arm/mach-orion5x/rd88f5182-setup.c
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*
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* Marvell Orion-NAS Reference Design Setup
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*
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* Maintainer: Ronen Shitrit <rshitrit@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/pci.h>
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#include <mach/orion5x.h>
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#include "common.h"
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/*****************************************************************************
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* RD-88F5182 Info
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****************************************************************************/
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/*
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* PCI
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*/
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#define RD88F5182_PCI_SLOT0_OFFS 7
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#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
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#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
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/*****************************************************************************
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* PCI
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****************************************************************************/
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static void __init rd88f5182_pci_preinit(void)
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{
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int pin;
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/*
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* Configure PCI GPIO IRQ pins
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*/
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pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
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if (gpio_request(pin, "PCI IntA") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
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}
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pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
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if (gpio_request(pin, "PCI IntB") == 0) {
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if (gpio_direction_input(pin) == 0) {
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to "
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"set_irq_type pin %d\n", pin);
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gpio_free(pin);
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}
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} else {
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printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
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}
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}
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static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
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u8 pin)
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{
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int irq;
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/*
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* Check for devices with hard-wired IRQs.
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*/
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irq = orion5x_pci_map_irq(dev, slot, pin);
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if (irq != -1)
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return irq;
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/*
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* PCI IRQs are connected via GPIOs
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*/
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switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
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case 0:
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if (pin == 1)
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
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else
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return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
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default:
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return -1;
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}
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}
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static struct hw_pci rd88f5182_pci __initdata = {
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.nr_controllers = 2,
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.preinit = rd88f5182_pci_preinit,
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.setup = orion5x_pci_sys_setup,
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.scan = orion5x_pci_sys_scan_bus,
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.map_irq = rd88f5182_pci_map_irq,
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};
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static int __init rd88f5182_pci_init(void)
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{
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if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
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pci_common_init(&rd88f5182_pci);
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return 0;
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}
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subsys_initcall(rd88f5182_pci_init);
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