powerpc/xics: Rearrange file to group code by function
Now that xics_update_irq_servers is called only from init and hotplug code, it becomes possible to clean up the ordering of functions in the file, grouping them but the interfaces they implement. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Milton Miller
Benjamin Herrenschmidt
parent
d13f7208b2
commit
0641cc91b0
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@ -9,7 +9,6 @@
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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@ -35,6 +34,8 @@
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#include "xics.h"
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#include "plpar_wrappers.h"
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static struct irq_host *xics_host;
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#define XICS_IPI 2
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#define XICS_IRQ_SPURIOUS 0
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@ -47,6 +48,20 @@
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*/
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#define IPI_PRIORITY 4
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static unsigned int default_server = 0xFF;
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static unsigned int default_distrib_server = 0;
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static unsigned int interrupt_server_size = 8;
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/* RTAS service tokens */
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static int ibm_get_xive;
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static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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/* Direct hardware low level accessors */
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/* The part of the interrupt presentation layer that we care about */
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struct xics_ipl {
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union {
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u32 word;
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@ -65,22 +80,6 @@ struct xics_ipl {
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static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
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static unsigned int default_server = 0xFF;
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static unsigned int default_distrib_server = 0;
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static unsigned int interrupt_server_size = 8;
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static struct irq_host *xics_host;
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/* RTAS service tokens */
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static int ibm_get_xive;
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static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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/* Direct HW low level accessors */
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static inline unsigned int direct_xirr_info_get(void)
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{
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int cpu = smp_processor_id();
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@ -110,7 +109,6 @@ static inline void direct_qirr_info(int n_cpu, u8 value)
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/* LPAR low level accessors */
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static inline unsigned int lpar_xirr_info_get(void)
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{
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unsigned long lpar_rc;
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@ -152,59 +150,9 @@ static inline void lpar_qirr_info(int n_cpu , u8 value)
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}
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/* High level handlers and init code */
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static void xics_update_irq_servers(void)
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{
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int i, j;
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struct device_node *np;
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u32 ilen;
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const u32 *ireg, *isize;
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u32 hcpuid;
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/* Find the server numbers for the boot cpu. */
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np = of_get_cpu_node(boot_cpuid, NULL);
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BUG_ON(!np);
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ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
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if (!ireg) {
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of_node_put(np);
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return;
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}
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i = ilen / sizeof(int);
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hcpuid = get_hard_smp_processor_id(boot_cpuid);
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/* Global interrupt distribution server is specified in the last
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* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
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* entry fom this property for current boot cpu id and use it as
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* default distribution server
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*/
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for (j = 0; j < i; j += 2) {
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if (ireg[j] == hcpuid) {
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default_server = hcpuid;
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default_distrib_server = ireg[j+1];
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isize = of_get_property(np,
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"ibm,interrupt-server#-size", NULL);
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if (isize)
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interrupt_server_size = *isize;
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}
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}
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of_node_put(np);
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}
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/* Interface to generic irq subsystem */
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#ifdef CONFIG_SMP
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/*
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* XICS only has a single IPI, so encode the messages per CPU
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*/
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struct xics_ipi_struct {
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unsigned long value;
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} ____cacheline_aligned;
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static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
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static int get_irq_server(unsigned int virq, unsigned int strict_check)
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{
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int server;
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@ -239,7 +187,6 @@ static int get_irq_server(unsigned int virq, unsigned int strict_check)
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}
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#endif
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static void xics_unmask_irq(unsigned int virq)
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{
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unsigned int irq;
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@ -273,6 +220,13 @@ static void xics_unmask_irq(unsigned int virq)
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}
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}
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static unsigned int xics_startup(unsigned int virq)
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{
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/* unmask it */
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xics_unmask_irq(virq);
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return 0;
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}
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static void xics_mask_real_irq(unsigned int irq)
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{
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int call_status;
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@ -309,28 +263,10 @@ static void xics_mask_irq(unsigned int virq)
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xics_mask_real_irq(irq);
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}
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static unsigned int xics_startup(unsigned int virq)
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static void xics_mask_unknown_vec(unsigned int vec)
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{
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/* unmask it */
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xics_unmask_irq(virq);
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return 0;
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}
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static void xics_eoi_direct(unsigned int virq)
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{
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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direct_xirr_info_set((0xff << 24) | irq);
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}
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static void xics_eoi_lpar(unsigned int virq)
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{
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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lpar_xirr_info_set((0xff << 24) | irq);
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printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
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xics_mask_real_irq(vec);
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}
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static inline unsigned int xics_xirr_vector(unsigned int xirr)
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@ -342,12 +278,6 @@ static inline unsigned int xics_xirr_vector(unsigned int xirr)
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return xirr & 0x00ffffff;
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}
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static void xics_mask_unknown_vec(unsigned int vec)
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{
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printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
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xics_mask_real_irq(vec);
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}
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static unsigned int xics_get_irq_direct(void)
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{
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unsigned int xirr = direct_xirr_info_get();
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@ -390,91 +320,20 @@ static unsigned int xics_get_irq_lpar(void)
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return NO_IRQ;
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}
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#ifdef CONFIG_SMP
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static irqreturn_t xics_ipi_dispatch(int cpu)
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static void xics_eoi_direct(unsigned int virq)
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{
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WARN_ON(cpu_is_offline(cpu));
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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while (xics_ipi_message[cpu].value) {
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if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNCTION);
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}
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if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_RESCHEDULE);
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}
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if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
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}
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
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}
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#endif
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}
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return IRQ_HANDLED;
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}
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static inline void smp_xics_do_message(int cpu, int msg)
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{
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set_bit(msg, &xics_ipi_message[cpu].value);
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mb();
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_qirr_info(cpu, IPI_PRIORITY);
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else
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direct_qirr_info(cpu, IPI_PRIORITY);
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}
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void smp_xics_message_pass(int target, int msg)
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{
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unsigned int i;
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if (target < NR_CPUS) {
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smp_xics_do_message(target, msg);
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} else {
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for_each_online_cpu(i) {
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if (target == MSG_ALL_BUT_SELF
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&& i == smp_processor_id())
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continue;
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smp_xics_do_message(i, msg);
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}
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}
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}
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static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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direct_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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lpar_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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#endif /* CONFIG_SMP */
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static void xics_set_cpu_priority(unsigned char cppr)
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{
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_cppr_info(cppr);
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else
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direct_cppr_info(cppr);
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iosync();
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direct_xirr_info_set((0xff << 24) | irq);
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}
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static void xics_eoi_lpar(unsigned int virq)
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{
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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lpar_xirr_info_set((0xff << 24) | irq);
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}
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static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
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@ -519,22 +378,6 @@ static void xics_set_affinity(unsigned int virq, cpumask_t cpumask)
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}
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}
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void xics_setup_cpu(void)
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{
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xics_set_cpu_priority(0xff);
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/*
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* Put the calling processor into the GIQ. This is really only
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* necessary from a secondary thread as the OF start-cpu interface
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* performs this function for us on primary threads.
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*
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* XXX: undo of teardown on kexec needs this too, as may hotplug
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*/
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rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
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(1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
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}
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static struct irq_chip xics_pic_direct = {
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.typename = " XICS ",
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.startup = xics_startup,
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@ -544,7 +387,6 @@ static struct irq_chip xics_pic_direct = {
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.set_affinity = xics_set_affinity
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};
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static struct irq_chip xics_pic_lpar = {
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.typename = " XICS ",
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.startup = xics_startup,
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@ -554,6 +396,9 @@ static struct irq_chip xics_pic_lpar = {
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.set_affinity = xics_set_affinity
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};
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/* Interface to arch irq controller subsystem layer */
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/* Points to the irq_chip we're actually using */
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static struct irq_chip *xics_irq_chip;
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@ -613,6 +458,169 @@ static void __init xics_init_host(void)
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irq_set_default_host(xics_host);
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}
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/* Inter-processor interrupt support */
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#ifdef CONFIG_SMP
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/*
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* XICS only has a single IPI, so encode the messages per CPU
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*/
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struct xics_ipi_struct {
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unsigned long value;
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} ____cacheline_aligned;
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static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
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static inline void smp_xics_do_message(int cpu, int msg)
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{
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set_bit(msg, &xics_ipi_message[cpu].value);
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mb();
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if (firmware_has_feature(FW_FEATURE_LPAR))
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lpar_qirr_info(cpu, IPI_PRIORITY);
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else
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direct_qirr_info(cpu, IPI_PRIORITY);
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}
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void smp_xics_message_pass(int target, int msg)
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{
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unsigned int i;
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if (target < NR_CPUS) {
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smp_xics_do_message(target, msg);
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} else {
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for_each_online_cpu(i) {
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if (target == MSG_ALL_BUT_SELF
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&& i == smp_processor_id())
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continue;
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smp_xics_do_message(i, msg);
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}
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}
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}
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static irqreturn_t xics_ipi_dispatch(int cpu)
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{
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WARN_ON(cpu_is_offline(cpu));
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while (xics_ipi_message[cpu].value) {
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if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNCTION);
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}
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if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_RESCHEDULE);
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}
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if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
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}
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
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&xics_ipi_message[cpu].value)) {
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mb();
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smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
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}
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#endif
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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direct_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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lpar_qirr_info(cpu, 0xff);
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return xics_ipi_dispatch(cpu);
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}
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static void xics_request_ipi(void)
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{
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unsigned int ipi;
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int rc;
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ipi = irq_create_mapping(xics_host, XICS_IPI);
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BUG_ON(ipi == NO_IRQ);
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/*
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* IPIs are marked IRQF_DISABLED as they must run with irqs
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* disabled
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*/
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set_irq_handler(ipi, handle_percpu_irq);
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if (firmware_has_feature(FW_FEATURE_LPAR))
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rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
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"IPI", NULL);
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else
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rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
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"IPI", NULL);
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BUG_ON(rc);
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}
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int __init smp_xics_probe(void)
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{
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xics_request_ipi();
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return cpus_weight(cpu_possible_map);
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}
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#endif /* CONFIG_SMP */
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/* Initialization */
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static void xics_update_irq_servers(void)
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{
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int i, j;
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struct device_node *np;
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u32 ilen;
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const u32 *ireg, *isize;
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u32 hcpuid;
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/* Find the server numbers for the boot cpu. */
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np = of_get_cpu_node(boot_cpuid, NULL);
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BUG_ON(!np);
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ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
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if (!ireg) {
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of_node_put(np);
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return;
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}
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i = ilen / sizeof(int);
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hcpuid = get_hard_smp_processor_id(boot_cpuid);
|
||||
|
||||
/* Global interrupt distribution server is specified in the last
|
||||
* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
|
||||
* entry fom this property for current boot cpu id and use it as
|
||||
* default distribution server
|
||||
*/
|
||||
for (j = 0; j < i; j += 2) {
|
||||
if (ireg[j] == hcpuid) {
|
||||
default_server = hcpuid;
|
||||
default_distrib_server = ireg[j+1];
|
||||
|
||||
isize = of_get_property(np,
|
||||
"ibm,interrupt-server#-size", NULL);
|
||||
if (isize)
|
||||
interrupt_server_size = *isize;
|
||||
}
|
||||
}
|
||||
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
|
||||
unsigned long size)
|
||||
{
|
||||
|
|
@ -716,39 +724,33 @@ void __init xics_init_IRQ(void)
|
|||
ppc64_boot_msg(0x21, "XICS Done");
|
||||
}
|
||||
|
||||
/* Cpu startup, shutdown, and hotplug */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void xics_request_ipi(void)
|
||||
static void xics_set_cpu_priority(unsigned char cppr)
|
||||
{
|
||||
unsigned int ipi;
|
||||
int rc;
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR))
|
||||
lpar_cppr_info(cppr);
|
||||
else
|
||||
direct_cppr_info(cppr);
|
||||
iosync();
|
||||
}
|
||||
|
||||
ipi = irq_create_mapping(xics_host, XICS_IPI);
|
||||
BUG_ON(ipi == NO_IRQ);
|
||||
|
||||
void xics_setup_cpu(void)
|
||||
{
|
||||
xics_set_cpu_priority(0xff);
|
||||
|
||||
/*
|
||||
* IPIs are marked IRQF_DISABLED as they must run with irqs
|
||||
* disabled
|
||||
* Put the calling processor into the GIQ. This is really only
|
||||
* necessary from a secondary thread as the OF start-cpu interface
|
||||
* performs this function for us on primary threads.
|
||||
*
|
||||
* XXX: undo of teardown on kexec needs this too, as may hotplug
|
||||
*/
|
||||
set_irq_handler(ipi, handle_percpu_irq);
|
||||
if (firmware_has_feature(FW_FEATURE_LPAR))
|
||||
rc = request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED,
|
||||
"IPI", NULL);
|
||||
else
|
||||
rc = request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED,
|
||||
"IPI", NULL);
|
||||
BUG_ON(rc);
|
||||
rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE,
|
||||
(1UL << interrupt_server_size) - 1 - default_distrib_server, 1);
|
||||
}
|
||||
|
||||
int __init smp_xics_probe(void)
|
||||
{
|
||||
xics_request_ipi();
|
||||
|
||||
return cpus_weight(cpu_possible_map);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
void xics_teardown_cpu(void)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
|
|
|||
Loading…
Reference in New Issue