[SCSI] aic7xxx: update *_shipped files
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Hannes Reinecke <hare@suse.de> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
This commit is contained in:
Denys Vlasenko
James Bottomley
parent
7b61ab89f9
commit
060ae855a8
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -26,20 +26,6 @@ ahc_reg_print_t ahc_sxfrctl0_print;
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ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_sxfrctl1_print;
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#else
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#define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsisigo_print;
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#else
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#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsisigi_print;
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#else
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@ -54,55 +40,6 @@ ahc_reg_print_t ahc_scsirate_print;
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ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsiid_print;
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#else
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#define ahc_scsiid_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsidatl_print;
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#else
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#define ahc_scsidatl_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsidath_print;
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#else
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#define ahc_scsidath_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_stcnt_print;
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#else
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#define ahc_stcnt_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_optionmode_print;
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#else
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#define ahc_optionmode_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_targcrccnt_print;
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#else
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#define ahc_targcrccnt_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_clrsint0_print;
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#else
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#define ahc_clrsint0_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_sstat0_print;
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#else
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@ -110,13 +47,6 @@ ahc_reg_print_t ahc_sstat0_print;
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ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_clrsint1_print;
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#else
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#define ahc_clrsint1_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_sstat1_print;
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#else
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@ -138,13 +68,6 @@ ahc_reg_print_t ahc_sstat3_print;
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ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsiid_ultra2_print;
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#else
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#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_simode0_print;
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#else
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@ -166,76 +89,6 @@ ahc_reg_print_t ahc_scsibusl_print;
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ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsibush_print;
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#else
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#define ahc_scsibush_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_sxfrctl2_print;
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#else
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#define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_shaddr_print;
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#else
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#define ahc_shaddr_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_seltimer_print;
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#else
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#define ahc_seltimer_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_selid_print;
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#else
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#define ahc_selid_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scamctl_print;
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#else
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#define ahc_scamctl_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_targid_print;
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#else
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#define ahc_targid_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_spiocap_print;
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#else
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#define ahc_spiocap_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_brdctl_print;
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#else
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#define ahc_brdctl_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_seectl_print;
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#else
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#define ahc_seectl_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_sblkctl_print;
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#else
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@ -243,62 +96,6 @@ ahc_reg_print_t ahc_sblkctl_print;
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ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_busy_targets_print;
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#else
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#define ahc_busy_targets_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_ultra_enb_print;
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#else
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#define ahc_ultra_enb_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_disc_dsb_print;
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#else
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#define ahc_disc_dsb_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_cmdsize_table_tail_print;
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#else
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#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_mwi_residual_print;
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#else
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#define ahc_mwi_residual_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_next_queued_scb_print;
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#else
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#define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_msg_out_print;
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#else
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#define ahc_msg_out_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_dmaparams_print;
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#else
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#define ahc_dmaparams_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_seq_flags_print;
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#else
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@ -306,20 +103,6 @@ ahc_reg_print_t ahc_seq_flags_print;
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ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_saved_scsiid_print;
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#else
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#define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_saved_lun_print;
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#else
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#define ahc_saved_lun_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_lastphase_print;
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#else
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@ -327,153 +110,6 @@ ahc_reg_print_t ahc_lastphase_print;
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ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_waiting_scbh_print;
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#else
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#define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_disconnected_scbh_print;
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#else
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#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_free_scbh_print;
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#else
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#define ahc_free_scbh_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_complete_scbh_print;
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#else
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#define ahc_complete_scbh_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_hscb_addr_print;
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#else
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#define ahc_hscb_addr_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_shared_data_addr_print;
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#else
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#define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_kernel_qinpos_print;
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#else
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#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_qinpos_print;
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#else
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#define ahc_qinpos_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_qoutpos_print;
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#else
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#define ahc_qoutpos_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_kernel_tqinpos_print;
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#else
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#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_tqinpos_print;
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#else
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#define ahc_tqinpos_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_arg_1_print;
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#else
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#define ahc_arg_1_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_arg_2_print;
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#else
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#define ahc_arg_2_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_last_msg_print;
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#else
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#define ahc_last_msg_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_scsiseq_template_print;
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#else
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#define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \
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ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap)
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#endif
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#if AIC_DEBUG_REGISTERS
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ahc_reg_print_t ahc_ha_274_biosglobal_print;
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#else
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#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seq_flags2_print;
|
||||
#else
|
||||
#define ahc_seq_flags2_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scsiconf_print;
|
||||
#else
|
||||
#define ahc_scsiconf_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_intdef_print;
|
||||
#else
|
||||
#define ahc_intdef_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_hostconf_print;
|
||||
#else
|
||||
#define ahc_hostconf_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ha_274_biosctrl_print;
|
||||
#else
|
||||
#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seqctl_print;
|
||||
#else
|
||||
|
|
@ -481,111 +117,6 @@ ahc_reg_print_t ahc_seqctl_print;
|
|||
ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seqram_print;
|
||||
#else
|
||||
#define ahc_seqram_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seqaddr0_print;
|
||||
#else
|
||||
#define ahc_seqaddr0_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seqaddr1_print;
|
||||
#else
|
||||
#define ahc_seqaddr1_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_accum_print;
|
||||
#else
|
||||
#define ahc_accum_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sindex_print;
|
||||
#else
|
||||
#define ahc_sindex_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dindex_print;
|
||||
#else
|
||||
#define ahc_dindex_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_allones_print;
|
||||
#else
|
||||
#define ahc_allones_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_allzeros_print;
|
||||
#else
|
||||
#define ahc_allzeros_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_none_print;
|
||||
#else
|
||||
#define ahc_none_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_flags_print;
|
||||
#else
|
||||
#define ahc_flags_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sindir_print;
|
||||
#else
|
||||
#define ahc_sindir_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dindir_print;
|
||||
#else
|
||||
#define ahc_dindir_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_function1_print;
|
||||
#else
|
||||
#define ahc_function1_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_stack_print;
|
||||
#else
|
||||
#define ahc_stack_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_targ_offset_print;
|
||||
#else
|
||||
#define ahc_targ_offset_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sram_base_print;
|
||||
#else
|
||||
|
|
@ -593,97 +124,6 @@ ahc_reg_print_t ahc_sram_base_print;
|
|||
ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_bctl_print;
|
||||
#else
|
||||
#define ahc_bctl_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dscommand0_print;
|
||||
#else
|
||||
#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_bustime_print;
|
||||
#else
|
||||
#define ahc_bustime_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dscommand1_print;
|
||||
#else
|
||||
#define ahc_dscommand1_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_busspd_print;
|
||||
#else
|
||||
#define ahc_busspd_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_hs_mailbox_print;
|
||||
#else
|
||||
#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dspcistatus_print;
|
||||
#else
|
||||
#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_hcntrl_print;
|
||||
#else
|
||||
#define ahc_hcntrl_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_haddr_print;
|
||||
#else
|
||||
#define ahc_haddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_hcnt_print;
|
||||
#else
|
||||
#define ahc_hcnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scbptr_print;
|
||||
#else
|
||||
#define ahc_scbptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_intstat_print;
|
||||
#else
|
||||
#define ahc_intstat_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_clrint_print;
|
||||
#else
|
||||
#define ahc_clrint_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_error_print;
|
||||
#else
|
||||
|
|
@ -705,69 +145,6 @@ ahc_reg_print_t ahc_dfstatus_print;
|
|||
ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dfwaddr_print;
|
||||
#else
|
||||
#define ahc_dfwaddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dfraddr_print;
|
||||
#else
|
||||
#define ahc_dfraddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dfdat_print;
|
||||
#else
|
||||
#define ahc_dfdat_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scbcnt_print;
|
||||
#else
|
||||
#define ahc_scbcnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_qinfifo_print;
|
||||
#else
|
||||
#define ahc_qinfifo_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_qincnt_print;
|
||||
#else
|
||||
#define ahc_qincnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_qoutfifo_print;
|
||||
#else
|
||||
#define ahc_qoutfifo_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_crccontrol1_print;
|
||||
#else
|
||||
#define ahc_crccontrol1_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_qoutcnt_print;
|
||||
#else
|
||||
#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scsiphase_print;
|
||||
#else
|
||||
|
|
@ -775,13 +152,6 @@ ahc_reg_print_t ahc_scsiphase_print;
|
|||
ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sfunct_print;
|
||||
#else
|
||||
#define ahc_sfunct_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_base_print;
|
||||
#else
|
||||
|
|
@ -789,69 +159,6 @@ ahc_reg_print_t ahc_scb_base_print;
|
|||
ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_cdb_ptr_print;
|
||||
#else
|
||||
#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_residual_sgptr_print;
|
||||
#else
|
||||
#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_scsi_status_print;
|
||||
#else
|
||||
#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_target_phases_print;
|
||||
#else
|
||||
#define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_target_data_dir_print;
|
||||
#else
|
||||
#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_target_itag_print;
|
||||
#else
|
||||
#define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_dataptr_print;
|
||||
#else
|
||||
#define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_datacnt_print;
|
||||
#else
|
||||
#define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_sgptr_print;
|
||||
#else
|
||||
#define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_control_print;
|
||||
#else
|
||||
|
|
@ -880,188 +187,6 @@ ahc_reg_print_t ahc_scb_tag_print;
|
|||
ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_cdb_len_print;
|
||||
#else
|
||||
#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_scsirate_print;
|
||||
#else
|
||||
#define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_scsioffset_print;
|
||||
#else
|
||||
#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_next_print;
|
||||
#else
|
||||
#define ahc_scb_next_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_64_spare_print;
|
||||
#else
|
||||
#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_seectl_2840_print;
|
||||
#else
|
||||
#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_status_2840_print;
|
||||
#else
|
||||
#define ahc_status_2840_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scb_64_btt_print;
|
||||
#else
|
||||
#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_cchaddr_print;
|
||||
#else
|
||||
#define ahc_cchaddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_cchcnt_print;
|
||||
#else
|
||||
#define ahc_cchcnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccsgram_print;
|
||||
#else
|
||||
#define ahc_ccsgram_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccsgaddr_print;
|
||||
#else
|
||||
#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccsgctl_print;
|
||||
#else
|
||||
#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccscbram_print;
|
||||
#else
|
||||
#define ahc_ccscbram_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccscbaddr_print;
|
||||
#else
|
||||
#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccscbctl_print;
|
||||
#else
|
||||
#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccscbcnt_print;
|
||||
#else
|
||||
#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_scbbaddr_print;
|
||||
#else
|
||||
#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_ccscbptr_print;
|
||||
#else
|
||||
#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_hnscb_qoff_print;
|
||||
#else
|
||||
#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_snscb_qoff_print;
|
||||
#else
|
||||
#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sdscb_qoff_print;
|
||||
#else
|
||||
#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_qoff_ctlsta_print;
|
||||
#else
|
||||
#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_dff_thrsh_print;
|
||||
#else
|
||||
#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sg_cache_shadow_print;
|
||||
#else
|
||||
#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
#if AIC_DEBUG_REGISTERS
|
||||
ahc_reg_print_t ahc_sg_cache_pre_print;
|
||||
#else
|
||||
#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
|
||||
ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
|
||||
#endif
|
||||
|
||||
|
||||
#define SCSISEQ 0x00
|
||||
#define TEMODE 0x80
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in New Issue