MN10300: Don't hard code the cacheline size in register defs
Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
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@ -43,14 +43,18 @@
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/* instruction cache access registers */
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/* instruction cache access registers */
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#define ICACHE_DATA(WAY, ENTRY, OFF) \
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#define ICACHE_DATA(WAY, ENTRY, OFF) \
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__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
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__SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \
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(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
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#define ICACHE_TAG(WAY, ENTRY) \
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#define ICACHE_TAG(WAY, ENTRY) \
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__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
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__SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \
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(ENTRY) * L1_CACHE_BYTES, u32)
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/* instruction cache access registers */
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/* data cache access registers */
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#define DCACHE_DATA(WAY, ENTRY, OFF) \
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#define DCACHE_DATA(WAY, ENTRY, OFF) \
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__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
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__SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \
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(ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
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#define DCACHE_TAG(WAY, ENTRY) \
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#define DCACHE_TAG(WAY, ENTRY) \
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__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
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__SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \
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(ENTRY) * L1_CACHE_BYTES, u32)
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#endif /* _ASM_CACHE_H */
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#endif /* _ASM_CACHE_H */
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