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MIPS: barrier: Clean up __smp_mb() definition 

We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.

Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
This commit is contained in:
Paul Burton 2019-10-01 21:53:10 +00:00
parent 21e3134b3e
commit 05e6da742b
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GPG Key ID: 3EA79FACB57500DD
1 changed files with 4 additions and 8 deletions
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12
arch/mips/include/asm/barrier.h
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@ -89,17 +89,13 @@ static inline void wmb(void)
#endif /* !CONFIG_CPU_HAS_WB */ #endif /* !CONFIG_CPU_HAS_WB */
#if defined(CONFIG_WEAK_ORDERING) #if defined(CONFIG_WEAK_ORDERING)
# ifdef CONFIG_CPU_CAVIUM_OCTEON # define __smp_mb() __sync()
# define __smp_mb() __sync()
# else
# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
# endif
# define __smp_rmb() rmb() # define __smp_rmb() rmb()
# define __smp_wmb() wmb() # define __smp_wmb() wmb()
#else #else
#define __smp_mb() barrier() # define __smp_mb() barrier()
#define __smp_rmb() barrier() # define __smp_rmb() barrier()
#define __smp_wmb() barrier() # define __smp_wmb() barrier()
#endif #endif
/* /*