Allwinner clock fixes for 5.0
Two fixes for clock indices, one for the A31 and one for the V3s. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXF1dVQAKCRDj7w1vZxhR xVl+AP42Ias43QHjEqkqj9UTHHphKzQH7xbfwPKLROHasPzW3gD8Cm18jB/Flj8e po4ZFsDjVwK6I357W47NII7LvtPsegw= =YqAf -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull Allwinner clock fixes from Maxime Ripard: Two fixes for clock indices, one for the A31 and one for the V3s. * tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi: A31: Fix wrong AHB gate number clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
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@ -264,9 +264,9 @@ static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
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static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
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0x060, BIT(10), 0);
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static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
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0x060, BIT(12), 0);
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0x060, BIT(11), 0);
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static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
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0x060, BIT(13), 0);
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0x060, BIT(12), 0);
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static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
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0x060, BIT(13), 0);
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static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
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@ -542,7 +542,7 @@ static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
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[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
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[RST_BUS_VE] = { 0x2c4, BIT(0) },
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[RST_BUS_TCON0] = { 0x2c4, BIT(3) },
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[RST_BUS_TCON0] = { 0x2c4, BIT(4) },
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[RST_BUS_CSI] = { 0x2c4, BIT(8) },
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[RST_BUS_DE] = { 0x2c4, BIT(12) },
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[RST_BUS_DBG] = { 0x2c4, BIT(31) },
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