ARM: sun8i: a83t: Add USB PHY and host device nodes
The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is the host controller for HSIC. OTG is not added yet. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -242,6 +242,68 @@
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#size-cells = <0>;
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};
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usbphy: phy@1c19400 {
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compatible = "allwinner,sun8i-a83t-usb-phy";
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reg = <0x01c19400 0x10>,
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<0x01c1a800 0x14>,
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<0x01c1b800 0x14>;
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reg-names = "phy_ctrl",
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"pmu1",
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"pmu2";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>,
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<&ccu CLK_USB_HSIC>,
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<&ccu CLK_USB_HSIC_12M>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"usb2_phy",
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"usb2_hsic_12M";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>,
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<&ccu RST_USB_HSIC>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@1c1a000 {
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compatible = "allwinner,sun8i-a83t-ehci",
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"generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI0>;
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resets = <&ccu RST_BUS_EHCI0>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci0: usb@1c1a400 {
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compatible = "allwinner,sun8i-a83t-ohci",
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"generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci1: usb@1c1b000 {
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compatible = "allwinner,sun8i-a83t-ehci",
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"generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI1>;
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resets = <&ccu RST_BUS_EHCI1>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-a83t-ccu";
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reg = <0x01c20000 0x400>;
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