dt-bindings: net: sun8i-emac: Convert the binding to a schemas
Switch our Allwinner H3 EMAC controller binding to a YAML schema to enable the DT validation. Since that controller is based on a Synopsys IP, let's add the validation to that schemas with a bunch of conditionals. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Maxime Ripard
Rob Herring
parent
4b859450fa
commit
0569929d97
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-gmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A83t EMAC Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <maxime.ripard@bootlin.com>
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properties:
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compatible:
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oneOf:
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- const: allwinner,sun8i-a83t-emac
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- const: allwinner,sun8i-h3-emac
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- const: allwinner,sun8i-r40-emac
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- const: allwinner,sun8i-v3s-emac
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- const: allwinner,sun50i-a64-emac
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- items:
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- const: allwinner,sun50i-h6-emac
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- const: allwinner,sun50i-a64-emac
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-names:
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const: macirq
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clocks:
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maxItems: 1
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clock-names:
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const: stmmaceth
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syscon:
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$ref: /schemas/types.yaml#definitions/phandle
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description:
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Phandle to the device containing the EMAC or GMAC clock
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register
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- phy-connection-type
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- phy-handle
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- syscon
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allOf:
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- $ref: "snps,dwmac.yaml#"
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-a83t-emac
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- allwinner,sun8i-h3-emac
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- allwinner,sun8i-v3s-emac
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- allwinner,sun50i-a64-emac
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then:
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properties:
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allwinner,tx-delay-ps:
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default: 0
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minimum: 0
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maximum: 700
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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allwinner,rx-delay-ps:
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default: 0
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minimum: 0
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maximum: 3100
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-r40-emac
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then:
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properties:
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allwinner,rx-delay-ps:
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default: 0
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minimum: 0
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maximum: 700
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multipleOf: 100
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description:
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External RGMII PHY TX clock delay chain value in ps.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-h3-emac
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- allwinner,sun8i-v3s-emac
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then:
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properties:
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allwinner,leds-active-low:
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$ref: /schemas/types.yaml#definitions/flag
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description:
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EPHY LEDs are active low.
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mdio-mux:
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type: object
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properties:
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compatible:
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const: allwinner,sun8i-h3-mdio-mux
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mdio-parent-bus:
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$ref: /schemas/types.yaml#definitions/phandle
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description:
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Phandle to EMAC MDIO.
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mdio@1:
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type: object
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description: Internal MDIO Bus
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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compatible:
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const: allwinner,sun8i-h3-mdio-internal
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reg:
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const: 1
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patternProperties:
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"^ethernet-phy@[0-9a-f]$":
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type: object
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description:
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Integrated PHY node
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properties:
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- clocks
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- resets
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mdio@2:
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type: object
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description: External MDIO Bus (H3 only)
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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const: 2
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required:
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- compatible
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- mdio-parent-bus
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- mdio@1
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examples:
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 12>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&int_mii_phy>;
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phy-connection-type = "mii";
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allwinner,leds-active-low;
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio1>;
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int_mii_phy: mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu 67>;
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resets = <&ccu 39>;
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phy-is-integrated;
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};
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};
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 12>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy>;
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phy-connection-type = "rgmii";
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allwinner,leds-active-low;
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mdio2: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio2>;
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mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu 67>;
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resets = <&ccu 39>;
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};
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};
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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};
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- |
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ethernet@1c0b000 {
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compatible = "allwinner,sun8i-a83t-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <0 82 1>;
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interrupt-names = "macirq";
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resets = <&ccu 13>;
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reset-names = "stmmaceth";
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clocks = <&ccu 27>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy1>;
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phy-connection-type = "rgmii";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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# FIXME: We should set it, but it would report all the generic
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# properties as additional properties.
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# additionalProperties: false
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...
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@ -1,201 +0,0 @@
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* Allwinner sun8i GMAC ethernet controller
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This device is a platform glue layer for stmmac.
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Please see stmmac.txt for the other unchanged properties.
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Required properties:
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- compatible: must be one of the following string:
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"allwinner,sun8i-a83t-emac"
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"allwinner,sun8i-h3-emac"
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"allwinner,sun8i-r40-gmac"
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"allwinner,sun8i-v3s-emac"
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"allwinner,sun50i-a64-emac"
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"allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac"
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- reg: address and length of the register for the device.
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- interrupts: interrupt for the device
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- interrupt-names: must be "macirq"
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- clocks: A phandle to the reference clock for this device
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- clock-names: must be "stmmaceth"
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- resets: A phandle to the reset control for this device
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- reset-names: must be "stmmaceth"
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- phy-mode: See ethernet.txt
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- phy-handle: See ethernet.txt
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- syscon: A phandle to the device containing the EMAC or GMAC clock register
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Optional properties:
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- allwinner,tx-delay-ps: TX clock delay chain value in ps.
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Range is 0-700. Default is 0.
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Unavailable for allwinner,sun8i-r40-gmac
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- allwinner,rx-delay-ps: RX clock delay chain value in ps.
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Range is 0-3100. Default is 0.
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Range is 0-700 for allwinner,sun8i-r40-gmac
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Both delay properties need to be a multiple of 100. They control the
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clock delay for external RGMII PHY. They do not apply to the internal
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PHY or external non-RGMII PHYs.
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Optional properties for the following compatibles:
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- "allwinner,sun8i-h3-emac",
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- "allwinner,sun8i-v3s-emac":
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- allwinner,leds-active-low: EPHY LEDs are active low
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Required child node of emac:
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- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
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Required properties of the mdio node:
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- #address-cells: shall be 1
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- #size-cells: shall be 0
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The device node referenced by "phy" or "phy-handle" must be a child node
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of the mdio node. See phy.txt for the generic PHY bindings.
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The following compatibles require that the emac node have a mdio-mux child
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node called "mdio-mux":
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- "allwinner,sun8i-h3-emac"
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- "allwinner,sun8i-v3s-emac":
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Required properties for the mdio-mux node:
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- compatible = "allwinner,sun8i-h3-mdio-mux"
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- mdio-parent-bus: a phandle to EMAC mdio
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- one child mdio for the integrated mdio with the compatible
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"allwinner,sun8i-h3-mdio-internal"
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- one child mdio for the external mdio if present (V3s have none)
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Required properties for the mdio-mux children node:
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- reg: 1 for internal MDIO bus, 2 for external MDIO bus
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The following compatibles require a PHY node representing the integrated
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PHY, under the integrated MDIO bus node if an mdio-mux node is used:
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- "allwinner,sun8i-h3-emac",
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- "allwinner,sun8i-v3s-emac":
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Additional information regarding generic multiplexer properties can be found
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at Documentation/devicetree/bindings/net/mdio-mux.txt
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Required properties of the integrated phy node:
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- clocks: a phandle to the reference clock for the EPHY
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||||||
- resets: a phandle to the reset control for the EPHY
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- Must be a child of the integrated mdio
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Example with integrated PHY:
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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|
||||||
reset-names = "stmmaceth";
|
|
||||||
clocks = <&ccu CLK_BUS_EMAC>;
|
|
||||||
clock-names = "stmmaceth";
|
|
||||||
|
|
||||||
phy-handle = <&int_mii_phy>;
|
|
||||||
phy-mode = "mii";
|
|
||||||
allwinner,leds-active-low;
|
|
||||||
|
|
||||||
mdio: mdio {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "snps,dwmac-mdio";
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio-mux {
|
|
||||||
compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
mdio-parent-bus = <&mdio>;
|
|
||||||
|
|
||||||
int_mdio: mdio@1 {
|
|
||||||
compatible = "allwinner,sun8i-h3-mdio-internal";
|
|
||||||
reg = <1>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
int_mii_phy: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
clocks = <&ccu CLK_BUS_EPHY>;
|
|
||||||
resets = <&ccu RST_BUS_EPHY>;
|
|
||||||
phy-is-integrated;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
ext_mdio: mdio@2 {
|
|
||||||
reg = <2>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
Example with external PHY:
|
|
||||||
emac: ethernet@1c0b000 {
|
|
||||||
compatible = "allwinner,sun8i-h3-emac";
|
|
||||||
syscon = <&syscon>;
|
|
||||||
reg = <0x01c0b000 0x104>;
|
|
||||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-names = "macirq";
|
|
||||||
resets = <&ccu RST_BUS_EMAC>;
|
|
||||||
reset-names = "stmmaceth";
|
|
||||||
clocks = <&ccu CLK_BUS_EMAC>;
|
|
||||||
clock-names = "stmmaceth";
|
|
||||||
|
|
||||||
phy-handle = <&ext_rgmii_phy>;
|
|
||||||
phy-mode = "rgmii";
|
|
||||||
allwinner,leds-active-low;
|
|
||||||
|
|
||||||
mdio: mdio {
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
compatible = "snps,dwmac-mdio";
|
|
||||||
};
|
|
||||||
|
|
||||||
mdio-mux {
|
|
||||||
compatible = "allwinner,sun8i-h3-mdio-mux";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
|
|
||||||
mdio-parent-bus = <&mdio>;
|
|
||||||
|
|
||||||
int_mdio: mdio@1 {
|
|
||||||
compatible = "allwinner,sun8i-h3-mdio-internal";
|
|
||||||
reg = <1>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
int_mii_phy: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
clocks = <&ccu CLK_BUS_EPHY>;
|
|
||||||
resets = <&ccu RST_BUS_EPHY>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
ext_mdio: mdio@2 {
|
|
||||||
reg = <2>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
ext_rgmii_phy: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
}:
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
Example with SoC without integrated PHY
|
|
||||||
|
|
||||||
emac: ethernet@1c0b000 {
|
|
||||||
compatible = "allwinner,sun8i-a83t-emac";
|
|
||||||
syscon = <&syscon>;
|
|
||||||
reg = <0x01c0b000 0x104>;
|
|
||||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
interrupt-names = "macirq";
|
|
||||||
resets = <&ccu RST_BUS_EMAC>;
|
|
||||||
reset-names = "stmmaceth";
|
|
||||||
clocks = <&ccu CLK_BUS_EMAC>;
|
|
||||||
clock-names = "stmmaceth";
|
|
||||||
|
|
||||||
phy-handle = <&ext_rgmii_phy>;
|
|
||||||
phy-mode = "rgmii";
|
|
||||||
|
|
||||||
mdio: mdio {
|
|
||||||
compatible = "snps,dwmac-mdio";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
ext_rgmii_phy: ethernet-phy@1 {
|
|
||||||
reg = <1>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
@ -45,6 +45,11 @@ properties:
|
||||||
contains:
|
contains:
|
||||||
enum:
|
enum:
|
||||||
- allwinner,sun7i-a20-gmac
|
- allwinner,sun7i-a20-gmac
|
||||||
|
- allwinner,sun8i-a83t-emac
|
||||||
|
- allwinner,sun8i-h3-emac
|
||||||
|
- allwinner,sun8i-r40-emac
|
||||||
|
- allwinner,sun8i-v3s-emac
|
||||||
|
- allwinner,sun50i-a64-emac
|
||||||
- snps,dwmac
|
- snps,dwmac
|
||||||
- snps,dwmac-3.50a
|
- snps,dwmac-3.50a
|
||||||
- snps,dwmac-3.610
|
- snps,dwmac-3.610
|
||||||
|
|
@ -267,6 +272,11 @@ allOf:
|
||||||
contains:
|
contains:
|
||||||
enum:
|
enum:
|
||||||
- allwinner,sun7i-a20-gmac
|
- allwinner,sun7i-a20-gmac
|
||||||
|
- allwinner,sun8i-a83t-emac
|
||||||
|
- allwinner,sun8i-h3-emac
|
||||||
|
- allwinner,sun8i-r40-emac
|
||||||
|
- allwinner,sun8i-v3s-emac
|
||||||
|
- allwinner,sun50i-a64-emac
|
||||||
- snps,dwxgmac
|
- snps,dwxgmac
|
||||||
- snps,dwxgmac-2.10
|
- snps,dwxgmac-2.10
|
||||||
- st,spear600-gmac
|
- st,spear600-gmac
|
||||||
|
|
@ -308,6 +318,11 @@ allOf:
|
||||||
contains:
|
contains:
|
||||||
enum:
|
enum:
|
||||||
- allwinner,sun7i-a20-gmac
|
- allwinner,sun7i-a20-gmac
|
||||||
|
- allwinner,sun8i-a83t-emac
|
||||||
|
- allwinner,sun8i-h3-emac
|
||||||
|
- allwinner,sun8i-r40-emac
|
||||||
|
- allwinner,sun8i-v3s-emac
|
||||||
|
- allwinner,sun50i-a64-emac
|
||||||
- snps,dwmac-4.00
|
- snps,dwmac-4.00
|
||||||
- snps,dwmac-4.10a
|
- snps,dwmac-4.10a
|
||||||
- snps,dwxgmac
|
- snps,dwxgmac
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue