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rtlwifi: rtl8723ae: Update driver to match 06/28/14 Realtek version 

Not only does this patch update the driver to match the latest Realtek release,
it is an important step in getting the internal code source at Realtek to match
the code in the kernel. The primary reason for this is to make it easier for
Realtek to maintain the kernel source without requiring an intermediate like me.

In this process of merging the two source repositories, there are a lot
of changes in both, and this commit is rather large.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Larry Finger 2014-09-26 16:40:24 -05:00 committed by John W. Linville
parent b1a3bfc97c
commit 0529c6b817
38 changed files with 5346 additions and 4779 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/wireless/rtlwifi/pci.c
View File

@ -952,10 +952,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
/*Shared IRQ or HW disappared */
if (!inta || inta == 0xffff) {
ret = IRQ_NONE;
if (!inta || inta == 0xffff)
goto done;
}
/*<1> beacon related */
if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {

13
drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
View File

@ -60,19 +60,6 @@ struct rtl92c_firmware_header {
__le32 rsvd5;
};
enum rtl8192c_h2c_cmd {
H2C_AP_OFFLOAD = 0,
H2C_SETPWRMODE = 1,
H2C_JOINBSSRPT = 2,
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 5,
H2C_RA_MASK = 6,
H2C_MACID_PS_MODE = 7,
H2C_P2P_PS_OFFLOAD = 8,
H2C_P2P_PS_CTW_CMD = 32,
MAX_H2CCMD
};
#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \

12
drivers/net/wireless/rtlwifi/rtl8192de/fw.h
View File

@ -132,18 +132,6 @@ struct rtl92d_firmware_header {
u32 rsvd5;
};
enum rtl8192d_h2c_cmd {
H2C_AP_OFFLOAD = 0,
H2C_SETPWRMODE = 1,
H2C_JOINBSSRPT = 2,
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 5,
H2C_RA_MASK = 6,
H2C_MAC_MODE_SEL = 9,
H2C_PWRM = 15,
MAX_H2CCMD
};
int rtl92d_download_fw(struct ieee80211_hw *hw);
void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);

1
drivers/net/wireless/rtlwifi/rtl8192se/fw.h
View File

@ -336,7 +336,6 @@ enum fw_h2c_cmd {
H2C_TMP3,
H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
H2C_TMP4,
MAX_H2CCMD /*52*/
};
/* The following macros are used for FW

7
drivers/net/wireless/rtlwifi/rtl8723ae/btc.h
View File

@ -11,10 +11,6 @@
** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
** more details.
**
** You should have received a copy of the GNU General Public License along with
** this program; if not, write to the Free Software Foundation, Inc.,
** 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
**
** The full GNU General Public License is included in this distribution in the
** file called LICENSE.
**
@ -24,8 +20,7 @@
** Hsinchu 300, Taiwan.
** Larry Finger <Larry.Finger@lwfinger.net>
**
*****************************************************************************
*/
******************************************************************************/
#ifndef __RTL8723E_BTC_H__
#define __RTL8723E_BTC_H__

195
drivers/net/wireless/rtlwifi/rtl8723ae/def.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -25,55 +21,145 @@
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#ifndef __RTL8723E_DEF_H__
#define __RTL8723E_DEF_H__
#define HAL_RETRY_LIMIT_INFRA 48
#define HAL_RETRY_LIMIT_AP_ADHOC 7
#define RESET_DELAY_8185 20
#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#define NUM_OF_FIRMWARE_QUEUE 10
#define NUM_OF_PAGES_IN_FW 0x100
#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
#define MAX_LINES_HWCONFIG_TXT 1000
#define MAX_BYTES_LINE_HWCONFIG_TXT 256
#define SW_THREE_WIRE 0
#define HW_THREE_WIRE 2
#define BT_DEMO_BOARD 0
#define BT_QA_BOARD 1
#define BT_FPGA 2
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
#define RX_MPDU_QUEUE 0
#define MAX_H2C_QUEUE_NUM 10
#define CHIP_8723 BIT(0)
#define NORMAL_CHIP BIT(3)
#define RF_TYPE_1T2R BIT(4)
#define RF_TYPE_2T2R BIT(5)
#define CHIP_VENDOR_UMC BIT(7)
#define B_CUT_VERSION BIT(12)
#define C_CUT_VERSION BIT(13)
#define D_CUT_VERSION ((BIT(12)|BIT(13)))
#define E_CUT_VERSION BIT(14)
#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
#define AC2QUEUEID(_AC) (_AC)
#define C2H_RX_CMD_HDR_LEN 8
#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
#define GET_C2H_CMD_CONTINUE(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
#define GET_C2H_CMD_CONTENT(__prxhdr) \
((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_BONDING_92C_1T2R 0x1
#define CHIP_8723 BIT(0)
#define NORMAL_CHIP BIT(3)
#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
#define RF_TYPE_1T2R BIT(4)
#define RF_TYPE_2T2R BIT(5)
#define CHIP_VENDOR_UMC BIT(7)
#define B_CUT_VERSION BIT(12)
#define C_CUT_VERSION BIT(13)
#define D_CUT_VERSION ((BIT(12)|BIT(13)))
#define E_CUT_VERSION BIT(14)
#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
/* MASK */
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
#define MANUFACTUER_MASK BIT(7)
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
#define MANUFACTUER_MASK BIT(7)
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
/* Get element */
#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
true : false)
#define IS_8723_SERIES(version) \
((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
#define IS_CHIP_VENDOR_UMC(version) \
((GET_CVID_MANUFACTUER(version)) ? true : false)
#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\
true : false)
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
true : false)
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
? true : false)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
? true : false)
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version)) ? \
true : false)
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? \
((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) \
? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \
true : false) : false)
#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
? ((GET_CVID_CUT_VERSION(version)) ? \
false : true) : false)
#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version))\
? ((GET_CVID_CUT_VERSION(version)) ? \
false : true) : false)
#define IS_VENDOR_8723A_B_CUT(version) ((IS_8723_SERIES(version))\
? ((GET_CVID_CUT_VERSION(version) == \
B_CUT_VERSION) ? true : false) : false)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\
? ((GET_CVID_CUT_VERSION(version) == \
B_CUT_VERSION) ? true : false) : false)
enum rf_optype {
RF_OP_BY_SW_3WIRE = 0,
@ -93,7 +179,7 @@ enum power_save_mode {
POWER_SAVE_MODE_SAVE,
};
enum power_polocy_config {
enum power_policy_config {
POWERCFG_MAX_POWER_SAVINGS,
POWERCFG_GLOBAL_POWER_SAVINGS,
POWERCFG_LOCAL_POWER_SAVINGS,
@ -143,6 +229,41 @@ enum rtl_desc_qsel {
QSLT_CMD = 0x13,
};
enum rtl_desc8723e_rate {
DESC92C_RATE1M = 0x00,
DESC92C_RATE2M = 0x01,
DESC92C_RATE5_5M = 0x02,
DESC92C_RATE11M = 0x03,
DESC92C_RATE6M = 0x04,
DESC92C_RATE9M = 0x05,
DESC92C_RATE12M = 0x06,
DESC92C_RATE18M = 0x07,
DESC92C_RATE24M = 0x08,
DESC92C_RATE36M = 0x09,
DESC92C_RATE48M = 0x0a,
DESC92C_RATE54M = 0x0b,
DESC92C_RATEMCS0 = 0x0c,
DESC92C_RATEMCS1 = 0x0d,
DESC92C_RATEMCS2 = 0x0e,
DESC92C_RATEMCS3 = 0x0f,
DESC92C_RATEMCS4 = 0x10,
DESC92C_RATEMCS5 = 0x11,
DESC92C_RATEMCS6 = 0x12,
DESC92C_RATEMCS7 = 0x13,
DESC92C_RATEMCS8 = 0x14,
DESC92C_RATEMCS9 = 0x15,
DESC92C_RATEMCS10 = 0x16,
DESC92C_RATEMCS11 = 0x17,
DESC92C_RATEMCS12 = 0x18,
DESC92C_RATEMCS13 = 0x19,
DESC92C_RATEMCS14 = 0x1a,
DESC92C_RATEMCS15 = 0x1b,
DESC92C_RATEMCS15_SG = 0x1c,
DESC92C_RATEMCS32 = 0x20,
};
struct phy_sts_cck_8723e_t {
u8 adc_pwdb_X[4];
u8 sq_rpt;

424
drivers/net/wireless/rtlwifi/rtl8723ae/dm.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -25,8 +21,7 @@
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#include "../wifi.h"
#include "../base.h"
@ -151,7 +146,7 @@ static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
};
static void rtl8723ae_dm_diginit(struct ieee80211_hw *hw)
static void rtl8723e_dm_diginit(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@ -176,7 +171,7 @@ static void rtl8723ae_dm_diginit(struct ieee80211_hw *hw)
dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
}
static u8 rtl_init_gain_min_pwdb(struct ieee80211_hw *hw)
static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@ -195,14 +190,15 @@ static u8 rtl_init_gain_min_pwdb(struct ieee80211_hw *hw)
} else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
} else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
} else if (dm_digtable->curmultista_cstate ==
DIG_MULTISTA_CONNECT) {
rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
}
return (u8) rssi_val_min;
}
static void rtl8723ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
{
u32 ret_value;
struct rtl_priv *rtlpriv = rtl_priv(hw);
@ -239,8 +235,7 @@ static void rtl8723ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
"cnt_parity_fail = %d, cnt_rate_illegal = %d, "
"cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
"cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
falsealm_cnt->cnt_parity_fail,
falsealm_cnt->cnt_rate_illegal,
falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
@ -263,52 +258,60 @@ static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
value_igi += 0;
else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
value_igi++;
else
else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
value_igi += 2;
value_igi = clamp(value_igi, (u8)DM_DIG_FA_LOWER, (u8)DM_DIG_FA_UPPER);
if (value_igi > DM_DIG_FA_UPPER)
value_igi = DM_DIG_FA_UPPER;
else if (value_igi < DM_DIG_FA_LOWER)
value_igi = DM_DIG_FA_LOWER;
if (rtlpriv->falsealm_cnt.cnt_all > 10000)
value_igi = 0x32;
dm_digtable->cur_igvalue = value_igi;
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dgtbl = &rtlpriv->dm_digtable;
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
if (rtlpriv->falsealm_cnt.cnt_all > dgtbl->fa_highthresh) {
if ((dgtbl->back_val - 2) < dgtbl->back_range_min)
dgtbl->back_val = dgtbl->back_range_min;
if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
if ((dm_digtable->back_val - 2) <
dm_digtable->back_range_min)
dm_digtable->back_val =
dm_digtable->back_range_min;
else
dgtbl->back_val -= 2;
} else if (rtlpriv->falsealm_cnt.cnt_all < dgtbl->fa_lowthresh) {
if ((dgtbl->back_val + 2) > dgtbl->back_range_max)
dgtbl->back_val = dgtbl->back_range_max;
dm_digtable->back_val -= 2;
} else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
if ((dm_digtable->back_val + 2) >
dm_digtable->back_range_max)
dm_digtable->back_val =
dm_digtable->back_range_max;
else
dgtbl->back_val += 2;
dm_digtable->back_val += 2;
}
if ((dgtbl->rssi_val_min + 10 - dgtbl->back_val) >
dgtbl->rx_gain_max)
dgtbl->cur_igvalue = dgtbl->rx_gain_max;
else if ((dgtbl->rssi_val_min + 10 -
dgtbl->back_val) < dgtbl->rx_gain_min)
dgtbl->cur_igvalue = dgtbl->rx_gain_min;
if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) >
dm_digtable->rx_gain_max)
dm_digtable->cur_igvalue = dm_digtable->rx_gain_max;
else if ((dm_digtable->rssi_val_min + 10 -
dm_digtable->back_val) < dm_digtable->rx_gain_min)
dm_digtable->cur_igvalue = dm_digtable->rx_gain_min;
else
dgtbl->cur_igvalue = dgtbl->rssi_val_min + 10 - dgtbl->back_val;
dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
dm_digtable->back_val;
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
"rssi_val_min = %x back_val %x\n",
dgtbl->rssi_val_min, dgtbl->back_val);
dm_digtable->rssi_val_min, dm_digtable->back_val);
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
{
static u8 binitialized;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
@ -318,16 +321,15 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
if (mac->opmode == NL80211_IFTYPE_ADHOC)
multi_sta = true;
if ((!multi_sta) ||
(dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) {
rtlpriv->initialized = false;
if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) {
binitialized = false;
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
return;
} else if (!rtlpriv->initialized) {
rtlpriv->initialized = true;
} else if (!binitialized) {
binitialized = true;
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
dm_digtable->cur_igvalue = 0x20;
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
@ -337,7 +339,7 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
if (dm_digtable->dig_ext_port_stage ==
DIG_EXT_PORT_STAGE_2) {
dm_digtable->cur_igvalue = 0x20;
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
@ -348,7 +350,7 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
} else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
dm_digtable->cur_igvalue = 0x20;
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
@ -357,22 +359,22 @@ static void rtl8723ae_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
dm_digtable->dig_ext_port_stage);
}
static void rtl8723ae_dm_initial_gain_sta(struct ieee80211_hw *hw)
static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
"presta_cstate = %x, cursta_cstate = %x\n",
dm_digtable->presta_cstate,
dm_digtable->cursta_cstate);
dm_digtable->presta_cstate,
dm_digtable->cursta_cstate);
if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
dm_digtable->rssi_val_min = rtl_init_gain_min_pwdb(hw);
dm_digtable->rssi_val_min =
rtl8723e_dm_initial_gain_min_pwdb(hw);
rtl92c_dm_ctrl_initgain_by_rssi(hw);
}
} else {
@ -381,16 +383,17 @@ static void rtl8723ae_dm_initial_gain_sta(struct ieee80211_hw *hw)
dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
dm_digtable->cur_igvalue = 0x20;
dm_digtable->pre_igvalue = 0;
rtl8723ae_dm_write_dig(hw);
rtl8723e_dm_write_dig(hw);
}
}
static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
dm_digtable->rssi_val_min = rtl_init_gain_min_pwdb(hw);
dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw);
if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
if (dm_digtable->rssi_val_min <= 25)
@ -418,12 +421,11 @@ static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
CCK_FA_STAGE_High;
else
dm_digtable->cur_cck_fa_state =
CCK_FA_STAGE_Low;
CCK_FA_STAGE_LOW;
if (dm_digtable->pre_cck_fa_state !=
dm_digtable->cur_cck_fa_state) {
if (dm_digtable->cur_cck_fa_state ==
CCK_FA_STAGE_Low)
CCK_FA_STAGE_LOW)
rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
0x83);
else
@ -449,13 +451,13 @@ static void rtl8723ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
}
static void rtl8723ae_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
if (mac->act_scanning == true)
if (mac->act_scanning)
return;
if (mac->link_state >= MAC80211_LINKED)
@ -463,28 +465,29 @@ static void rtl8723ae_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
else
dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
rtl8723ae_dm_initial_gain_sta(hw);
rtl8723ae_dm_initial_gain_multi_sta(hw);
rtl8723ae_dm_cck_packet_detection_thresh(hw);
rtl8723e_dm_initial_gain_sta(hw);
rtl8723e_dm_initial_gain_multi_sta(hw);
rtl8723e_dm_cck_packet_detection_thresh(hw);
dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
}
static void rtl8723ae_dm_dig(struct ieee80211_hw *hw)
static void rtl8723e_dm_dig(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
if (rtlpriv->dm.dm_initialgain_enable == false)
if (!rtlpriv->dm.dm_initialgain_enable)
return;
if (dm_digtable->dig_enable_flag == false)
if (!dm_digtable->dig_enable_flag)
return;
rtl8723ae_dm_ctrl_initgain_by_twoport(hw);
rtl8723e_dm_ctrl_initgain_by_twoport(hw);
}
static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
@ -502,7 +505,7 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
if ((mac->link_state < MAC80211_LINKED) &&
(rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
"Not connected\n");
"Not connected to any\n");
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
@ -512,18 +515,21 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
if (mac->link_state >= MAC80211_LINKED) {
if (mac->opmode == NL80211_IFTYPE_ADHOC) {
undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
undec_sm_pwdb =
rtlpriv->dm.entry_min_undec_sm_pwdb;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"AP Client PWDB = 0x%lx\n",
undec_sm_pwdb);
undec_sm_pwdb);
} else {
undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
undec_sm_pwdb =
rtlpriv->dm.undec_sm_pwdb;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"STA Default Port PWDB = 0x%lx\n",
undec_sm_pwdb);
undec_sm_pwdb);
}
} else {
undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
undec_sm_pwdb =
rtlpriv->dm.entry_min_undec_sm_pwdb;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"AP Ext Port PWDB = 0x%lx\n",
@ -534,37 +540,39 @@ static void rtl8723ae_dm_dynamic_txpower(struct ieee80211_hw *hw)
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
} else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
(undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
} else if ((undec_sm_pwdb <
(TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
(undec_sm_pwdb >=
TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
} else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
} else if (undec_sm_pwdb <
(TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"TXHIGHPWRLEVEL_NORMAL\n");
}
if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) {
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"PHY_SetTxPowerLevel8192S() Channel = %d\n",
rtlphy->current_channel);
rtl8723ae_phy_set_txpower_level(hw, rtlphy->current_channel);
rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
}
rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
}
void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw)
void rtl8723e_dm_write_dig(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
"cur_igvalue = 0x%x, "
"pre_igvalue = 0x%x, back_val = %d\n",
dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
dm_digtable->back_val);
"cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
dm_digtable->back_val);
if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
@ -576,32 +584,39 @@ void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw)
}
}
static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw)
{
}
static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
static u64 last_txok_cnt;
static u64 last_rxok_cnt;
static u32 last_bt_edca_ul;
static u32 last_bt_edca_dl;
u64 cur_txok_cnt = 0;
u64 cur_rxok_cnt = 0;
u32 edca_be_ul = 0x5ea42b;
u32 edca_be_dl = 0x5ea42b;
bool bt_change_edca = false;
if ((mac->last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
(mac->last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) ||
(last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) {
rtlpriv->dm.current_turbo_edca = false;
mac->last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
mac->last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul;
last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl;
}
if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
if (rtlpriv->btcoexist.bt_edca_ul != 0) {
edca_be_ul = rtlpriv->btcoexist.bt_edca_ul;
bt_change_edca = true;
}
if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
if (rtlpriv->btcoexist.bt_edca_dl != 0) {
edca_be_ul = rtlpriv->btcoexist.bt_edca_dl;
bt_change_edca = true;
}
@ -609,22 +624,11 @@ static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
rtlpriv->dm.current_turbo_edca = false;
return;
}
if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
if (!(edca_be_ul & 0xffff0000))
edca_be_ul |= 0x005e0000;
if (!(edca_be_dl & 0xffff0000))
edca_be_dl |= 0x005e0000;
}
if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
(!rtlpriv->dm.disable_framebursting))) {
cur_txok_cnt = rtlpriv->stats.txbytesunicast -
mac->last_txok_cnt;
cur_rxok_cnt = rtlpriv->stats.rxbytesunicast -
mac->last_rxok_cnt;
cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
if (cur_rxok_cnt > 4 * cur_txok_cnt) {
if (!rtlpriv->dm.is_cur_rdlstate ||
@ -647,18 +651,20 @@ static void rtl8723ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
} else {
if (rtlpriv->dm.current_turbo_edca) {
u8 tmp = AC0_BE;
rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
&tmp);
rtlpriv->cfg->ops->set_hw_reg(hw,
HW_VAR_AC_PARAM,
(u8 *)(&tmp));
rtlpriv->dm.current_turbo_edca = false;
}
}
rtlpriv->dm.is_any_nonbepkts = false;
mac->last_txok_cnt = rtlpriv->stats.txbytesunicast;
mac->last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
last_txok_cnt = rtlpriv->stats.txbytesunicast;
last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
}
static void rtl8723ae_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter(
struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
@ -667,10 +673,20 @@ static void rtl8723ae_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
"pMgntInfo->txpower_tracking = %d\n",
rtlpriv->dm.txpower_tracking);
rtlpriv->dm.txpower_tracking);
}
void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
{
rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw);
}
void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw)
{
return;
}
void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rate_adaptive *p_ra = &(rtlpriv->ra);
@ -682,101 +698,32 @@ void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
rtlpriv->dm.useramask = true;
else
rtlpriv->dm.useramask = false;
}
static void rtl8723ae_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rate_adaptive *p_ra = &(rtlpriv->ra);
u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
struct ieee80211_sta *sta = NULL;
if (is_hal_stop(rtlhal)) {
RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
" driver is going to unload\n");
return;
}
if (!rtlpriv->dm.useramask) {
RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
" driver does not control rate adaptive mask\n");
return;
}
if (mac->link_state == MAC80211_LINKED &&
mac->opmode == NL80211_IFTYPE_STATION) {
switch (p_ra->pre_ratr_state) {
case DM_RATR_STA_HIGH:
high_rssithresh_for_ra = 50;
low_rssithresh_for_ra = 20;
break;
case DM_RATR_STA_MIDDLE:
high_rssithresh_for_ra = 55;
low_rssithresh_for_ra = 20;
break;
case DM_RATR_STA_LOW:
high_rssithresh_for_ra = 50;
low_rssithresh_for_ra = 25;
break;
default:
high_rssithresh_for_ra = 50;
low_rssithresh_for_ra = 20;
break;
}
if (rtlpriv->dm.undec_sm_pwdb > high_rssithresh_for_ra)
p_ra->ratr_state = DM_RATR_STA_HIGH;
else if (rtlpriv->dm.undec_sm_pwdb > low_rssithresh_for_ra)
p_ra->ratr_state = DM_RATR_STA_MIDDLE;
else
p_ra->ratr_state = DM_RATR_STA_LOW;
if (p_ra->pre_ratr_state != p_ra->ratr_state) {
RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
"RSSI = %ld\n",
rtlpriv->dm.undec_sm_pwdb);
RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
"RSSI_LEVEL = %d\n", p_ra->ratr_state);
RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
"PreState = %d, CurState = %d\n",
p_ra->pre_ratr_state, p_ra->ratr_state);
rcu_read_lock();
sta = rtl_find_sta(hw, mac->bssid);
if (sta)
rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
p_ra->ratr_state);
rcu_read_unlock();
p_ra->pre_ratr_state = p_ra->ratr_state;
}
}
}
void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
static u8 initialize;
static u32 reg_874, reg_c70, reg_85c, reg_a74;
if (!rtlpriv->reg_init) {
rtlpriv->reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
MASKDWORD) & 0x1CC000) >> 14;
if (initialize == 0) {
reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
MASKDWORD) & 0x1CC000) >> 14;
rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
MASKDWORD) & BIT(3)) >> 3;
reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
MASKDWORD) & BIT(3)) >> 3;
rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
MASKDWORD) & 0xFF000000) >> 24;
reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
MASKDWORD) & 0xFF000000) >> 24;
rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) &
0xF000) >> 12;
reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
rtlpriv->reg_init = true;
initialize = 1;
}
if (!force_in_normal) {
if (!bforce_in_normal) {
if (dm_pstable->rssi_val_min != 0) {
if (dm_pstable->pre_rfstate == RF_NORMAL) {
if (dm_pstable->rssi_val_min >= 30)
@ -798,7 +745,6 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
if (dm_pstable->cur_rfstate == RF_SAVE) {
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
BIT(5), 0x1);
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
@ -813,12 +759,12 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
} else {
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
0x1CC000, rtlpriv->reg_874);
0x1CC000, reg_874);
rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
rtlpriv->reg_c70);
reg_c70);
rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
rtlpriv->reg_85c);
rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74);
reg_85c);
rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
BIT(5), 0x0);
@ -828,7 +774,7 @@ void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 force_in_normal)
}
}
static void rtl8723ae_dm_dynamic_bpowersaving(struct ieee80211_hw *hw)
static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@ -847,48 +793,49 @@ static void rtl8723ae_dm_dynamic_bpowersaving(struct ieee80211_hw *hw)
rtlpriv->dm.entry_min_undec_sm_pwdb;
RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
"AP Client PWDB = 0x%lx\n",
dm_pstable->rssi_val_min);
dm_pstable->rssi_val_min);
} else {
dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
dm_pstable->rssi_val_min =
rtlpriv->dm.undec_sm_pwdb;
RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
"STA Default Port PWDB = 0x%lx\n",
dm_pstable->rssi_val_min);
dm_pstable->rssi_val_min);
}
} else {
dm_pstable->rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
dm_pstable->rssi_val_min =
rtlpriv->dm.entry_min_undec_sm_pwdb;
RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
"AP Ext Port PWDB = 0x%lx\n",
dm_pstable->rssi_val_min);
dm_pstable->rssi_val_min);
}
rtl8723ae_dm_rf_saving(hw, false);
rtl8723e_dm_rf_saving(hw, false);
}
void rtl8723ae_dm_init(struct ieee80211_hw *hw)
void rtl8723e_dm_init(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
rtl8723ae_dm_diginit(hw);
rtl8723e_dm_diginit(hw);
rtl8723_dm_init_dynamic_txpower(hw);
rtl8723_dm_init_edca_turbo(hw);
rtl8723ae_dm_init_rate_adaptive_mask(hw);
rtl8723ae_dm_initialize_txpower_tracking(hw);
rtl8723e_dm_init_rate_adaptive_mask(hw);
rtl8723e_dm_initialize_txpower_tracking(hw);
rtl8723_dm_init_dynamic_bb_powersaving(hw);
}
void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw)
void rtl8723e_dm_watchdog(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
bool fw_current_inpsmode = false;
bool fw_ps_awake = true;
rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
(u8 *) (&fw_current_inpsmode));
(u8 *)(&fw_current_inpsmode));
rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
(u8 *) (&fw_ps_awake));
(u8 *)(&fw_ps_awake));
if (ppsc->p2p_ps_info.p2p_ps_mode)
fw_ps_awake = false;
@ -896,58 +843,57 @@ void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw)
if ((ppsc->rfpwr_state == ERFON) &&
((!fw_current_inpsmode) && fw_ps_awake) &&
(!ppsc->rfchange_inprogress)) {
rtl8723ae_dm_dig(hw);
rtl8723ae_dm_false_alarm_counter_statistics(hw);
rtl8723ae_dm_dynamic_bpowersaving(hw);
rtl8723ae_dm_dynamic_txpower(hw);
rtl8723ae_dm_refresh_rate_adaptive_mask(hw);
rtl8723ae_dm_bt_coexist(hw);
rtl8723ae_dm_check_edca_turbo(hw);
rtl8723e_dm_pwdb_monitor(hw);
rtl8723e_dm_dig(hw);
rtl8723e_dm_false_alarm_counter_statistics(hw);
rtl8723e_dm_dynamic_bb_powersaving(hw);
rtl8723e_dm_dynamic_txpower(hw);
rtl8723e_dm_check_txpower_tracking(hw);
/* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
rtl8723e_dm_bt_coexist(hw);
rtl8723e_dm_check_edca_turbo(hw);
}
if (rtlpcipriv->bt_coexist.init_set)
if (rtlpriv->btcoexist.init_set)
rtl_write_byte(rtlpriv, 0x76e, 0xc);
}
static void rtl8723ae_dm_init_bt_coexist(struct ieee80211_hw *hw)
static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
rtlpcipriv->bt_coexist.bt_rfreg_origin_1e
rtlpriv->btcoexist.bt_rfreg_origin_1e
= rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff);
rtlpcipriv->bt_coexist.bt_rfreg_origin_1f
rtlpriv->btcoexist.bt_rfreg_origin_1f
= rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0);
rtlpcipriv->bt_coexist.cstate = 0;
rtlpcipriv->bt_coexist.previous_state = 0;
rtlpcipriv->bt_coexist.cstate_h = 0;
rtlpcipriv->bt_coexist.previous_state_h = 0;
rtlpcipriv->bt_coexist.lps_counter = 0;
rtlpriv->btcoexist.cstate = 0;
rtlpriv->btcoexist.previous_state = 0;
rtlpriv->btcoexist.cstate_h = 0;
rtlpriv->btcoexist.previous_state_h = 0;
rtlpriv->btcoexist.lps_counter = 0;
/* Enable counter statistics */
rtl_write_byte(rtlpriv, 0x76e, 0x4);
rtl_write_byte(rtlpriv, 0x778, 0x3);
rtl_write_byte(rtlpriv, 0x40, 0x20);
rtlpcipriv->bt_coexist.init_set = true;
rtlpriv->btcoexist.init_set = true;
}
void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw)
void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
u8 tmp_byte = 0;
if (!rtlpcipriv->bt_coexist.bt_coexistence) {
if (!rtlpriv->btcoexist.bt_coexistence) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
"[DM]{BT], BT not exist!!\n");
return;
}
if (!rtlpcipriv->bt_coexist.init_set) {
if (!rtlpriv->btcoexist.init_set) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
"[DM][BT], rtl8723ae_dm_bt_coexist()\n");
rtl8723ae_dm_init_bt_coexist(hw);
"[DM][BT], rtl8723e_dm_bt_coexist()\n");
rtl8723e_dm_init_bt_coexist(hw);
}
tmp_byte = rtl_read_byte(rtlpriv, 0x40);
@ -955,5 +901,5 @@ void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw)
"[DM][BT], 0x40 is 0x%x", tmp_byte);
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG,
"[DM][BT], bt_dm_coexist start");
rtl8723ae_dm_bt_coexist_8723(hw);
rtl8723e_dm_bt_coexist_8723(hw);
}

48
drivers/net/wireless/rtlwifi/rtl8723ae/dm.h
View File

@ -25,17 +25,23 @@
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#ifndef __RTL8723E_DM_H__
#define __RTL8723E_DM_H__
#define HAL_DM_DIG_DISABLE BIT(0)
#define HAL_DM_HIPWR_DISABLE BIT(1)
#define OFDM_TABLE_LENGTH 37
#define CCK_TABLE_LENGTH 33
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
@ -63,12 +69,18 @@
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define CTS2SELF_THVAL 30
#define REGC38_TH 20
#define WAIOTTHVAL 25
#define TXHIGHPWRLEVEL_NORMAL 0
#define TXHIGHPWRLEVEL_LEVEL1 1
#define TXHIGHPWRLEVEL_LEVEL2 2
#define TXHIGHPWRLEVEL_BT1 3
#define TXHIGHPWRLEVEL_BT2 4
#define DM_TYPE_BYFW 0
#define DM_TYPE_BYDRIVER 1
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
@ -82,6 +94,7 @@ struct swat_t {
long trying_threshold;
u8 cur_antenna;
u8 pre_antenna;
};
enum tag_dynamic_init_gain_operation_type_definition {
@ -98,7 +111,7 @@ enum tag_dynamic_init_gain_operation_type_definition {
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_FA_STAGE_Low = 2,
CCK_FA_STAGE_LOW = 2,
CCK_FA_STAGE_High = 3,
CCK_PD_STAGE_MAX = 4,
};
@ -138,17 +151,24 @@ enum dm_dig_connect_e {
DIG_CONNECT_MAX
};
#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
((((struct rtl_priv *)(_priv))->mac80211.opmode == \
NL80211_IFTYPE_ADHOC) ? \
(((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) \
: (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))
void rtl8723ae_dm_init(struct ieee80211_hw *hw);
void rtl8723ae_dm_watchdog(struct ieee80211_hw *hw);
void rtl8723ae_dm_write_dig(struct ieee80211_hw *hw);
void rtl8723ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
void rtl8723ae_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
void rtl8723ae_dm_bt_coexist(struct ieee80211_hw *hw);
( \
(((struct rtl_priv *)(_priv))->mac80211.opmode == \
NL80211_IFTYPE_ADHOC) ? \
(((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
(((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb) \
)
void rtl8723e_dm_init(struct ieee80211_hw *hw);
void rtl8723e_dm_watchdog(struct ieee80211_hw *hw);
void rtl8723e_dm_write_dig(struct ieee80211_hw *hw);
void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw);
#endif

260
drivers/net/wireless/rtlwifi/rtl8723ae/fw.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -25,8 +21,7 @@
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
@ -36,7 +31,8 @@
#include "fw.h"
#include "../rtl8723com/fw_common.h"
static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
static bool _rtl8723e_check_fw_read_last_h2c(struct ieee80211_hw *hw,
u8 boxnum)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 val_hmetfr, val_mcutst_1;
@ -50,17 +46,17 @@ static bool rtl8723ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
return result;
}
static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
u8 element_id, u32 cmd_len,
u8 *p_cmdbuffer)
static void _rtl8723e_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *cmdbuffer)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u8 boxnum;
u16 box_reg = 0, box_extreg = 0;
u8 u1tmp;
bool isfw_rd = false;
bool bwrite_success = false;
u8 u1b_tmp;
bool isfw_read = false;
u8 buf_index = 0;
bool bwrite_sucess = false;
u8 wait_h2c_limmit = 100;
u8 wait_writeh2c_limmit = 100;
u8 boxcontent[4], boxextcontent[2];
@ -83,7 +79,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
h2c_waitcounter++;
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Wait 100 us (%d times)...\n",
h2c_waitcounter);
h2c_waitcounter);
udelay(100);
if (h2c_waitcounter > 1000)
@ -99,12 +95,11 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
}
}
while (!bwrite_success) {
while (!bwrite_sucess) {
wait_writeh2c_limmit--;
if (wait_writeh2c_limmit == 0) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Write H2C fail because no trigger "
"for FW INT!\n");
"Write H2C fail because no trigger for FW INT!\n");
break;
}
@ -128,34 +123,35 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
"switch case not process\n");
break;
}
isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
while (!isfw_rd) {
isfw_read = _rtl8723e_check_fw_read_last_h2c(hw, boxnum);
while (!isfw_read) {
wait_h2c_limmit--;
if (wait_h2c_limmit == 0) {
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Waiting too long for FW read clear HMEBox(%d)!\n",
"Wating too long for FW read clear HMEBox(%d)!\n",
boxnum);
break;
}
udelay(10);
isfw_rd = rtl8723ae_check_fw_read_last_h2c(hw, boxnum);
u1tmp = rtl_read_byte(rtlpriv, 0x1BF);
isfw_read = _rtl8723e_check_fw_read_last_h2c(hw,
boxnum);
u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Waiting for FW read clear HMEBox(%d)!!! "
"0x1BF = %2x\n", boxnum, u1tmp);
"Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n",
boxnum, u1b_tmp);
}
if (!isfw_rd) {
if (!isfw_read) {
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Write H2C register BOX[%d] fail!!!!! "
"Fw do not read.\n", boxnum);
"Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
boxnum);
break;
}
@ -169,8 +165,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
switch (cmd_len) {
case 1:
boxcontent[0] &= ~(BIT(7));
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer, 1);
memcpy((u8 *)(boxcontent) + 1,
cmdbuffer + buf_index, 1);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
@ -179,8 +175,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
case 2:
boxcontent[0] &= ~(BIT(7));
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer, 2);
memcpy((u8 *)(boxcontent) + 1,
cmdbuffer + buf_index, 2);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
@ -189,8 +185,8 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
case 3:
boxcontent[0] &= ~(BIT(7));
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer, 3);
memcpy((u8 *)(boxcontent) + 1,
cmdbuffer + buf_index, 3);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
@ -199,10 +195,10 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
case 4:
boxcontent[0] |= (BIT(7));
memcpy((u8 *) (boxextcontent),
p_cmdbuffer, 2);
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer + 2, 2);
memcpy((u8 *)(boxextcontent),
cmdbuffer + buf_index, 2);
memcpy((u8 *)(boxcontent) + 1,
cmdbuffer + buf_index + 2, 2);
for (idx = 0; idx < 2; idx++) {
rtl_write_byte(rtlpriv, box_extreg + idx,
@ -216,10 +212,10 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
case 5:
boxcontent[0] |= (BIT(7));
memcpy((u8 *) (boxextcontent),
p_cmdbuffer, 2);
memcpy((u8 *) (boxcontent) + 1,
p_cmdbuffer + 2, 3);
memcpy((u8 *)(boxextcontent),
cmdbuffer + buf_index, 2);
memcpy((u8 *)(boxcontent) + 1,
cmdbuffer + buf_index + 2, 3);
for (idx = 0; idx < 2; idx++) {
rtl_write_byte(rtlpriv, box_extreg + idx,
@ -237,7 +233,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
break;
}
bwrite_success = true;
bwrite_sucess = true;
rtlhal->last_hmeboxnum = boxnum + 1;
if (rtlhal->last_hmeboxnum == 4)
@ -245,7 +241,7 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"pHalData->last_hmeboxnum = %d\n",
rtlhal->last_hmeboxnum);
rtlhal->last_hmeboxnum);
}
spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
@ -255,53 +251,50 @@ static void _rtl8723ae_fill_h2c_command(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
}
void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw,
u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
void rtl8723e_fill_h2c_cmd(struct ieee80211_hw *hw,
u8 element_id, u32 cmd_len, u8 *cmdbuffer)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u32 tmp_cmdbuf[2];
if (rtlhal->fw_ready == false) {
if (!rtlhal->fw_ready) {
RT_ASSERT(false,
"return H2C cmd because of Fw download fail!!!\n");
"return H2C cmd because of Fw download fail!!!\n");
return;
}
_rtl8723ae_fill_h2c_command(hw, element_id, cmd_len, p_cmdbuffer);
return;
memset(tmp_cmdbuf, 0, 8);
memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
_rtl8723e_fill_h2c_command(hw, element_id, cmd_len,
(u8 *)&tmp_cmdbuf);
}
static bool _rtl8723ae_cmd_send_packet(struct ieee80211_hw *hw,
struct sk_buff *skb)
void rtl8723e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring;
struct rtl_tx_desc *pdesc;
unsigned long flags;
struct sk_buff *pskb = NULL;
u8 u1_h2c_set_pwrmode[3] = { 0 };
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
ring = &rtlpci->tx_ring[BEACON_QUEUE];
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
pskb = __skb_dequeue(&ring->queue);
if (pskb)
kfree_skb(pskb);
SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
(rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
ppsc->reg_max_lps_awakeintvl);
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
pdesc = &ring->desc[0];
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
__skb_queue_tail(&ring->queue, skb);
spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
return true;
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl8723e_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
u1_h2c_set_pwrmode, 3);
rtl8723e_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
}
#define BEACON_PG 0 /* ->1 */
#define PSPOLL_PG 2
#define NULL_PG 3
#define PROBERSP_PG 4 /* ->5 */
#define TOTAL_RESERVED_PKT_LEN 768
static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
/* page 0 beacon */
0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
@ -412,111 +405,111 @@ static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
void rtl8723e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct sk_buff *skb = NULL;
u32 totalpacketlen;
bool rtstatus;
u8 u1RsvdPageLoc[3] = { 0 };
bool dlok = false;
u8 u1rsvdpageloc[3] = { 0 };
bool b_dlok = false;
u8 *beacon;
u8 *p_pspoll;
u8 *nullfunc;
u8 *p_probersp;
/*---------------------------------------------------------
(1) beacon
---------------------------------------------------------
*/
* (1) beacon
*---------------------------------------------------------
*/
beacon = &reserved_page_packet[BEACON_PG * 128];
SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
/*-------------------------------------------------------
(2) ps-poll
--------------------------------------------------------
*/
* (2) ps-poll
*--------------------------------------------------------
*/
p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
/*--------------------------------------------------------
(3) null data
---------------------------------------------------------i
*/
* (3) null data
*---------------------------------------------------------
*/
nullfunc = &reserved_page_packet[NULL_PG * 128];
SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
/*---------------------------------------------------------
(4) probe response
----------------------------------------------------------
*/
* (4) probe response
*----------------------------------------------------------
*/
p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
totalpacketlen = TOTAL_RESERVED_PKT_LEN;
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
"rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
"rtl8723e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
&reserved_page_packet[0], totalpacketlen);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl8723ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
u1RsvdPageLoc, 3);
"rtl8723e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
u1rsvdpageloc, 3);
skb = dev_alloc_skb(totalpacketlen);
memcpy((u8 *) skb_put(skb, totalpacketlen),
memcpy((u8 *)skb_put(skb, totalpacketlen),
&reserved_page_packet, totalpacketlen);
rtstatus = _rtl8723ae_cmd_send_packet(hw, skb);
rtstatus = rtl8723_cmd_send_packet(hw, skb);
if (rtstatus)
dlok = true;
b_dlok = true;
if (dlok) {
if (b_dlok) {
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"Set RSVD page location to Fw.\n");
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"H2C_RSVDPAGE:\n",
u1RsvdPageLoc, 3);
rtl8723ae_fill_h2c_cmd(hw, H2C_RSVDPAGE,
sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
"H2C_RSVDPAGE:\n",
u1rsvdpageloc, 3);
rtl8723e_fill_h2c_cmd(hw, H2C_RSVDPAGE,
sizeof(u1rsvdpageloc), u1rsvdpageloc);
} else
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"Set RSVD page location to Fw FAIL!!!!!!.\n");
}
void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
void rtl8723e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
{
u8 u1_joinbssrpt_parm[1] = { 0 };
SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
rtl8723ae_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
rtl8723e_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
}
static void rtl8723e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw,
u8 ctwindow)
{
u8 u1_ctwindow_period[1] = {ctwindow};
u8 u1_ctwindow_period[1] = { ctwindow};
rtl8723e_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
}
void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
void rtl8723e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
@ -530,7 +523,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
break;
case P2P_PS_ENABLE:
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
@ -542,7 +535,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
}
/* hw only support 2 set of NoA */
for (i = 0; i < p2pinfo->noa_num; i++) {
for (i = 0 ; i < p2pinfo->noa_num ; i++) {
/* To control the register setting for which NOA*/
rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
if (i == 0)
@ -561,27 +554,33 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
start_time = p2pinfo->noa_start_time[i];
if (p2pinfo->noa_count_type[i] != 1) {
while (start_time <= (tsf_low+(50*1024))) {
start_time += p2pinfo->noa_interval[i];
while (start_time <=
(tsf_low+(50*1024))) {
start_time +=
p2pinfo->noa_interval[i];
if (p2pinfo->noa_count_type[i] != 255)
p2pinfo->noa_count_type[i]--;
}
}
rtl_write_dword(rtlpriv, 0x5E8, start_time);
rtl_write_dword(rtlpriv, 0x5EC,
p2pinfo->noa_count_type[i]);
p2pinfo->noa_count_type[i]);
}
if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
/* rst p2p circuit */
rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
p2p_ps_offload->offload_en = 1;
if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
p2p_ps_offload->role = 1;
p2p_ps_offload->allstasleep = 0;
} else {
p2p_ps_offload->role = 0;
}
p2p_ps_offload->discovery = 0;
}
break;
@ -597,26 +596,7 @@ void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
default:
break;
}
rtl8723ae_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
}
void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 u1_h2c_set_pwrmode[3] = { 0 };
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
SET_H2CCMD_PWRMODE_PARM_SMART_PS_23A(u1_h2c_set_pwrmode,
(rtlpriv->mac80211.p2p) ?
ppsc->smart_ps : 1);
SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
ppsc->reg_max_lps_awakeintvl);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl8723ae_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
u1_h2c_set_pwrmode, 3);
rtl8723ae_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
rtl8723e_fill_h2c_cmd(hw, H2C_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
}

55
drivers/net/wireless/rtlwifi/rtl8723ae/fw.h
View File

@ -24,50 +24,28 @@
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#ifndef __RTL92C__FW__H__
#define __RTL92C__FW__H__
#define FW_8192C_SIZE 0x3000
#define FW_8192C_START_ADDRESS 0x1000
#define FW_8192C_END_ADDRESS 0x3FFF
#define FW_8192C_PAGE_SIZE 4096
#define FW_8192C_PAGE_SIZE 4096
#define FW_8192C_POLLING_DELAY 5
#define FW_8192C_POLLING_TIMEOUT_COUNT 6000
#define FW_8192C_POLLING_TIMEOUT_COUNT 1000
#define BEACON_PG 0
#define PSPOLL_PG 2
#define NULL_PG 3
#define PROBERSP_PG 4 /* ->5 */
#define IS_FW_HEADER_EXIST(_pfwhdr) \
((_pfwhdr->signature&0xFFFF) == 0x2300 ||\
(_pfwhdr->signature&0xFFFF) == 0x2301 ||\
(_pfwhdr->signature&0xFFFF) == 0x2302)
#define TOTAL_RESERVED_PKT_LEN 768
#define IS_FW_HEADER_EXIST(_pfwhdr) \
((_pfwhdr->signature&0xFF00) == 0x2300)
struct rtl8723ae_firmware_header {
u16 signature;
u8 category;
u8 function;
u16 version;
u8 subversion;
u8 rsvd1;
u8 month;
u8 date;
u8 hour;
u8 minute;
u16 ramcodeSize;
u16 rsvd2;
u32 svnindex;
u32 rsvd3;
u32 rsvd4;
u32 rsvd5;
};
#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS_23A(__ph2ccmd, __val) \
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
@ -80,11 +58,10 @@ struct rtl8723ae_firmware_header {
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
void rtl8723ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
void rtl8723ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
void rtl8723ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl8723ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
void rtl8723ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
void rtl8723e_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
void rtl8723e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
void rtl8723e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl8723e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
void rtl8723e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
#endif

410
drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -31,96 +27,102 @@
#include "../pci.h"
#include "dm.h"
#include "fw.h"
#include "../rtl8723com/fw_common.h"
#include "phy.h"
#include "reg.h"
#include "hal_btc.h"
void rtl8723ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
bool reject)
static bool bt_operation_on;
void rtl8723e_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
bool b_reject)
{
}
void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlpriv->link_info.busytraffic) {
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_IDLE;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_IDLE;
if (rtlpriv->link_info.tx_busy_traffic)
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_UPLINK;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_UPLINK;
else
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_UPLINK;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_UPLINK;
if (rtlpriv->link_info.rx_busy_traffic)
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_DOWNLINK;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_DOWNLINK;
else
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_DOWNLINK;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_DOWNLINK;
} else {
rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_WIFI_IDLE;
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_UPLINK;
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_DOWNLINK;
rtlpriv->btcoexist.cstate |= BT_COEX_STATE_WIFI_IDLE;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_UPLINK;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_DOWNLINK;
}
if (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
rtlpriv->mac80211.mode == WIRELESS_MODE_B) {
rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_WIFI_LEGACY;
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_HT20;
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_HT40;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_LEGACY;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_HT20;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_HT40;
} else {
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_WIFI_LEGACY;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_LEGACY;
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_HT40;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_HT20;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_HT40;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_HT20;
} else {
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_HT20;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_HT40;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_HT20;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_HT40;
}
}
if (rtlpriv->bt_operation_on)
rtlpcipriv->bt_coexist.cstate |= BT_COEX_STATE_BT30;
if (bt_operation_on)
rtlpriv->btcoexist.cstate |= BT_COEX_STATE_BT30;
else
rtlpcipriv->bt_coexist.cstate &= ~BT_COEX_STATE_BT30;
rtlpriv->btcoexist.cstate &= ~BT_COEX_STATE_BT30;
}
u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rssi_thresh1)
u8 rtl8723e_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rssi_thresh1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
long smooth;
long undecoratedsmoothed_pwdb;
u8 bt_rssi_state = 0;
smooth = rtl8723ae_dm_bt_get_rx_ss(hw);
undecoratedsmoothed_pwdb = rtl8723e_dm_bt_get_rx_ss(hw);
if (level_num == 2) {
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (smooth >= (rssi_thresh +
BT_FW_COEX_THRESH_TOL)) {
if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->bt_coexist.cstate |=
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->bt_coexist.cstate &=
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to High\n");
@ -130,12 +132,12 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
"[DM][BT], RSSI_1 state stay at Low\n");
}
} else {
if (smooth < rssi_thresh) {
if (undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to Low\n");
} else {
@ -148,22 +150,22 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
if (rssi_thresh > rssi_thresh1) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 thresh error!!\n");
return rtlpcipriv->bt_coexist.bt_pre_rssi_state;
return rtlpriv->btcoexist.bt_pre_rssi_state;
}
if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (smooth >=
if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh+BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to Medium\n");
} else {
@ -171,28 +173,28 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state stay at Low\n");
}
} else if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_MEDIUM) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_MEDIUM)) {
if (smooth >= (rssi_thresh1 +
BT_FW_COEX_THRESH_TOL)) {
} else if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_MEDIUM) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_MEDIUM)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to High\n");
} else if (smooth < rssi_thresh) {
} else if (undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->bt_coexist.cstate |=
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->bt_coexist.cstate &=
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->bt_coexist.cstate &=
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to Low\n");
@ -202,13 +204,13 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
"[DM][BT], RSSI_1 state stay at Medium\n");
}
} else {
if (smooth < rssi_thresh1) {
if (undecoratedsmoothed_pwdb < rssi_thresh1) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->bt_coexist.cstate |=
rtlpriv->btcoexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpcipriv->bt_coexist.cstate &=
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->bt_coexist.cstate &=
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_1_LOW;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI_1 state switch to Medium\n");
@ -219,38 +221,37 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
}
}
}
rtlpcipriv->bt_coexist.bt_pre_rssi_state1 = bt_rssi_state;
rtlpriv->btcoexist.bt_pre_rssi_state1 = bt_rssi_state;
return bt_rssi_state;
}
u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rssi_thresh1)
u8 rtl8723e_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
u8 level_num,
u8 rssi_thresh,
u8 rssi_thresh1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
long smooth;
long undecoratedsmoothed_pwdb = 0;
u8 bt_rssi_state = 0;
smooth = rtl8723ae_dm_bt_get_rx_ss(hw);
undecoratedsmoothed_pwdb = rtl8723e_dm_bt_get_rx_ss(hw);
if (level_num == 2) {
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
rtlpriv->btcoexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)){
if (smooth >=
if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to High\n");
} else {
@ -259,12 +260,12 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
"[DM][BT], RSSI state stay at Low\n");
}
} else {
if (smooth < rssi_thresh) {
if (undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->bt_coexist.cstate |=
BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->bt_coexist.cstate &=
~BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to Low\n");
} else {
@ -277,20 +278,20 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
if (rssi_thresh > rssi_thresh1) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI thresh error!!\n");
return rtlpcipriv->bt_coexist.bt_pre_rssi_state;
return rtlpriv->btcoexist.bt_pre_rssi_state;
}
if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (smooth >=
if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_LOW) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_LOW)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to Medium\n");
@ -299,28 +300,28 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state stay at Low\n");
}
} else if ((rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_MEDIUM) ||
(rtlpcipriv->bt_coexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_MEDIUM)) {
if (smooth >=
} else if ((rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_MEDIUM) ||
(rtlpriv->btcoexist.bt_pre_rssi_state ==
BT_RSSI_STATE_STAY_MEDIUM)) {
if (undecoratedsmoothed_pwdb >=
(rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to High\n");
} else if (smooth < rssi_thresh) {
} else if (undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to Low\n");
@ -330,13 +331,13 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
"[DM][BT], RSSI state stay at Medium\n");
}
} else {
if (smooth < rssi_thresh1) {
if (undecoratedsmoothed_pwdb < rssi_thresh1) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
|= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->bt_coexist.cstate
rtlpriv->btcoexist.cstate
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], RSSI state switch to Medium\n");
@ -347,31 +348,32 @@ u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
}
}
}
rtlpcipriv->bt_coexist.bt_pre_rssi_state = bt_rssi_state;
rtlpriv->btcoexist.bt_pre_rssi_state = bt_rssi_state;
return bt_rssi_state;
}
long rtl8723ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw)
long rtl8723e_dm_bt_get_rx_ss(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
long smooth = 0;
if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
smooth = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
else
smooth = rtlpriv->dm.entry_min_undec_sm_pwdb;
long undecoratedsmoothed_pwdb = 0;
if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
undecoratedsmoothed_pwdb =
GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
} else {
undecoratedsmoothed_pwdb
= rtlpriv->dm.entry_min_undec_sm_pwdb;
}
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_get_rx_ss() = %ld\n", smooth);
"rtl8723e_dm_bt_get_rx_ss() = %ld\n",
undecoratedsmoothed_pwdb);
return smooth;
return undecoratedsmoothed_pwdb;
}
void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw,
bool balance_on, u8 ms0, u8 ms1)
void rtl8723e_dm_bt_balance(struct ieee80211_hw *hw,
bool balance_on, u8 ms0, u8 ms1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 h2c_parameter[3] = {0};
@ -379,27 +381,26 @@ void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw,
h2c_parameter[2] = 1;
h2c_parameter[1] = ms1;
h2c_parameter[0] = ms0;
rtlpcipriv->bt_coexist.fw_coexist_all_off = false;
rtlpriv->btcoexist.fw_coexist_all_off = false;
} else {
h2c_parameter[2] = 0;
h2c_parameter[1] = 0;
h2c_parameter[0] = 0;
}
rtlpcipriv->bt_coexist.balance_on = balance_on;
rtlpriv->btcoexist.balance_on = balance_on;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
balance_on ? "ON" : "OFF", ms0, ms1,
h2c_parameter[0]<<16 | h2c_parameter[1]<<8 | h2c_parameter[2]);
balance_on ? "ON" : "OFF", ms0, ms1, h2c_parameter[0]<<16 |
h2c_parameter[1]<<8 | h2c_parameter[2]);
rtl8723ae_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter);
rtl8723e_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter);
}
void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
void rtl8723e_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if (type == BT_AGCTABLE_OFF) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@ -410,15 +411,15 @@ void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
rtl_write_dword(rtlpriv, 0xc78, 0x611f0001);
rtl_write_dword(rtlpriv, 0xc78, 0x60200001);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x32000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x71000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xb0000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xfc000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x30355);
} else if (type == BT_AGCTABLE_ON) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@ -429,25 +430,24 @@ void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
rtl_write_dword(rtlpriv, 0xc78, 0x4b1f0001);
rtl_write_dword(rtlpriv, 0xc78, 0x4a200001);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xdc000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x90000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x51000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x12000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
rtl8723e_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x00355);
rtlpcipriv->bt_coexist.sw_coexist_all_off = false;
rtlpriv->btcoexist.sw_coexist_all_off = false;
}
}
void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type)
void rtl8723e_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if (type == BT_BB_BACKOFF_OFF) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
@ -457,87 +457,81 @@ void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type)
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[BT]BBBackOffLevel On!\n");
rtl_write_dword(rtlpriv, 0xc04, 0x3a07611);
rtlpcipriv->bt_coexist.sw_coexist_all_off = false;
rtlpriv->btcoexist.sw_coexist_all_off = false;
}
}
void rtl8723ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw)
void rtl8723e_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_fw_coex_all_off()\n");
"rtl8723e_dm_bt_fw_coex_all_off()\n");
if (rtlpcipriv->bt_coexist.fw_coexist_all_off)
if (rtlpriv->btcoexist.fw_coexist_all_off)
return;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_fw_coex_all_off(), real Do\n");
rtl8723ae_dm_bt_fw_coex_all_off_8723a(hw);
rtlpcipriv->bt_coexist.fw_coexist_all_off = true;
"rtl8723e_dm_bt_fw_coex_all_off(), real Do\n");
rtl8723e_dm_bt_fw_coex_all_off_8723a(hw);
rtlpriv->btcoexist.fw_coexist_all_off = true;
}
void rtl8723ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw)
void rtl8723e_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_sw_coex_all_off()\n");
"rtl8723e_dm_bt_sw_coex_all_off()\n");
if (rtlpcipriv->bt_coexist.sw_coexist_all_off)
if (rtlpriv->btcoexist.sw_coexist_all_off)
return;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_sw_coex_all_off(), real Do\n");
rtl8723ae_dm_bt_sw_coex_all_off_8723a(hw);
rtlpcipriv->bt_coexist.sw_coexist_all_off = true;
"rtl8723e_dm_bt_sw_coex_all_off(), real Do\n");
rtl8723e_dm_bt_sw_coex_all_off_8723a(hw);
rtlpriv->btcoexist.sw_coexist_all_off = true;
}
void rtl8723ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw)
void rtl8723e_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_hw_coex_all_off()\n");
"rtl8723e_dm_bt_hw_coex_all_off()\n");
if (rtlpcipriv->bt_coexist.hw_coexist_all_off)
if (rtlpriv->btcoexist.hw_coexist_all_off)
return;
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"rtl8723ae_dm_bt_hw_coex_all_off(), real Do\n");
"rtl8723e_dm_bt_hw_coex_all_off(), real Do\n");
rtl8723ae_dm_bt_hw_coex_all_off_8723a(hw);
rtl8723e_dm_bt_hw_coex_all_off_8723a(hw);
rtlpcipriv->bt_coexist.hw_coexist_all_off = true;
rtlpriv->btcoexist.hw_coexist_all_off = true;
}
void rtl8723ae_btdm_coex_all_off(struct ieee80211_hw *hw)
void rtl8723e_btdm_coex_all_off(struct ieee80211_hw *hw)
{
rtl8723ae_dm_bt_fw_coex_all_off(hw);
rtl8723ae_dm_bt_sw_coex_all_off(hw);
rtl8723ae_dm_bt_hw_coex_all_off(hw);
rtl8723e_dm_bt_fw_coex_all_off(hw);
rtl8723e_dm_bt_sw_coex_all_off(hw);
rtl8723e_dm_bt_hw_coex_all_off(hw);
}
bool rtl8723ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw)
bool rtl8723e_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
if ((rtlpcipriv->bt_coexist.previous_state ==
rtlpcipriv->bt_coexist.cstate) &&
(rtlpcipriv->bt_coexist.previous_state_h ==
rtlpcipriv->bt_coexist.cstate_h))
if ((rtlpriv->btcoexist.previous_state == rtlpriv->btcoexist.cstate) &&
(rtlpriv->btcoexist.previous_state_h ==
rtlpriv->btcoexist.cstate_h))
return false;
else
return true;
return true;
}
bool rtl8723ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw)
bool rtl8723e_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (rtlpriv->link_info.tx_busy_traffic)
return true;
else
return false;
return false;
}

38
drivers/net/wireless/rtlwifi/rtl8723ae/hal_bt_coexist.h
View File

@ -53,8 +53,8 @@
#define BT_COEX_STATE_WIFI_LEGACY BIT(3)
#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
#define BT_COEX_STATE_DEC_BT_POWER BIT(7)
#define BT_COEX_STATE_WIFI_IDLE BIT(8)
@ -78,7 +78,7 @@
#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25)
#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26)
#define BT_COEX_STATE_BTINFO_COMMON BIT(30)
#define BT_COEX_STATE_BTINFO_COMMON BIT(30)
#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31)
#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29)
@ -133,28 +133,26 @@
#define BTINFO_B_SCO_ESCO BIT(1)
#define BTINFO_B_CONNECTION BIT(0)
void rtl8723e_btdm_coex_all_off(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw);
void rtl8723ae_btdm_coex_all_off(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
long rtl8723ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_balance(struct ieee80211_hw *hw,
void rtl8723e_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
long rtl8723e_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_balance(struct ieee80211_hw *hw,
bool balance_on, u8 ms0, u8 ms1);
void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type);
void rtl8723ae_dm_bt_bback_off_level(struct ieee80211_hw *hw, u8 type);
u8 rtl8723ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
void rtl8723e_dm_bt_agc_table(struct ieee80211_hw *hw, u8 tyep);
void rtl8723e_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type);
u8 rtl8723e_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rssi_thresh1);
u8 rtl8723ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rtl8723e_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh,
u8 rssi_thresh1);
void _rtl8723_dm_bt_check_wifi_state(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
bool reject);
bool rtl8723ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw);
bool rtl8723ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
bool b_reject);
bool rtl8723e_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw);
bool rtl8723e_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
#endif

1226
drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.c
View File

File diff suppressed because it is too large Load Diff

66
drivers/net/wireless/rtlwifi/rtl8723ae/hal_btc.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -24,8 +20,7 @@
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
****************************************************************************
*/
*****************************************************************************/
#ifndef __RTL8723E_HAL_BTC_H__
#define __RTL8723E_HAL_BTC_H__
@ -34,21 +29,31 @@
#include "btc.h"
#include "hal_bt_coexist.h"
#define BT_TXRX_CNT_THRES_1 1200
#define BT_TXRX_CNT_THRES_2 1400
#define BT_TXRX_CNT_THRES_3 3000
#define BT_TXRX_CNT_LEVEL_0 0 /* < 1200 */
#define BT_TXRX_CNT_LEVEL_1 1 /* >= 1200 && < 1400 */
#define BT_TXRX_CNT_LEVEL_2 2 /* >= 1400 */
#define BT_TXRX_CNT_LEVEL_3 3
#define BT_TXRX_CNT_THRES_1 1200
#define BT_TXRX_CNT_THRES_2 1400
#define BT_TXRX_CNT_THRES_3 3000
/* < 1200 */
#define BT_TXRX_CNT_LEVEL_0 0
/* >= 1200 && < 1400 */
#define BT_TXRX_CNT_LEVEL_1 1
/* >= 1400 */
#define BT_TXRX_CNT_LEVEL_2 2
#define BT_TXRX_CNT_LEVEL_3 3
#define BT_COEX_DISABLE 0
#define BT_Q_PKT_OFF 0
#define BT_Q_PKT_ON 1
#define BT_TX_PWR_OFF 0
#define BT_TX_PWR_ON 1
/* TDMA mode definition */
#define TDMA_2ANT 0
#define TDMA_1ANT 1
#define TDMA_NAV_OFF 0
#define TDMA_NAV_ON 1
#define TDMA_DAC_SWING_OFF 0
#define TDMA_DAC_SWING_ON 1
#define TDMA_2ANT 0
#define TDMA_1ANT 1
#define TDMA_NAV_OFF 0
#define TDMA_NAV_ON 1
#define TDMA_DAC_SWING_OFF 0
#define TDMA_DAC_SWING_ON 1
/* PTA mode related definition */
#define BT_PTA_MODE_OFF 0
@ -80,6 +85,7 @@ enum bt_traffic_mode_profile {
BT_PROFILE_SCO
};
/*
enum hci_ext_bt_operation {
HCI_BT_OP_NONE = 0x0,
HCI_BT_OP_INQUIRE_START = 0x1,
@ -93,6 +99,7 @@ enum hci_ext_bt_operation {
HCI_BT_OP_BT_DEV_DISABLE = 0x9,
HCI_BT_OP_MAX,
};
*/
enum bt_spec {
BT_SPEC_1_0_b = 0x00,
@ -123,12 +130,12 @@ enum bt_state {
BT_INFO_STATE_MAX = 7
};
enum rtl8723ae_c2h_evt {
enum rtl8723e_c2h_evt {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3, /* The FW notify the report of the specific */
/* tx packet. */
/* The FW notify the report of the specific tx packet. */
C2H_CCX_TX_RPT = 3,
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_HW_INFO_EXCH = 10,
@ -137,15 +144,16 @@ enum rtl8723ae_c2h_evt {
MAX_C2HEVENT
};
void rtl8723ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_coexist_8723(struct ieee80211_hw *hw);
void rtl8723ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw,
void rtl8723e_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_coexist_8723(struct ieee80211_hw *hw);
void rtl8723e_dm_bt_set_bt_dm(struct ieee80211_hw *hw,
struct btdm_8723 *p_btdm);
void rtl_8723e_c2h_command_handle(struct ieee80211_hw *hw);
void rtl_8723e_bt_wifi_media_status_notify(struct ieee80211_hw *hw,
bool mstatus);
void rtl8723ae_bt_coex_off_before_lps(struct ieee80211_hw *hw);
bool mstatus);
void rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps(
struct ieee80211_hw *hw);
#endif

1530
drivers/net/wireless/rtlwifi/rtl8723ae/hw.c
View File

File diff suppressed because it is too large Load Diff

66
drivers/net/wireless/rtlwifi/rtl8723ae/hw.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -34,38 +30,38 @@
((rtlefuse->eeprom_svid == (_val1)) && \
(rtlefuse->eeprom_smid == (_val2)))
void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw);
void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw);
void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw,
u32 *p_inta, u32 *p_intb);
int rtl8723ae_hw_init(struct ieee80211_hw *hw);
void rtl8723ae_card_disable(struct ieee80211_hw *hw);
void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw);
void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw);
int rtl8723ae_set_network_type(struct ieee80211_hw *hw,
enum nl80211_iftype type);
void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci);
void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw);
void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw);
void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw,
u32 add_msr, u32 rm_msr);
void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u8 rssi_level);
void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw);
bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw);
void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index,
u8 *p_macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
u32 *p_inta, u32 *p_intb);
int rtl8723e_hw_init(struct ieee80211_hw *hw);
void rtl8723e_card_disable(struct ieee80211_hw *hw);
void rtl8723e_enable_interrupt(struct ieee80211_hw *hw);
void rtl8723e_disable_interrupt(struct ieee80211_hw *hw);
int rtl8723e_set_network_type(struct ieee80211_hw *hw,
enum nl80211_iftype type);
void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci);
void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw);
void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw);
void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
u32 add_msr, u32 rm_msr);
void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u8 rssi_level);
void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw);
bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw);
void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
u8 *p_macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
bool autoload_fail, u8 *hwinfo);
void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw);
void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw);
void rtl8723ae_suspend(struct ieee80211_hw *hw);
void rtl8723ae_resume(struct ieee80211_hw *hw);
void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
bool autoload_fail, u8 *hwinfo);
void rtl8723e_bt_reg_init(struct ieee80211_hw *hw);
void rtl8723e_bt_hw_init(struct ieee80211_hw *hw);
void rtl8723e_suspend(struct ieee80211_hw *hw);
void rtl8723e_resume(struct ieee80211_hw *hw);
#endif

54
drivers/net/wireless/rtlwifi/rtl8723ae/led.c
View File

@ -32,44 +32,44 @@
#include "reg.h"
#include "led.h"
static void _rtl8723ae_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled, enum rtl_led_pin ledpin)
static void _rtl8723e_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled, enum rtl_led_pin ledpin)
{
pled->hw = hw;
pled->ledpin = ledpin;
pled->ledon = false;
}
void rtl8723ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv,
REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
break;
case LED_PIN_LED1:
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
"switch case not process\n");
break;
}
pled->ledon = true;
}
void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
@ -86,7 +86,7 @@ void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
case LED_PIN_LED0:
ledcfg &= 0xf0;
if (pcipriv->ledctl.led_opendrain) {
ledcfg &= 0x90;
ledcfg &= 0x90; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
ledcfg &= 0xFE;
@ -94,50 +94,51 @@ void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
} else {
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg | BIT(3) | BIT(5)));
(ledcfg | BIT(3) | BIT(5)));
}
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1) & 0x10;
rtl_write_byte(rtlpriv, REG_LEDCFG1, (ledcfg | BIT(3)));
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
ledcfg &= 0x10; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
"switch case not process\n");
break;
}
pled->ledon = false;
}
void rtl8723ae_init_sw_leds(struct ieee80211_hw *hw)
void rtl8723e_init_sw_leds(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
_rtl8723ae_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
_rtl8723ae_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
_rtl8723e_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
_rtl8723e_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void _rtl8723ae_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
static void _rtl8723e_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
rtl8723ae_sw_led_on(hw, pLed0);
rtl8723e_sw_led_on(hw, pLed0);
break;
case LED_CTL_POWER_OFF:
rtl8723ae_sw_led_off(hw, pLed0);
rtl8723e_sw_led_off(hw, pLed0);
break;
default:
break;
}
}
void rtl8723ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
void rtl8723e_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
@ -152,6 +153,7 @@ void rtl8723ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
ledaction == LED_CTL_POWER_ON)) {
return;
}
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n", ledaction);
_rtl8723ae_sw_led_control(hw, ledaction);
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, "ledaction %d,\n",
ledaction);
_rtl8723e_sw_led_control(hw, ledaction);
}

13
drivers/net/wireless/rtlwifi/rtl8723ae/led.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -30,10 +26,9 @@
#ifndef __RTL92CE_LED_H__
#define __RTL92CE_LED_H__
void rtl8723ae_init_sw_leds(struct ieee80211_hw *hw);
void rtl8723ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8723ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8723ae_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction);
void rtl8723e_init_sw_leds(struct ieee80211_hw *hw);
void rtl8723e_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8723e_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8723e_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif

892
drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
View File

File diff suppressed because it is too large Load Diff

67
drivers/net/wireless/rtlwifi/rtl8723ae/phy.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -39,6 +35,7 @@
#define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1
@ -49,12 +46,15 @@
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50
#define AntennaDiversityValue 0x80
#define ANTENNADIVERSITYVALUE 0x80
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_ADDA_REG_NUM 16
#define IQK_MAC_REG_NUM 4
#define IQK_DELAY_TIME 1
#define RF6052_MAX_PATH 2
#define CT_OFFSET_MAC_ADDR 0X16
@ -166,36 +166,37 @@ struct tx_power_struct {
u32 mcs_original_offset[4][16];
};
u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask);
void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask, u32 data);
bool rtl8723ae_phy_mac_config(struct ieee80211_hw *hw);
bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw);
bool rtl8723ae_phy_rf_config(struct ieee80211_hw *hw);
u32 bitmask);
void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask, u32 data);
bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw);
bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw);
bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw);
bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
void rtl8723ae_phy_set_txpower_level(struct ieee80211_hw *hw,
u8 channel);
bool rtl8723ae_phy_update_txpower_dbm(struct ieee80211_hw *hw,
long power_indbm);
void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
void rtl8723ae_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
void rtl8723ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl8723ae_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery);
void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl8723ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl8723ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8723ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl8723ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state);
void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw,
long power_indbm);
void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw,
u8 operation);
void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state);
#endif

91
drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -30,80 +26,87 @@
#include "../pwrseqcmd.h"
#include "pwrseq.h"
/* drivers should parse arrays below and do the corresponding actions */
/* drivers should parse below arrays and do the corresponding actions */
/*3 Power on Array*/
struct wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_CARDEMU_TO_ACT,
struct wlan_pwr_cfg rtl8723A_power_on_flow
[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/*3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU,
struct wlan_pwr_cfg rtl8723A_radio_off_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_END
};
/*3Card Disable Array*/
struct wlan_pwr_cfg
rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU,
RTL8723A_TRANS_CARDEMU_TO_CARDDIS,
struct wlan_pwr_cfg rtl8723A_card_disable_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_CARDDIS
RTL8723A_TRANS_END
};
/*3 Card Enable Array*/
struct wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_CARDDIS_TO_CARDEMU,
RTL8723A_TRANS_CARDEMU_TO_ACT,
struct wlan_pwr_cfg rtl8723A_card_enable_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_CARDDIS_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/*3Suspend Array*/
struct wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU,
RTL8723A_TRANS_CARDEMU_TO_SUS,
struct wlan_pwr_cfg rtl8723A_suspend_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_SUS
RTL8723A_TRANS_END
};
/*3 Resume Array*/
struct wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_SUS_TO_CARDEMU,
RTL8723A_TRANS_CARDEMU_TO_ACT,
struct wlan_pwr_cfg rtl8723A_resume_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_SUS_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_ACT
RTL8723A_TRANS_END
};
/*3HWPDN Array*/
struct wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU,
RTL8723A_TRANS_CARDEMU_TO_PDN,
struct wlan_pwr_cfg rtl8723A_hwpdn_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS] = {
RTL8723A_TRANS_ACT_TO_CARDEMU
RTL8723A_TRANS_CARDEMU_TO_PDN
RTL8723A_TRANS_END
};
/*3 Enter LPS */
struct wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS
+ RTL8723A_TRANS_END_STPS] = {
struct wlan_pwr_cfg rtl8723A_enter_lps_flow
[RTL8723A_TRANS_ACT_TO_LPS_STEPS +
RTL8723A_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8723A_TRANS_ACT_TO_LPS,
RTL8723A_TRANS_ACT_TO_LPS
RTL8723A_TRANS_END
};
/*3 Leave LPS */
struct wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS
+ RTL8723A_TRANS_END_STPS] = {
struct wlan_pwr_cfg rtl8723A_leave_lps_flow
[RTL8723A_TRANS_LPS_TO_ACT_STEPS +
RTL8723A_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8723A_TRANS_LPS_TO_ACT,
RTL8723A_TRANS_LPS_TO_ACT
RTL8723A_TRANS_END
};

543
drivers/net/wireless/rtlwifi/rtl8723ae/pwrseq.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -30,282 +26,305 @@
#ifndef __RTL8723E_PWRSEQ_H__
#define __RTL8723E_PWRSEQ_H__
#include "../pwrseqcmd.h"
/*
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
* Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
* There are 6 HW Power States:
* 0: POFF--Power Off
* 1: PDN--Power Down
* 2: CARDEMU--Card Emulation
* 3: ACT--Active Mode
* 4: LPS--Low Power State
* 5: SUS--Suspend
*
* The transision from different states are defined below
* TRANS_CARDEMU_TO_ACT
* TRANS_ACT_TO_CARDEMU
* TRANS_CARDEMU_TO_SUS
* TRANS_SUS_TO_CARDEMU
* TRANS_CARDEMU_TO_PDN
* TRANS_ACT_TO_LPS
* TRANS_LPS_TO_ACT
*
* TRANS_END
*/
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8723A_TRANS_END_STEPS 1
TRANS_END
*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }*/
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STPS 10
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STPS 10
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STPS 10
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STPS 10
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STPS 10
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STPS 10
#define RTL8723A_TRANS_ACT_TO_LPS_STPS 15
#define RTL8723A_TRANS_LPS_TO_ACT_STPS 15
#define RTL8723A_TRANS_END_STPS 1
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* disable SW LPS 0x04[10]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
/* release WLON reset 0x04[16]=1*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
* comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0}, \
/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/*0x1F[7:0] = 0 turn off RF*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
* comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
/*0x1F[7:0] = 0 turn off RF*/ \
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, \
* comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), \
(BIT(4)|BIT(3))}, \
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | \
PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)}, \
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, \
PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, \
PWR_CMD_POLLING, BIT(1), 0} \
/*wait power state to suspend*/
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK| \
PWR_INTF_SDIO_MSK,\
PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, \
BIT(3)|BIT(4), BIT(3)}, \
/*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT(3)|BIT(4), \
BIT(3)|BIT(4)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_POLLING, BIT(1), 0},
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*wait power state to suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0} \
/*0x04[12:11] = 2b'01enable WL suspend*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)},\
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
/*0x04[10] = 1, enable SW LPS*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0} \
/*wait power state to suspend*/
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
/*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*wait power state to suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
/*0x04[12:11] = 2b'00enable WL suspend*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0} \
/*PCIe DMA start*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)} \
/* 0x04[15] = 1*/
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
/*0x04[10] = 1, enable SW LPS*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(2), BIT(2)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_POLLING, BIT(1), 0},
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0} \
/* 0x04[15] = 0*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F}, \
/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F}, \
/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)} \
/*Respond TxOK to scheduler*/
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU\
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_WRITE, BIT(0), 0}, \
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_POLLING, BIT(1), BIT(1)},\
/*0x04[12:11] = 2b'00enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
/*PCIe DMA start*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0},
#define RTL8723A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
/*SDIO RPWM*/ \
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
/*USB RPWM*/ \
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
/*PCIe RPWM*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
/*Delay*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
/* 0x08[4] = 0 switch TSF to 40M*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
/*Polling 0x109[7]=0 TSF in 40M*/ \
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
/*. 0x29[7:6] = 2b'00 enable BB clock*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
/*. 0x101[1] = 1*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
/* 0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), \
BIT(1)|BIT(0)}, \
/* 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0} \
/*. 0x522 = 0*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
#define RTL8723A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_ACT_TO_LPS \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
/*Should be zero if no packet is transmitting*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_POLLING, 0xFF, 0},\
/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_POLLING, 0xFF, 0},\
/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_POLLING, 0xFF, 0},\
/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_POLLING, 0xFF, 0},\
/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(0), 0},\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
/*Respond TxOK to scheduler*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(5), BIT(5)},\
#define RTL8723A_TRANS_LPS_TO_ACT\
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
/*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(4), 0}, \
/*Polling 0x109[7]=0 TSF in 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_POLLING, BIT(7), 0}, \
/*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
/*. 0x101[1] = 1*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(1), BIT(1)},\
/*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0xFF},\
/*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
/* format */
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */
#define RTL8723A_TRANS_END \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0, PWR_CMD_END, 0, 0}
extern struct
wlan_pwr_cfg rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_SUS_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STPS
+ RTL8723A_TRANS_CARDEMU_TO_PDN_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct
wlan_pwr_cfg rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STPS
+ RTL8723A_TRANS_END_STPS];
extern struct wlan_pwr_cfg rtl8723A_power_on_flow
[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_radio_off_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_card_disable_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_card_enable_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_suspend_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_resume_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_hwpdn_flow
[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_enter_lps_flow
[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8723A_leave_lps_flow
[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
/* RTL8723 Power Configuration CMDs for PCIe interface */
#define Rtl8723_NIC_PWR_ON_FLOW rtl8723A_power_on_flow

2600
drivers/net/wireless/rtlwifi/rtl8723ae/reg.h
View File

File diff suppressed because it is too large Load Diff

261
drivers/net/wireless/rtlwifi/rtl8723ae/rf.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -34,10 +30,12 @@
#include "rf.h"
#include "dm.h"
void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
switch (bandwidth) {
case HT_CHANNEL_WIDTH_20:
@ -59,11 +57,11 @@ void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
}
}
void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel)
void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u32 tx_agc[2] = {0, 0}, tmpval;
@ -79,7 +77,8 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
if (turbo_scanoff) {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B;
idx1++) {
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
@ -89,24 +88,27 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
} else {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
}
if (rtlefuse->eeprom_regulatory == 0) {
tmpval = (rtlphy->mcs_offset[0][6]) +
(rtlphy->mcs_offset[0][7] << 8);
tmpval =
(rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
8);
tx_agc[RF90_PATH_A] += tmpval;
tmpval = (rtlphy->mcs_offset[0][14]) +
(rtlphy->mcs_offset[0][15] << 24);
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
24);
tx_agc[RF90_PATH_B] += tmpval;
}
}
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
ptr = (u8 *) (&(tx_agc[idx1]));
ptr = (u8 *)&tx_agc[idx1];
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
@ -119,7 +121,7 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_A_CCK1_MCS32);
RTXAGC_A_CCK1_MCS32);
tmpval = tx_agc[RF90_PATH_A] >> 8;
@ -129,100 +131,99 @@ void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11);
RTXAGC_B_CCK11_A_CCK2_11);
tmpval = tx_agc[RF90_PATH_B] >> 24;
rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11);
RTXAGC_B_CCK11_A_CCK2_11);
tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK1_55_MCS32);
RTXAGC_B_CCK1_55_MCS32);
}
static void rtl8723ae_phy_get_power_base(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel,
u32 *ofdmbase, u32 *mcsbase)
static void rtl8723e_phy_get_power_base(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel,
u32 *ofdmbase, u32 *mcsbase)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u32 powerBase0, powerBase1;
u32 powerbase0, powerbase1;
u8 legacy_pwrdiff, ht20_pwrdiff;
u8 i, powerlevel[2];
for (i = 0; i < 2; i++) {
powerlevel[i] = ppowerlevel[i];
legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
powerBase0 = powerlevel[i] + legacy_pwrdiff;
powerbase0 = powerlevel[i] + legacy_pwrdiff;
powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
(powerBase0 << 8) | powerBase0;
*(ofdmbase + i) = powerBase0;
powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
(powerbase0 << 8) | powerbase0;
*(ofdmbase + i) = powerbase0;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
" [OFDM power base index rf(%c) = 0x%x]\n",
((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
}
for (i = 0; i < 2; i++) {
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
ht20_pwrdiff =
rtlefuse->txpwr_ht20diff[i][channel - 1];
powerlevel[i] += ht20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1 << 24) |
(powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
powerbase1 = powerlevel[i];
powerbase1 = (powerbase1 << 24) |
(powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
*(mcsbase + i) = powerBase1;
*(mcsbase + i) = powerbase1;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
" [MCS power base index rf(%c) = 0x%x]\n",
((i == 0) ? 'A' : 'B'), *(mcsbase + i));
((i == 0) ? 'A' : 'B'), *(mcsbase + i));
}
}
static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
u8 channel, u8 index,
u32 *powerBase0,
u32 *powerBase1,
u32 *p_outwriteval)
static void get_txpower_writeval_by_reg(struct ieee80211_hw *hw,
u8 channel, u8 index,
u32 *powerbase0,
u32 *powerbase1,
u32 *p_outwriteval)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u8 i, chnlgroup = 0, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
u32 writeval, customer_limit, rf;
for (rf = 0; rf < 2; rf++) {
switch (rtlefuse->eeprom_regulatory) {
case 0:
chnlgroup = 0;
writeVal = rtlphy->mcs_offset[chnlgroup]
[index + (rf ? 8 : 0)] +
((index < 2) ? powerBase0[rf] :
powerBase1[rf]);
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
(rf ? 8 : 0)]
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, "
"writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"RTK better performance, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
case 1:
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
writeVal = ((index < 2) ? powerBase0[rf] :
powerBase1[rf]);
writeval = ((index < 2) ? powerbase0[rf] :
powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Realtek regulatory, 40MHz, "
"writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"Realtek regulatory, 40MHz, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
} else {
if (rtlphy->pwrgroup_cnt == 1)
chnlgroup = 0;
@ -234,29 +235,30 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
else if (channel > 9)
chnlgroup = 2;
if (rtlphy->current_chan_bw ==
HT_CHANNEL_WIDTH_20)
HT_CHANNEL_WIDTH_20)
chnlgroup++;
else
chnlgroup += 4;
}
writeVal = rtlphy->mcs_offset[chnlgroup]
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)] + ((index < 2) ?
powerBase0[rf] :
powerBase1[rf]);
powerbase0[rf] :
powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
}
break;
case 2:
writeVal =
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
writeval =
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Better regulatory, writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"Better regulatory, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
case 3:
chnlgroup = 0;
@ -265,18 +267,21 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 40MHz rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht40[rf][channel-1]);
rtlefuse->pwrgroup_ht40[rf][channel -
1]);
} else {
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 20MHz rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht20[rf][channel-1]);
rtlefuse->pwrgroup_ht20[rf][channel -
1]);
}
for (i = 0; i < 4; i++) {
pwr_diff_limit[i] =
(u8) ((rtlphy->mcs_offset
[chnlgroup][index + (rf ? 8 : 0)] &
(0x7f << (i * 8))) >> (i * 8));
(u8)((rtlphy->mcs_txpwrlevel_origoffset
[chnlgroup][index +
(rf ? 8 : 0)] & (0x7f <<
(i * 8))) >> (i * 8));
if (rtlphy->current_chan_bw ==
HT_CHANNEL_WIDTH_20_40) {
@ -302,41 +307,42 @@ static void rtl8723ae_get_txpwr_val_by_reg(struct ieee80211_hw *hw,
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Customer's limit rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), customer_limit);
((rf == 0) ? 'A' : 'B'), customer_limit);
writeVal = customer_limit +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
writeval = customer_limit +
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Customer, writeVal rf(%c)= 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"Customer, writeval rf(%c)= 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
default:
chnlgroup = 0;
writeVal = rtlphy->mcs_offset[chnlgroup][index +
(rf ? 8 : 0)] + ((index < 2) ? powerBase0[rf] :
powerBase1[rf]);
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)]
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, writeVal rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal);
"RTK better performance, writeval rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
}
if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
writeVal = writeVal - 0x06060606;
writeval = writeval - 0x06060606;
else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
TXHIGHPWRLEVEL_BT2)
writeVal = writeVal - 0x0c0c0c0c;
*(p_outwriteval + rf) = writeVal;
writeval = writeval - 0x0c0c0c0c;
*(p_outwriteval + rf) = writeval;
}
}
static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
u8 index, u32 *pValue)
static void _rtl8723e_write_ofdm_power_reg(struct ieee80211_hw *hw,
u8 index, u32 *pvalue)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
u16 regoffset_a[6] = {
RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
@ -349,29 +355,29 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
};
u8 i, rf, pwr_val[4];
u32 writeVal;
u32 writeval;
u16 regoffset;
for (rf = 0; rf < 2; rf++) {
writeVal = pValue[rf];
writeval = pvalue[rf];
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8) ((writeVal & (0x7f <<
(i * 8))) >> (i * 8));
pwr_val[i] = (u8)((writeval & (0x7f <<
(i * 8))) >> (i * 8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
(pwr_val[1] << 8) | pwr_val[0];
if (rf == 0)
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Set 0x%x = %08x\n", regoffset, writeVal);
"Set 0x%x = %08x\n", regoffset, writeval);
if (((get_rf_type(rtlphy) == RF_2T2R) &&
(regoffset == RTXAGC_A_MCS15_MCS12 ||
@ -380,7 +386,7 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
(regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_B_MCS07_MCS04))) {
writeVal = pwr_val[3];
writeval = pwr_val[3];
if (regoffset == RTXAGC_A_MCS15_MCS12 ||
regoffset == RTXAGC_A_MCS07_MCS04)
regoffset = 0xc90;
@ -389,37 +395,49 @@ static void _rtl8723ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
regoffset = 0xc98;
for (i = 0; i < 3; i++) {
writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
writeval = (writeval > 6) ? (writeval - 6) : 0;
rtl_write_byte(rtlpriv, (u32) (regoffset + i),
(u8) writeVal);
(u8)writeval);
}
}
}
}
void rtl8723ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel)
void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel)
{
u32 writeVal[2], powerBase0[2], powerBase1[2];
u32 writeval[2], powerbase0[2], powerbase1[2];
u8 index;
rtl8723ae_phy_get_power_base(hw, ppowerlevel,
channel, &powerBase0[0], &powerBase1[0]);
rtl8723e_phy_get_power_base(hw, ppowerlevel,
channel, &powerbase0[0], &powerbase1[0]);
for (index = 0; index < 6; index++) {
rtl8723ae_get_txpwr_val_by_reg(hw, channel, index,
&powerBase0[0],
&powerBase1[0],
&writeVal[0]);
get_txpower_writeval_by_reg(hw, channel, index, &powerbase0[0],
&powerbase1[0],
&writeval[0]);
_rtl8723ae_write_ofdm_power_reg(hw, index, &writeVal[0]);
_rtl8723e_write_ofdm_power_reg(hw, index, &writeval[0]);
}
}
static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_phy *rtlphy = &rtlpriv->phy;
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return _rtl8723e_phy_rf6052_config_parafile(hw);
}
static bool _rtl8723e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &rtlpriv->phy;
u32 u4_regvalue = 0;
u8 rfpath;
bool rtstatus = true;
@ -457,11 +475,12 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
switch (rfpath) {
case RF90_PATH_A:
rtstatus = rtl8723ae_phy_config_rf_with_headerfile(hw,
rtstatus = rtl8723e_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
case RF90_PATH_B:
rtstatus = rtl8723ae_phy_config_rf_with_headerfile(hw,
rtstatus =
rtl8723e_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
case RF90_PATH_C:
@ -469,6 +488,7 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
case RF90_PATH_D:
break;
}
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
@ -481,25 +501,14 @@ static bool _rtl8723ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
BRFSI_RFENV << 16, u4_regvalue);
break;
}
if (rtstatus != true) {
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"Radio[%d] Fail!!", rfpath);
return false;
}
}
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n");
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
return rtstatus;
}
bool rtl8723ae_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return _rtl8723ae_phy_rf6052_config_parafile(hw);
}

18
drivers/net/wireless/rtlwifi/rtl8723ae/rf.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -31,12 +27,14 @@
#define __RTL8723E_RF_H__
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
void rtl8723ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth);
void rtl8723ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel);
void rtl8723ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel);
bool rtl8723ae_phy_rf6052_config(struct ieee80211_hw *hw);
void rtl8723e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
u8 bandwidth);
void rtl8723e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel);
void rtl8723e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel);
bool rtl8723e_phy_rf6052_config(struct ieee80211_hw *hw);
#endif

216
drivers/net/wireless/rtlwifi/rtl8723ae/sw.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -28,34 +24,35 @@
*****************************************************************************/
#include "../wifi.h"
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "../core.h"
#include "../pci.h"
#include "../base.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "../rtl8723com/phy_common.h"
#include "dm.h"
#include "hw.h"
#include "fw.h"
#include "../rtl8723com/fw_common.h"
#include "hw.h"
#include "sw.h"
#include "trx.h"
#include "led.h"
#include "table.h"
#include "hal_btc.h"
#include "../btcoexist/rtl_btc.h"
#include "../rtl8723com/phy_common.h"
static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
#include <linux/vmalloc.h>
#include <linux/module.h>
static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw)
{
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
/*close ASPM for AMD defaultly */
rtlpci->const_amdpci_aspm = 0;
/* ASPM PS mode.
/**
* ASPM PS mode.
* 0 - Disable ASPM,
* 1 - Enable ASPM without Clock Req,
* 2 - Enable ASPM with Clock Req,
@ -71,7 +68,8 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
/*Setting for PCI-E bridge */
rtlpci->const_hostpci_aspm_setting = 0x02;
/* In Hw/Sw Radio Off situation.
/**
* In Hw/Sw Radio Off situation.
* 0 - Default,
* 1 - From ASPM setting without low Mac Pwr,
* 2 - From ASPM setting with low Mac Pwr,
@ -80,7 +78,8 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
*/
rtlpci->const_hwsw_rfoff_d3 = 0;
/* This setting works for those device with
/**
* This setting works for those device with
* backdoor ASPM setting such as EPHY setting.
* 0 - Not support ASPM,
* 1 - Support ASPM,
@ -89,14 +88,17 @@ static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
rtlpci->const_support_pciaspm = 1;
}
int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
int rtl8723e_init_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
int err;
int err = 0;
rtl8723e_bt_reg_init(hw);
rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
rtl8723ae_bt_reg_init(hw);
rtlpriv->dm.dm_initialgain_enable = 1;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.disable_framebursting = 0;
@ -138,7 +140,9 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
PHIMR_PSTIMEOUT |
0);
rtlpci->irq_mask[1] = (u32)(PHIMR_RXFOVW | 0);
rtlpci->irq_mask[1] =
(u32)(PHIMR_RXFOVW |
0);
/* for debug level */
rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
@ -146,12 +150,11 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
rtlpriv->psc.reg_fwctrl_lps = 3;
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
/* for ASPM, you can close aspm through
* set const_support_pciaspm = 0
*/
rtl8723ae_init_aspm_vars(hw);
rtl8723e_init_aspm_vars(hw);
if (rtlpriv->psc.reg_fwctrl_lps == 1)
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
@ -186,7 +189,7 @@ int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
return 0;
}
void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
@ -196,59 +199,69 @@ void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
}
}
static bool is_fw_header(struct rtl92c_firmware_header *hdr)
/* get bt coexist status */
bool rtl8723e_get_btc_status(void)
{
return true;
}
static bool is_fw_header(struct rtl8723e_firmware_header *hdr)
{
return (hdr->signature & 0xfff0) == 0x2300;
}
static struct rtl_hal_ops rtl8723ae_hal_ops = {
.init_sw_vars = rtl8723ae_init_sw_vars,
.deinit_sw_vars = rtl8723ae_deinit_sw_vars,
.read_eeprom_info = rtl8723ae_read_eeprom_info,
.interrupt_recognized = rtl8723ae_interrupt_recognized,
.hw_init = rtl8723ae_hw_init,
.hw_disable = rtl8723ae_card_disable,
.hw_suspend = rtl8723ae_suspend,
.hw_resume = rtl8723ae_resume,
.enable_interrupt = rtl8723ae_enable_interrupt,
.disable_interrupt = rtl8723ae_disable_interrupt,
.set_network_type = rtl8723ae_set_network_type,
.set_chk_bssid = rtl8723ae_set_check_bssid,
.set_qos = rtl8723ae_set_qos,
.set_bcn_reg = rtl8723ae_set_beacon_related_registers,
.set_bcn_intv = rtl8723ae_set_beacon_interval,
.update_interrupt_mask = rtl8723ae_update_interrupt_mask,
.get_hw_reg = rtl8723ae_get_hw_reg,
.set_hw_reg = rtl8723ae_set_hw_reg,
.update_rate_tbl = rtl8723ae_update_hal_rate_tbl,
.fill_tx_desc = rtl8723ae_tx_fill_desc,
.fill_tx_cmddesc = rtl8723ae_tx_fill_cmddesc,
.query_rx_desc = rtl8723ae_rx_query_desc,
.set_channel_access = rtl8723ae_update_channel_access_setting,
.radio_onoff_checking = rtl8723ae_gpio_radio_on_off_checking,
.set_bw_mode = rtl8723ae_phy_set_bw_mode,
.switch_channel = rtl8723ae_phy_sw_chnl,
.dm_watchdog = rtl8723ae_dm_watchdog,
.scan_operation_backup = rtl_phy_scan_operation_backup,
.set_rf_power_state = rtl8723ae_phy_set_rf_power_state,
.led_control = rtl8723ae_led_control,
.set_desc = rtl8723ae_set_desc,
.get_desc = rtl8723ae_get_desc,
.tx_polling = rtl8723ae_tx_polling,
.enable_hw_sec = rtl8723ae_enable_hw_security_config,
.set_key = rtl8723ae_set_key,
.init_sw_leds = rtl8723ae_init_sw_leds,
static struct rtl_hal_ops rtl8723e_hal_ops = {
.init_sw_vars = rtl8723e_init_sw_vars,
.deinit_sw_vars = rtl8723e_deinit_sw_vars,
.read_eeprom_info = rtl8723e_read_eeprom_info,
.interrupt_recognized = rtl8723e_interrupt_recognized,
.hw_init = rtl8723e_hw_init,
.hw_disable = rtl8723e_card_disable,
.hw_suspend = rtl8723e_suspend,
.hw_resume = rtl8723e_resume,
.enable_interrupt = rtl8723e_enable_interrupt,
.disable_interrupt = rtl8723e_disable_interrupt,
.set_network_type = rtl8723e_set_network_type,
.set_chk_bssid = rtl8723e_set_check_bssid,
.set_qos = rtl8723e_set_qos,
.set_bcn_reg = rtl8723e_set_beacon_related_registers,
.set_bcn_intv = rtl8723e_set_beacon_interval,
.update_interrupt_mask = rtl8723e_update_interrupt_mask,
.get_hw_reg = rtl8723e_get_hw_reg,
.set_hw_reg = rtl8723e_set_hw_reg,
.update_rate_tbl = rtl8723e_update_hal_rate_tbl,
.fill_tx_desc = rtl8723e_tx_fill_desc,
.fill_tx_cmddesc = rtl8723e_tx_fill_cmddesc,
.query_rx_desc = rtl8723e_rx_query_desc,
.set_channel_access = rtl8723e_update_channel_access_setting,
.radio_onoff_checking = rtl8723e_gpio_radio_on_off_checking,
.set_bw_mode = rtl8723e_phy_set_bw_mode,
.switch_channel = rtl8723e_phy_sw_chnl,
.dm_watchdog = rtl8723e_dm_watchdog,
.scan_operation_backup = rtl8723e_phy_scan_operation_backup,
.set_rf_power_state = rtl8723e_phy_set_rf_power_state,
.led_control = rtl8723e_led_control,
.set_desc = rtl8723e_set_desc,
.get_desc = rtl8723e_get_desc,
.is_tx_desc_closed = rtl8723e_is_tx_desc_closed,
.tx_polling = rtl8723e_tx_polling,
.enable_hw_sec = rtl8723e_enable_hw_security_config,
.set_key = rtl8723e_set_key,
.init_sw_leds = rtl8723e_init_sw_leds,
.get_bbreg = rtl8723_phy_query_bb_reg,
.set_bbreg = rtl8723_phy_set_bb_reg,
.get_rfreg = rtl8723ae_phy_query_rf_reg,
.set_rfreg = rtl8723ae_phy_set_rf_reg,
.get_rfreg = rtl8723e_phy_query_rf_reg,
.set_rfreg = rtl8723e_phy_set_rf_reg,
.c2h_command_handle = rtl_8723e_c2h_command_handle,
.bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
.bt_coex_off_before_lps = rtl8723ae_bt_coex_off_before_lps,
.bt_coex_off_before_lps =
rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps,
.get_btc_status = rtl8723e_get_btc_status,
.rx_command_packet = rtl8723e_rx_command_packet,
.is_fw_header = is_fw_header,
};
static struct rtl_mod_params rtl8723ae_mod_params = {
static struct rtl_mod_params rtl8723e_mod_params = {
.sw_crypto = false,
.inactiveps = true,
.swctrl_lps = false,
@ -256,13 +269,13 @@ static struct rtl_mod_params rtl8723ae_mod_params = {
.debug = DBG_EMERG,
};
static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
static struct rtl_hal_cfg rtl8723e_hal_cfg = {
.bar_id = 2,
.write_readback = true,
.name = "rtl8723ae_pci",
.fw_name = "rtlwifi/rtl8723fw.bin",
.ops = &rtl8723ae_hal_ops,
.mod_params = &rtl8723ae_mod_params,
.name = "rtl8723e_pci",
.fw_name = "rtlwifi/rtl8723efw.bin",
.ops = &rtl8723e_hal_ops,
.mod_params = &rtl8723e_mod_params,
.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
.maps[SYS_CLK] = REG_SYS_CLKR,
@ -271,6 +284,8 @@ static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
.maps[MAC_RCR_ACRC32] = ACRC32,
.maps[MAC_RCR_ACF] = ACF,
.maps[MAC_RCR_AAP] = AAP,
.maps[MAC_HIMR] = REG_HIMR,
.maps[MAC_HIMRE] = REG_HIMRE,
.maps[EFUSE_TEST] = REG_EFUSE_TEST,
.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
.maps[EFUSE_CLK] = 0,
@ -328,62 +343,63 @@ static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
.maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
.maps[RTL_IMR_VODOK] = PHIMR_VODOK,
.maps[RTL_IMR_ROK] = PHIMR_ROK,
.maps[RTL_IBSS_INT_MASKS] = (PHIMR_BCNDMAINT0 |
PHIMR_TXBCNOK | PHIMR_TXBCNERR),
.maps[RTL_IBSS_INT_MASKS] =
(PHIMR_BCNDMAINT0 | PHIMR_TXBCNOK | PHIMR_TXBCNERR),
.maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
.maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
.maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
.maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
.maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
.maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
.maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
.maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
.maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
.maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
.maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
.maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
.maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
.maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
.maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
.maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
.maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
.maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
.maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
.maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
.maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
.maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
.maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
.maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
.maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
.maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
.maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
};
static struct pci_device_id rtl8723ae_pci_ids[] = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723ae_hal_cfg)},
static struct pci_device_id rtl8723e_pci_ids[] = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723e_hal_cfg)},
{},
};
MODULE_DEVICE_TABLE(pci, rtl8723ae_pci_ids);
MODULE_DEVICE_TABLE(pci, rtl8723e_pci_ids);
MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
MODULE_FIRMWARE("rtlwifi/rtl8723fw.bin");
MODULE_FIRMWARE("rtlwifi/rtl8723fw_B.bin");
MODULE_FIRMWARE("rtlwifi/rtl8723efw.bin");
module_param_named(swenc, rtl8723ae_mod_params.sw_crypto, bool, 0444);
module_param_named(debug, rtl8723ae_mod_params.debug, int, 0444);
module_param_named(ips, rtl8723ae_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl8723ae_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl8723ae_mod_params.fwctrl_lps, bool, 0444);
module_param_named(swenc, rtl8723e_mod_params.sw_crypto, bool, 0444);
module_param_named(debug, rtl8723e_mod_params.debug, int, 0444);
module_param_named(ips, rtl8723e_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl8723e_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl8723e_mod_params.fwctrl_lps, bool, 0444);
module_param_named(disable_watchdog, rtl8723e_mod_params.disable_watchdog,
bool, 0444);
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
static struct pci_driver rtl8723ae_driver = {
static struct pci_driver rtl8723e_driver = {
.name = KBUILD_MODNAME,
.id_table = rtl8723ae_pci_ids,
.id_table = rtl8723e_pci_ids,
.probe = rtl_pci_probe,
.remove = rtl_pci_disconnect,
.driver.pm = &rtlwifi_pm_ops,
};
module_pci_driver(rtl8723ae_driver);
module_pci_driver(rtl8723e_driver);

12
drivers/net/wireless/rtlwifi/rtl8723ae/sw.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -30,8 +26,10 @@
#ifndef __RTL8723E_SW_H__
#define __RTL8723E_SW_H__
int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw);
void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw);
void rtl8723ae_init_var_map(struct ieee80211_hw *hw);
int rtl8723e_init_sw_vars(struct ieee80211_hw *hw);
void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw);
void rtl8723e_init_var_map(struct ieee80211_hw *hw);
bool rtl8723e_get_btc_status(void);
#endif

8
drivers/net/wireless/rtlwifi/rtl8723ae/table.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -335,7 +331,7 @@ u32 RTL8723EPHY_REG_ARRAY_PG[RTL8723E_PHY_REG_ARRAY_PGLENGTH] = {
0x868, 0xffffffff, 0x00000000,
};
u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH] = {
u32 RTL8723E_RADIOA_1TARRAY[RTL8723ERADIOA_1TARRAYLENGTH] = {
0x000, 0x00030159,
0x001, 0x00031284,
0x002, 0x00098000,
@ -479,12 +475,10 @@ u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH] = {
0x000, 0x00030159,
};
u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH] = {
0x0,
};
u32 RTL8723EMAC_ARRAY[RTL8723E_MACARRAYLENGTH] = {
0x420, 0x00000080,
0x423, 0x00000000,

8
drivers/net/wireless/rtlwifi/rtl8723ae/table.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -38,8 +34,8 @@
extern u32 RTL8723EPHY_REG_1TARRAY[RTL8723E_PHY_REG_1TARRAY_LENGTH];
#define RTL8723E_PHY_REG_ARRAY_PGLENGTH 336
extern u32 RTL8723EPHY_REG_ARRAY_PG[RTL8723E_PHY_REG_ARRAY_PGLENGTH];
#define Rtl8723ERADIOA_1TARRAYLENGTH 282
extern u32 RTL8723E_RADIOA_1TARRAY[Rtl8723ERADIOA_1TARRAYLENGTH];
#define RTL8723ERADIOA_1TARRAYLENGTH 282
extern u32 RTL8723E_RADIOA_1TARRAY[RTL8723ERADIOA_1TARRAYLENGTH];
#define RTL8723E_RADIOB_1TARRAYLENGTH 1
extern u32 RTL8723E_RADIOB_1TARRAY[RTL8723E_RADIOB_1TARRAYLENGTH];
#define RTL8723E_MACARRAYLENGTH 172

456
drivers/net/wireless/rtlwifi/rtl8723ae/trx.c
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -37,7 +33,7 @@
#include "trx.h"
#include "led.h"
static u8 _rtl8723ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
static u8 _rtl8723e_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
{
__le16 fc = rtl_get_fc(skb);
@ -49,16 +45,174 @@ static u8 _rtl8723ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
return skb->priority;
}
static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
struct rtl_stats *pstatus, u8 *pdesc,
struct rx_fwinfo_8723e *p_drvinfo,
bool bpacket_match_bssid,
bool bpacket_toself, bool packet_beacon)
/* mac80211's rate_idx is like this:
*
* 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
*
* B/G rate:
* (rx_status->flag & RX_FLAG_HT) = 0,
* DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
*
* N rate:
* (rx_status->flag & RX_FLAG_HT) = 1,
* DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
*
* 5G band:rx_status->band == IEEE80211_BAND_5GHZ
* A rate:
* (rx_status->flag & RX_FLAG_HT) = 0,
* DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
*
* N rate:
* (rx_status->flag & RX_FLAG_HT) = 1,
* DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
*/
static int _rtl8723e_rate_mapping(struct ieee80211_hw *hw,
bool isht, u8 desc_rate)
{
int rate_idx;
if (!isht) {
if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
switch (desc_rate) {
case DESC92C_RATE1M:
rate_idx = 0;
break;
case DESC92C_RATE2M:
rate_idx = 1;
break;
case DESC92C_RATE5_5M:
rate_idx = 2;
break;
case DESC92C_RATE11M:
rate_idx = 3;
break;
case DESC92C_RATE6M:
rate_idx = 4;
break;
case DESC92C_RATE9M:
rate_idx = 5;
break;
case DESC92C_RATE12M:
rate_idx = 6;
break;
case DESC92C_RATE18M:
rate_idx = 7;
break;
case DESC92C_RATE24M:
rate_idx = 8;
break;
case DESC92C_RATE36M:
rate_idx = 9;
break;
case DESC92C_RATE48M:
rate_idx = 10;
break;
case DESC92C_RATE54M:
rate_idx = 11;
break;
default:
rate_idx = 0;
break;
}
} else {
switch (desc_rate) {
case DESC92C_RATE6M:
rate_idx = 0;
break;
case DESC92C_RATE9M:
rate_idx = 1;
break;
case DESC92C_RATE12M:
rate_idx = 2;
break;
case DESC92C_RATE18M:
rate_idx = 3;
break;
case DESC92C_RATE24M:
rate_idx = 4;
break;
case DESC92C_RATE36M:
rate_idx = 5;
break;
case DESC92C_RATE48M:
rate_idx = 6;
break;
case DESC92C_RATE54M:
rate_idx = 7;
break;
default:
rate_idx = 0;
break;
}
}
} else {
switch (desc_rate) {
case DESC92C_RATEMCS0:
rate_idx = 0;
break;
case DESC92C_RATEMCS1:
rate_idx = 1;
break;
case DESC92C_RATEMCS2:
rate_idx = 2;
break;
case DESC92C_RATEMCS3:
rate_idx = 3;
break;
case DESC92C_RATEMCS4:
rate_idx = 4;
break;
case DESC92C_RATEMCS5:
rate_idx = 5;
break;
case DESC92C_RATEMCS6:
rate_idx = 6;
break;
case DESC92C_RATEMCS7:
rate_idx = 7;
break;
case DESC92C_RATEMCS8:
rate_idx = 8;
break;
case DESC92C_RATEMCS9:
rate_idx = 9;
break;
case DESC92C_RATEMCS10:
rate_idx = 10;
break;
case DESC92C_RATEMCS11:
rate_idx = 11;
break;
case DESC92C_RATEMCS12:
rate_idx = 12;
break;
case DESC92C_RATEMCS13:
rate_idx = 13;
break;
case DESC92C_RATEMCS14:
rate_idx = 14;
break;
case DESC92C_RATEMCS15:
rate_idx = 15;
break;
default:
rate_idx = 0;
break;
}
}
return rate_idx;
}
static void _rtl8723e_query_rxphystatus(struct ieee80211_hw *hw,
struct rtl_stats *pstatus, u8 *pdesc,
struct rx_fwinfo_8723e *p_drvinfo,
bool bpacket_match_bssid,
bool bpacket_toself, bool packet_beacon)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
struct phy_sts_cck_8723e_t *cck_buf;
s8 rx_pwr_all, rx_pwr[4];
s8 rx_pwr_all = 0, rx_pwr[4];
u8 rf_rx_num = 0, evm, pwdb_all;
u8 i, max_spatial_stream;
u32 rssi, total_rssi = 0;
@ -68,8 +222,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
pstatus->packet_matchbssid = bpacket_match_bssid;
pstatus->packet_toself = bpacket_toself;
pstatus->packet_beacon = packet_beacon;
pstatus->rx_mimo_sig_qual[0] = -1;
pstatus->rx_mimo_sig_qual[1] = -1;
pstatus->rx_mimo_signalquality[0] = -1;
pstatus->rx_mimo_signalquality[1] = -1;
if (is_cck) {
u8 report, cck_highpwr;
@ -77,14 +231,14 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
/* CCK Driver info Structure is not the same as OFDM packet. */
cck_buf = (struct phy_sts_cck_8723e_t *)p_drvinfo;
/* (1)Hardware does not provide RSSI for CCK
* (2)PWDB, Average PWDB cacluated by
/* (1)Hardware does not provide RSSI for CCK */
/* (2)PWDB, Average PWDB cacluated by
* hardware (for rate adaptive)
*/
if (ppsc->rfpwr_state == ERFON)
cck_highpwr = (u8) rtl_get_bbreg(hw,
RFPGA0_XA_HSSIPARAMETER2,
BIT(9));
cck_highpwr = (u8)rtl_get_bbreg(hw,
RFPGA0_XA_HSSIPARAMETER2,
BIT(9));
else
cck_highpwr = false;
@ -127,8 +281,9 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
}
pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
/* CCK gain is smaller than OFDM/MCS gain,
* so we add gain diff. From experience, the val is 6
/* CCK gain is smaller than OFDM/MCS gain, */
/* so we add gain diff by experiences,
* the val is 6
*/
pwdb_all += 6;
if (pwdb_all > 100)
@ -152,9 +307,9 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
if (bpacket_match_bssid) {
u8 sq;
if (pstatus->rx_pwdb_all > 40) {
if (pstatus->rx_pwdb_all > 40)
sq = 100;
} else {
else {
sq = cck_buf->sq_rpt;
if (sq > 64)
sq = 0;
@ -165,8 +320,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
}
pstatus->signalquality = sq;
pstatus->rx_mimo_sig_qual[0] = sq;
pstatus->rx_mimo_sig_qual[1] = -1;
pstatus->rx_mimo_signalquality[0] = sq;
pstatus->rx_mimo_signalquality[1] = -1;
}
} else {
rtlpriv->dm.rfpath_rxenable[0] =
@ -179,18 +334,20 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
if (rtlpriv->dm.rfpath_rxenable[i])
rf_rx_num++;
rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f)*2) - 110;
rx_pwr[i] = ((p_drvinfo->gain_trsw[i] &
0x3f) * 2) - 110;
/* Translate DBM to percentage. */
rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
total_rssi += rssi;
/* Get Rx snr value in DB */
rtlpriv->stats.rx_snr_db[i] = (p_drvinfo->rxsnr[i] / 2);
rtlpriv->stats.rx_snr_db[i] =
(long)(p_drvinfo->rxsnr[i] / 2);
/* Record Signal Strength for next packet */
if (bpacket_match_bssid)
pstatus->rx_mimo_signalstrength[i] = (u8) rssi;
pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
}
/* (2)PWDB, Average PWDB cacluated by
@ -204,8 +361,8 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
pstatus->recvsignalpower = rx_pwr_all;
/* (3)EVM of HT rate */
if (pstatus->is_ht && pstatus->rate >= DESC92_RATEMCS8 &&
pstatus->rate <= DESC92_RATEMCS15)
if (pstatus->is_ht && pstatus->rate >= DESC92C_RATEMCS8 &&
pstatus->rate <= DESC92C_RATEMCS15)
max_spatial_stream = 2;
else
max_spatial_stream = 1;
@ -218,8 +375,10 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
* spatial stream only
*/
if (i == 0)
pstatus->signalquality = (evm & 0xff);
pstatus->rx_mimo_sig_qual[i] = (evm & 0xff);
pstatus->signalquality =
(u8)(evm & 0xff);
pstatus->rx_mimo_signalquality[i] =
(u8)(evm & 0xff);
}
}
}
@ -235,71 +394,73 @@ static void _rtl8723ae_query_rxphystatus(struct ieee80211_hw *hw,
total_rssi /= rf_rx_num));
}
static void _rtl8723ae_translate_rx_signal_stuff(struct ieee80211_hw *hw,
struct sk_buff *skb, struct rtl_stats *pstatus,
u8 *pdesc, struct rx_fwinfo_8723e *p_drvinfo)
static void translate_rx_signal_stuff(struct ieee80211_hw *hw,
struct sk_buff *skb,
struct rtl_stats *pstatus, u8 *pdesc,
struct rx_fwinfo_8723e *p_drvinfo)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct ieee80211_hdr *hdr;
u8 *tmp_buf;
u8 *praddr;
__le16 fc;
u16 type;
bool packet_matchbssid, packet_toself, packet_beacon = false;
/*u8 *psaddr;*/
u16 fc, type;
bool packet_matchbssid, packet_toself, packet_beacon;
tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
hdr = (struct ieee80211_hdr *)tmp_buf;
fc = hdr->frame_control;
type = WLAN_FC_GET_TYPE(fc);
fc = le16_to_cpu(hdr->frame_control);
type = WLAN_FC_GET_TYPE(hdr->frame_control);
praddr = hdr->addr1;
packet_matchbssid =
((IEEE80211_FTYPE_CTL != type) &&
ether_addr_equal(mac->bssid,
(le16_to_cpu(fc) & IEEE80211_FCTL_TODS) ? hdr->addr1 :
(le16_to_cpu(fc) & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
hdr->addr3) &&
(!pstatus->hwerror) && (!pstatus->crc) && (!pstatus->icv));
packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
(ether_addr_equal(mac->bssid, (fc & IEEE80211_FCTL_TODS) ?
hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ?
hdr->addr2 : hdr->addr3)) &&
(!pstatus->hwerror) &&
(!pstatus->crc) && (!pstatus->icv));
packet_toself = (packet_matchbssid &&
ether_addr_equal(praddr, rtlefuse->dev_addr));
packet_toself = packet_matchbssid &&
(ether_addr_equal(praddr, rtlefuse->dev_addr));
if (ieee80211_is_beacon(fc))
if (ieee80211_is_beacon(hdr->frame_control))
packet_beacon = true;
else
packet_beacon = false;
_rtl8723ae_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
packet_matchbssid, packet_toself,
packet_beacon);
_rtl8723e_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
packet_matchbssid, packet_toself,
packet_beacon);
rtl_process_phyinfo(hw, tmp_buf, pstatus);
}
bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb)
bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb)
{
struct rx_fwinfo_8723e *p_drvinfo;
struct ieee80211_hdr *hdr;
u32 phystatus = GET_RX_DESC_PHYST(pdesc);
status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
RX_DRV_INFO_SIZE_UNIT;
status->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
status->icv = (u16) GET_RX_DESC_ICV(pdesc);
status->crc = (u16) GET_RX_DESC_CRC32(pdesc);
status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
RX_DRV_INFO_SIZE_UNIT;
status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
status->icv = (u16)GET_RX_DESC_ICV(pdesc);
status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
status->hwerror = (status->crc | status->icv);
status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
status->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
status->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
status->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
status->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
&& (GET_RX_DESC_FAGGR(pdesc) == 1));
status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
status->shortpreamble = (u16)GET_RX_DESC_SPLCP(pdesc);
status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
status->isfirst_ampdu = (bool)((GET_RX_DESC_PAGGR(pdesc) == 1) &&
(GET_RX_DESC_FAGGR(pdesc) == 1));
status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
status->rx_is40Mhzpacket = (bool)GET_RX_DESC_BW(pdesc);
status->is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
status->is_cck = RTL8723E_RX_HAL_IS_CCK_RATE(status->rate);
@ -307,6 +468,9 @@ bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
rx_status->freq = hw->conf.chandef.chan->center_freq;
rx_status->band = hw->conf.chandef.chan->band;
hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size
+ status->rx_bufshift);
if (status->crc)
rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
@ -320,69 +484,68 @@ bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
/* hw will set status->decrypted true, if it finds the
* frame is open data frame or mgmt frame.
* Thus hw will not decrypt a robust managment frame
* So hw will not decryption robust managment frame
* for IEEE80211w but still set status->decrypted
* true, so here we should set it back to undecrypted
* for IEEE80211w frame, and mac80211 sw will help
* to decrypt it
*/
if (status->decrypted) {
hdr = (struct ieee80211_hdr *)(skb->data +
status->rx_drvinfo_size + status->rx_bufshift);
if (!hdr) {
/* during testing, hdr could be NULL here */
WARN_ON_ONCE(true);
pr_err("decrypted is true but hdr NULL, from skb %p\n",
rtl_get_hdr(skb));
return false;
}
if ((_ieee80211_is_robust_mgmt_frame(hdr)) &&
(ieee80211_has_protected(hdr->frame_control)))
rx_status->flag &= ~RX_FLAG_DECRYPTED;
else
if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
(ieee80211_has_protected(hdr->frame_control)))
rx_status->flag |= RX_FLAG_DECRYPTED;
else
rx_status->flag &= ~RX_FLAG_DECRYPTED;
}
/* rate_idx: index of data rate into band's
* supported rates or MCS index if HT rates
* are use (RX_FLAG_HT)
* Notice: this is diff with windows define
*/
rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
status->rate, false);
rx_status->rate_idx = _rtl8723e_rate_mapping(hw,
status->is_ht, status->rate);
rx_status->mactime = status->timestamp_low;
if (phystatus == true) {
p_drvinfo = (struct rx_fwinfo_8723e *)(skb->data +
status->rx_bufshift);
status->rx_bufshift);
_rtl8723ae_translate_rx_signal_stuff(hw,
skb, status, pdesc, p_drvinfo);
translate_rx_signal_stuff(hw, skb, status, pdesc, p_drvinfo);
}
/*rx_status->qual = status->signal; */
rx_status->signal = status->recvsignalpower + 10;
return true;
}
void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, u8 hw_queue,
struct rtl_tcb_desc *ptcdesc)
void rtl8723e_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
u8 *txbd, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
bool defaultadapter = true;
u8 *pdesc = pdesc_tx;
bool b_defaultadapter = true;
/* bool b_trigger_ac = false; */
u8 *pdesc = (u8 *)pdesc_tx;
u16 seq_number;
__le16 fc = hdr->frame_control;
u8 fw_qsel = _rtl8723ae_map_hwqueue_to_fwqueue(skb, hw_queue);
u8 fw_qsel = _rtl8723e_map_hwqueue_to_fwqueue(skb, hw_queue);
bool firstseg = ((hdr->seq_ctrl &
cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
bool lastseg = ((hdr->frame_control &
cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
dma_addr_t mapping = pci_map_single(rtlpci->pdev,
skb->data, skb->len,
PCI_DMA_TODEVICE);
@ -398,12 +561,13 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
} else if (mac->opmode == NL80211_IFTYPE_AP ||
mac->opmode == NL80211_IFTYPE_ADHOC) {
if (sta)
bw_40 = sta->bandwidth >= IEEE80211_STA_RX_BW_40;
bw_40 = sta->ht_cap.cap &
IEEE80211_HT_CAP_SUP_WIDTH_20_40;
}
seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
rtl_get_tcb_desc(hw, info, sta, skb, ptcdesc);
rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_8723e));
@ -415,9 +579,9 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
if (firstseg) {
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
SET_TX_DESC_TX_RATE(pdesc, ptcdesc->hw_rate);
SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
if (ptcdesc->use_shortgi || ptcdesc->use_shortpreamble)
if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
@ -426,31 +590,33 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
}
SET_TX_DESC_SEQ(pdesc, seq_number);
SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcdesc->rts_enable &&
!ptcdesc->
cts_enable) ? 1 : 0));
SET_TX_DESC_RTS_ENABLE(pdesc,
((ptcb_desc->rts_enable &&
!ptcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_HW_RTS_ENABLE(pdesc,
((ptcdesc->rts_enable
|| ptcdesc->cts_enable) ? 1 : 0));
SET_TX_DESC_CTS2SELF(pdesc, ((ptcdesc->cts_enable) ? 1 : 0));
SET_TX_DESC_RTS_STBC(pdesc, ((ptcdesc->rts_stbc) ? 1 : 0));
((ptcb_desc->rts_enable ||
ptcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_CTS2SELF(pdesc,
((ptcb_desc->cts_enable) ? 1 : 0));
SET_TX_DESC_RTS_STBC(pdesc,
((ptcb_desc->rts_stbc) ? 1 : 0));
SET_TX_DESC_RTS_RATE(pdesc, ptcdesc->rts_rate);
SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
SET_TX_DESC_RTS_BW(pdesc, 0);
SET_TX_DESC_RTS_SC(pdesc, ptcdesc->rts_sc);
SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
SET_TX_DESC_RTS_SHORT(pdesc,
((ptcdesc->rts_rate <= DESC92_RATE54M) ?
(ptcdesc->rts_use_shortpreamble ? 1 : 0)
: (ptcdesc->rts_use_shortgi ? 1 : 0)));
((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
(ptcb_desc->rts_use_shortpreamble ? 1 : 0)
: (ptcb_desc->rts_use_shortgi ? 1 : 0)));
if (bw_40) {
if (ptcdesc->packet_bw) {
if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
SET_TX_DESC_DATA_BW(pdesc, 1);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
SET_TX_DESC_TX_SUB_CARRIER(pdesc,
mac->cur_40_prime_sc);
mac->cur_40_prime_sc);
}
} else {
SET_TX_DESC_DATA_BW(pdesc, 0);
@ -481,6 +647,7 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
default:
SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
break;
}
}
@ -490,7 +657,7 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
SET_TX_DESC_DISABLE_FB(pdesc, 0);
SET_TX_DESC_USE_RATE(pdesc, ptcdesc->use_driver_rate ? 1 : 0);
SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
if (ieee80211_is_data_qos(fc)) {
if (mac->rdg_en) {
@ -510,18 +677,21 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
if (rtlpriv->dm.useramask) {
SET_TX_DESC_RATE_ID(pdesc, ptcdesc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcdesc->mac_id);
SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
} else {
SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcdesc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcdesc->ratr_index);
SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
}
if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
SET_TX_DESC_HWSEQ_EN_8723(pdesc, 1);
/* SET_TX_DESC_HWSEQ_EN(pdesc, 1); */
/* SET_TX_DESC_PKT_ID(pdesc, 8); */
if (!defaultadapter)
if (!b_defaultadapter)
SET_TX_DESC_HWSEQ_SEL_8723(pdesc, 1);
/* SET_TX_DESC_QOS(pdesc, 1); */
}
SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
@ -534,17 +704,19 @@ void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
}
void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw,
u8 *pdesc, bool firstseg,
bool lastseg, struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
u8 fw_queue = QSLT_BEACON;
dma_addr_t mapping = pci_map_single(rtlpci->pdev,
skb->data, skb->len,
PCI_DMA_TODEVICE);
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
__le16 fc = hdr->frame_control;
if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
@ -557,7 +729,7 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
if (firstseg)
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
SET_TX_DESC_TX_RATE(pdesc, DESC92_RATE1M);
SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
SET_TX_DESC_SEQ(pdesc, 0);
@ -577,7 +749,7 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
SET_TX_DESC_OWN(pdesc, 1);
SET_TX_DESC_PKT_SIZE(pdesc, (u16) (skb->len));
SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
SET_TX_DESC_FIRST_SEG(pdesc, 1);
SET_TX_DESC_LAST_SEG(pdesc, 1);
@ -597,8 +769,8 @@ void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
pdesc, TX_DESC_SIZE);
}
void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val)
void rtl8723e_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val)
{
if (istx == true) {
switch (desc_name) {
@ -635,7 +807,7 @@ void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
}
}
u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name)
{
u32 ret = 0;
@ -660,6 +832,9 @@ u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
case HW_DESC_RXPKT_LEN:
ret = GET_RX_DESC_PKT_LEN(pdesc);
break;
case HW_DESC_RXBUFF_ADDR:
ret = GET_RX_DESC_BUFF_ADDR(pdesc);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
desc_name);
@ -669,7 +844,25 @@ u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
return ret;
}
void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index)
{
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl8723e_get_desc(entry, true, HW_DESC_OWN);
/**
*beacon packet will only use the first
*descriptor defautly,and the own may not
*be cleared by the hardware
*/
if (own)
return false;
return true;
}
void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (hw_queue == BEACON_QUEUE) {
@ -679,3 +872,10 @@ void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
BIT(0) << (hw_queue));
}
}
u32 rtl8723e_rx_command_packet(struct ieee80211_hw *hw,
struct rtl_stats status,
struct sk_buff *skb)
{
return 0;
}

325
drivers/net/wireless/rtlwifi/rtl8723ae/trx.h
View File

@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@ -30,77 +26,77 @@
#ifndef __RTL8723E_TRX_H__
#define __RTL8723E_TRX_H__
#define TX_DESC_SIZE 64
#define TX_DESC_SIZE 64
#define TX_DESC_AGGR_SUBFRAME_SIZE 32
#define RX_DESC_SIZE 32
#define RX_DESC_SIZE 32
#define RX_DRV_INFO_SIZE_UNIT 8
#define TX_DESC_NEXT_DESC_OFFSET 40
#define USB_HWDESC_HEADER_LEN 32
#define CRCLENGTH 4
#define CRCLENGTH 4
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
#define SET_TX_DESC_BMC(__pdesc, __val) \
#define SET_TX_DESC_BMC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
#define SET_TX_DESC_HTC(__pdesc, __val) \
#define SET_TX_DESC_HTC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
#define SET_TX_DESC_LINIP(__pdesc, __val) \
#define SET_TX_DESC_LINIP(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
#define SET_TX_DESC_GF(__pdesc, __val) \
#define SET_TX_DESC_GF(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_TX_DESC_OWN(__pdesc, __val) \
#define SET_TX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 16)
#define GET_TX_DESC_OFFSET(__pdesc) \
#define GET_TX_DESC_OFFSET(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 8)
#define GET_TX_DESC_BMC(__pdesc) \
#define GET_TX_DESC_BMC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 1)
#define GET_TX_DESC_HTC(__pdesc) \
#define GET_TX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 25, 1)
#define GET_TX_DESC_LAST_SEG(__pdesc) \
#define GET_TX_DESC_LAST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_TX_DESC_LINIP(__pdesc) \
#define GET_TX_DESC_LINIP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_TX_DESC_NO_ACM(__pdesc) \
#define GET_TX_DESC_NO_ACM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_TX_DESC_GF(__pdesc) \
#define GET_TX_DESC_GF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_TX_DESC_OWN(__pdesc) \
#define GET_TX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_TX_DESC_MACID(__pdesc, __val) \
#define SET_TX_DESC_MACID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 5, __val)
#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 5, 1, __val)
#define SET_TX_DESC_BK(__pdesc, __val) \
#define SET_TX_DESC_BK(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 6, 1, __val)
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 7, 1, __val)
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
#define SET_TX_DESC_PIFS(__pdesc, __val) \
#define SET_TX_DESC_PIFS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val)
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val)
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
@ -109,34 +105,34 @@
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val)
#define GET_TX_DESC_MACID(__pdesc) \
#define GET_TX_DESC_MACID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
#define GET_TX_DESC_AGG_BREAK(__pdesc) \
#define GET_TX_DESC_AGG_BREAK(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
#define GET_TX_DESC_PIFS(__pdesc) \
#define GET_TX_DESC_PIFS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
#define GET_TX_DESC_RATE_ID(__pdesc) \
#define GET_TX_DESC_RATE_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
#define GET_TX_DESC_SEC_TYPE(__pdesc) \
#define GET_TX_DESC_SEC_TYPE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 24, 8)
#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val)
#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val)
@ -144,9 +140,9 @@
SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
#define SET_TX_DESC_RAW(__pdesc, __val) \
#define SET_TX_DESC_RAW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
#define SET_TX_DESC_CCX(__pdesc, __val) \
#define SET_TX_DESC_CCX(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
@ -161,62 +157,62 @@
#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val)
#define GET_TX_DESC_RTS_RC(__pdesc) \
#define GET_TX_DESC_RTS_RC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 0, 6)
#define GET_TX_DESC_DATA_RC(__pdesc) \
#define GET_TX_DESC_DATA_RC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 6, 6)
#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 14, 2)
#define GET_TX_DESC_MORE_FRAG(__pdesc) \
#define GET_TX_DESC_MORE_FRAG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 17, 1)
#define GET_TX_DESC_RAW(__pdesc) \
#define GET_TX_DESC_RAW(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 18, 1)
#define GET_TX_DESC_CCX(__pdesc) \
#define GET_TX_DESC_CCX(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 19, 1)
#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 20, 3)
#define GET_TX_DESC_ANTSEL_A(__pdesc) \
#define GET_TX_DESC_ANTSEL_A(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 24, 1)
#define GET_TX_DESC_ANTSEL_B(__pdesc) \
#define GET_TX_DESC_ANTSEL_B(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 25, 1)
#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 26, 2)
#define GET_TX_DESC_TX_ANTL(__pdesc) \
#define GET_TX_DESC_TX_ANTL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 28, 2)
#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 30, 2)
#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val)
#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val)
#define SET_TX_DESC_SEQ(__pdesc, __val) \
#define SET_TX_DESC_SEQ(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val)
#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 4, __val)
#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 0, 8)
#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 8, 8)
#define GET_TX_DESC_SEQ(__pdesc) \
#define GET_TX_DESC_SEQ(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 16, 12)
#define GET_TX_DESC_PKT_ID(__pdesc) \
#define GET_TX_DESC_PKT_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 28, 4)
/* For RTL8723 */
#define SET_TX_DESC_TRIGGER_INT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 30, 1, __val)
#define SET_TX_DESC_HWSEQ_EN_8723(__pdesc, __val) \
#define SET_TX_DESC_HWSEQ_EN_8723(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 31, 1, __val)
#define SET_TX_DESC_HWSEQ_SEL_8723(__pTxDesc, __Value) \
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 6, 2, __Value)
#define SET_TX_DESC_HWSEQ_SEL_8723(__txdesc, __value) \
SET_BITS_TO_LE_4BYTE(__txdesc+16, 6, 2, __value)
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val)
#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val)
#define SET_TX_DESC_QOS(__pdesc, __val) \
#define SET_TX_DESC_QOS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val)
#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
@ -248,54 +244,54 @@
SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val)
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val)
#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val)
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val)
#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
#define GET_TX_DESC_RTS_RATE(__pdesc) \
#define GET_TX_DESC_RTS_RATE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 0, 5)
#define GET_TX_DESC_AP_DCFE(__pdesc) \
#define GET_TX_DESC_AP_DCFE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 5, 1)
#define GET_TX_DESC_QOS(__pdesc) \
#define GET_TX_DESC_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 6, 1)
#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 7, 1)
#define GET_TX_DESC_USE_RATE(__pdesc) \
#define GET_TX_DESC_USE_RATE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 8, 1)
#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 9, 1)
#define GET_TX_DESC_DISABLE_FB(__pdesc) \
#define GET_TX_DESC_DISABLE_FB(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 10, 1)
#define GET_TX_DESC_CTS2SELF(__pdesc) \
#define GET_TX_DESC_CTS2SELF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 11, 1)
#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 12, 1)
#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 13, 1)
#define GET_TX_DESC_PORT_ID(__pdesc) \
#define GET_TX_DESC_PORT_ID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 14, 1)
#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 18, 1)
#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 19, 1)
#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 20, 2)
#define GET_TX_DESC_TX_STBC(__pdesc) \
#define GET_TX_DESC_TX_STBC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 22, 2)
#define GET_TX_DESC_DATA_SHORT(__pdesc) \
#define GET_TX_DESC_DATA_SHORT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 24, 1)
#define GET_TX_DESC_DATA_BW(__pdesc) \
#define GET_TX_DESC_DATA_BW(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 25, 1)
#define GET_TX_DESC_RTS_SHORT(__pdesc) \
#define GET_TX_DESC_RTS_SHORT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 26, 1)
#define GET_TX_DESC_RTS_BW(__pdesc) \
#define GET_TX_DESC_RTS_BW(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 27, 1)
#define GET_TX_DESC_RTS_SC(__pdesc) \
#define GET_TX_DESC_RTS_SC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 28, 2)
#define GET_TX_DESC_RTS_STBC(__pdesc) \
#define GET_TX_DESC_RTS_STBC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 30, 2)
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
@ -315,17 +311,17 @@
#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val)
#define GET_TX_DESC_TX_RATE(__pdesc) \
#define GET_TX_DESC_TX_RATE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 0, 6)
#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 6, 1)
#define GET_TX_DESC_CCX_TAG(__pdesc) \
#define GET_TX_DESC_CCX_TAG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 7, 1)
#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 8, 5)
#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 13, 4)
#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 17, 1)
#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 18, 6)
@ -336,9 +332,9 @@
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val)
#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val)
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val)
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val)
#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val)
@ -349,19 +345,19 @@
#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val)\
SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val)
#define GET_TX_DESC_TXAGC_A(__pdesc) \
#define GET_TX_DESC_TXAGC_A(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 0, 5)
#define GET_TX_DESC_TXAGC_B(__pdesc) \
#define GET_TX_DESC_TXAGC_B(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 5, 5)
#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 10, 1)
#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 11, 5)
#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 16, 4)
#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 20, 4)
#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 24, 4)
#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 28, 4)
@ -379,11 +375,11 @@
#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 16, 4)
#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 20, 4)
#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 24, 4)
#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 28, 4)
@ -395,7 +391,7 @@
#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+32, 0, 32)
#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+36, 0, 32)
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
@ -410,97 +406,97 @@
#define GET_RX_DESC_PKT_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
#define GET_RX_DESC_CRC32(__pdesc) \
#define GET_RX_DESC_CRC32(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 14, 1)
#define GET_RX_DESC_ICV(__pdesc) \
#define GET_RX_DESC_ICV(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 15, 1)
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 4)
#define GET_RX_DESC_SECURITY(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 20, 3)
#define GET_RX_DESC_QOS(__pdesc) \
#define GET_RX_DESC_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 23, 1)
#define GET_RX_DESC_SHIFT(__pdesc) \
#define GET_RX_DESC_SHIFT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 2)
#define GET_RX_DESC_PHYST(__pdesc) \
#define GET_RX_DESC_PHYST(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_RX_DESC_SWDEC(__pdesc) \
#define GET_RX_DESC_SWDEC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_RX_DESC_LS(__pdesc) \
#define GET_RX_DESC_LS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_RX_DESC_FS(__pdesc) \
#define GET_RX_DESC_FS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_RX_DESC_EOR(__pdesc) \
#define GET_RX_DESC_EOR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_RX_DESC_OWN(__pdesc) \
#define GET_RX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
#define SET_RX_DESC_EOR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_RX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_RX_DESC_MACID(__pdesc) \
#define GET_RX_DESC_MACID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
#define GET_RX_DESC_TID(__pdesc) \
#define GET_RX_DESC_TID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 5, 4)
#define GET_RX_DESC_HWRSVD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 9, 5)
#define GET_RX_DESC_PAGGR(__pdesc) \
#define GET_RX_DESC_PAGGR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
#define GET_RX_DESC_FAGGR(__pdesc) \
#define GET_RX_DESC_FAGGR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
#define GET_RX_DESC_A1_FIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
#define GET_RX_DESC_A2_FIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 20, 4)
#define GET_RX_DESC_PAM(__pdesc) \
#define GET_RX_DESC_PAM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
#define GET_RX_DESC_PWR(__pdesc) \
#define GET_RX_DESC_PWR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
#define GET_RX_DESC_MD(__pdesc) \
#define GET_RX_DESC_MD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
#define GET_RX_DESC_MF(__pdesc) \
#define GET_RX_DESC_MF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
#define GET_RX_DESC_TYPE(__pdesc) \
#define GET_RX_DESC_TYPE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
#define GET_RX_DESC_MC(__pdesc) \
#define GET_RX_DESC_MC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
#define GET_RX_DESC_BC(__pdesc) \
#define GET_RX_DESC_BC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
#define GET_RX_DESC_SEQ(__pdesc) \
#define GET_RX_DESC_SEQ(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
#define GET_RX_DESC_FRAG(__pdesc) \
#define GET_RX_DESC_FRAG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 16, 14)
#define GET_RX_DESC_NEXT_IND(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 30, 1)
#define GET_RX_DESC_RSVD(__pdesc) \
#define GET_RX_DESC_RSVD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 31, 1)
#define GET_RX_DESC_RXMCS(__pdesc) \
#define GET_RX_DESC_RXMCS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 0, 6)
#define GET_RX_DESC_RXHT(__pdesc) \
#define GET_RX_DESC_RXHT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
#define GET_RX_DESC_SPLCP(__pdesc) \
#define GET_RX_DESC_SPLCP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 8, 1)
#define GET_RX_DESC_BW(__pdesc) \
#define GET_RX_DESC_BW(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 9, 1)
#define GET_RX_DESC_HTC(__pdesc) \
#define GET_RX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
#define GET_RX_DESC_HWPC_ERR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 14, 1)
#define GET_RX_DESC_HWPC_IND(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 15, 1)
#define GET_RX_DESC_IV0(__pdesc) \
#define GET_RX_DESC_IV0(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 16, 16)
#define GET_RX_DESC_IV1(__pdesc) \
#define GET_RX_DESC_IV1(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 0, 32)
#define GET_RX_DESC_TSFL(__pdesc) \
#define GET_RX_DESC_TSFL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
@ -508,17 +504,17 @@
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
do { \
if (_size > TX_DESC_NEXT_DESC_OFFSET) \
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
do { \
if (_size > TX_DESC_NEXT_DESC_OFFSET) \
memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
else \
memset(__pdesc, 0, _size); \
else \
memset(__pdesc, 0, _size); \
} while (0)
struct rx_fwinfo_8723e {
@ -699,22 +695,27 @@ struct rx_desc_8723e {
} __packed;
void rtl8723ae_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc,
u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, u8 hw_queue,
struct rtl_tcb_desc *ptcb_desc);
bool rtl8723ae_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb);
void rtl8723ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
u32 rtl8723ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
void rtl8723ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl8723ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,
void rtl8723e_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr,
u8 *pdesc, u8 *txbd,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, u8 hw_queue,
struct rtl_tcb_desc *ptcb_desc);
bool rtl8723e_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb);
void rtl8723e_set_desc(struct ieee80211_hw *hw,
u8 *pdesc, bool istx, u8 desc_name, u8 *val);
u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name);
bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool firstseg, bool lastseg,
struct sk_buff *skb);
u32 rtl8723e_rx_command_packet(struct ieee80211_hw *hw,
struct rtl_stats status,
struct sk_buff *skb);
#endif

2
drivers/net/wireless/rtlwifi/rtl8723be/hw.c
View File

@ -1015,7 +1015,7 @@ int rtl8723be_hw_init(struct ieee80211_hw *hw)
tmp_u1b &= 0x7F;
rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
err = rtl8723_download_fw(hw, true);
err = rtl8723_download_fw(hw, true, FW_8192C_POLLING_TIMEOUT_COUNT);
if (err) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"Failed to download FW. Init HW without FW now..\n");

2
drivers/net/wireless/rtlwifi/rtl8723be/sw.c
View File

@ -196,7 +196,7 @@ bool rtl8723be_get_btc_status(void)
return true;
}
static bool is_fw_header(struct rtl92c_firmware_header *hdr)
static bool is_fw_header(struct rtl8723e_firmware_header *hdr)
{
return (hdr->signature & 0xfff0) == 0x5300;
}

14
drivers/net/wireless/rtlwifi/rtl8723com/dm_common.c
View File

@ -44,7 +44,6 @@ EXPORT_SYMBOL_GPL(rtl8723_dm_init_dynamic_txpower);
void rtl8723_dm_init_edca_turbo(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->dm.current_turbo_edca = false;
rtlpriv->dm.is_any_nonbepkts = false;
rtlpriv->dm.is_cur_rdlstate = false;
@ -54,12 +53,13 @@ EXPORT_SYMBOL_GPL(rtl8723_dm_init_edca_turbo);
void rtl8723_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
rtlpriv->dm_pstable.pre_ccastate = CCA_MAX;
rtlpriv->dm_pstable.cur_ccasate = CCA_MAX;
rtlpriv->dm_pstable.pre_rfstate = RF_MAX;
rtlpriv->dm_pstable.cur_rfstate = RF_MAX;
rtlpriv->dm_pstable.rssi_val_min = 0;
rtlpriv->dm_pstable.initialize = 0;
dm_pstable->pre_ccastate = CCA_MAX;
dm_pstable->cur_ccasate = CCA_MAX;
dm_pstable->pre_rfstate = RF_MAX;
dm_pstable->cur_rfstate = RF_MAX;
dm_pstable->rssi_val_min = 0;
dm_pstable->initialize = 0;
}
EXPORT_SYMBOL_GPL(rtl8723_dm_init_dynamic_bb_powersaving);

84
drivers/net/wireless/rtlwifi/rtl8723com/fw_common.c
View File

@ -36,7 +36,8 @@ void rtl8723_enable_fw_download(struct ieee80211_hw *hw, bool enable)
if (enable) {
tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
tmp | 0x04);
tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
@ -95,7 +96,7 @@ void rtl8723_fw_page_write(struct ieee80211_hw *hw,
}
EXPORT_SYMBOL_GPL(rtl8723_fw_page_write);
static void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
{
u32 fwlen = *pfwlen;
u8 remain = (u8) (fwlen % 4);
@ -109,60 +110,64 @@ static void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
}
*pfwlen = fwlen;
}
EXPORT_SYMBOL(rtl8723_fill_dummy);
void rtl8723_write_fw(struct ieee80211_hw *hw,
enum version_8723e version,
u8 *buffer, u32 size)
u8 *buffer, u32 size, u8 max_page)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 *bufferptr = buffer;
u32 pagenums, remainsize;
u32 page_nums, remain_size;
u32 page, offset;
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size);
rtl8723_fill_dummy(bufferptr, &size);
pagenums = size / FW_8192C_PAGE_SIZE;
remainsize = size % FW_8192C_PAGE_SIZE;
page_nums = size / FW_8192C_PAGE_SIZE;
remain_size = size % FW_8192C_PAGE_SIZE;
if (pagenums > 8) {
if (page_nums > max_page) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Page numbers should not greater then 8\n");
"Page numbers should not greater than %d\n", max_page);
}
for (page = 0; page < pagenums; page++) {
for (page = 0; page < page_nums; page++) {
offset = page * FW_8192C_PAGE_SIZE;
rtl8723_fw_page_write(hw, page, (bufferptr + offset),
FW_8192C_PAGE_SIZE);
}
if (remainsize) {
offset = pagenums * FW_8192C_PAGE_SIZE;
page = pagenums;
if (remain_size) {
offset = page_nums * FW_8192C_PAGE_SIZE;
page = page_nums;
rtl8723_fw_page_write(hw, page, (bufferptr + offset),
remainsize);
remain_size);
}
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW write done.\n");
}
EXPORT_SYMBOL_GPL(rtl8723_write_fw);
void rtl8723ae_firmware_selfreset(struct ieee80211_hw *hw)
{
u8 u1tmp;
u8 u1b_tmp;
u8 delay = 100;
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
while (u1tmp & BIT(2)) {
while (u1b_tmp & BIT(2)) {
delay--;
if (delay == 0)
break;
udelay(50);
u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
}
if (delay == 0) {
u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1tmp&(~BIT(2)));
u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
u1b_tmp&(~BIT(2)));
}
}
EXPORT_SYMBOL_GPL(rtl8723ae_firmware_selfreset);
@ -190,7 +195,8 @@ void rtl8723be_firmware_selfreset(struct ieee80211_hw *hw)
}
EXPORT_SYMBOL_GPL(rtl8723be_firmware_selfreset);
int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be)
int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be,
int max_count)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int err = -EIO;
@ -199,10 +205,10 @@ int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be)
do {
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
} while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
} while ((counter++ < max_count) &&
(!(value32 & FWDL_CHKSUM_RPT)));
if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
if (counter >= max_count) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"chksum report fail ! REG_MCUFWDL:0x%08x .\n",
value32);
@ -223,15 +229,15 @@ int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be)
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
if (value32 & WINTINI_RDY) {
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
"Polling FW ready success!! "
"REG_MCUFWDL:0x%08x .\n",
"Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
value32);
err = 0;
goto exit;
}
udelay(FW_8192C_POLLING_DELAY);
} while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
mdelay(FW_8192C_POLLING_DELAY);
} while (counter++ < max_count);
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",
@ -243,25 +249,28 @@ exit:
EXPORT_SYMBOL_GPL(rtl8723_fw_free_to_go);
int rtl8723_download_fw(struct ieee80211_hw *hw,
bool is_8723be)
bool is_8723be, int max_count)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl92c_firmware_header *pfwheader;
struct rtl8723e_firmware_header *pfwheader;
u8 *pfwdata;
u32 fwsize;
int err;
enum version_8723e version = rtlhal->version;
int max_page;
if (!rtlhal->pfirmware)
return 1;
pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
pfwheader = (struct rtl8723e_firmware_header *)rtlhal->pfirmware;
pfwdata = rtlhal->pfirmware;
fwsize = rtlhal->fwsize;
RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
"normal Firmware SIZE %d\n", fwsize);
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE)
max_page = 6;
else
max_page = 8;
if (rtlpriv->cfg->ops->is_fw_header(pfwheader)) {
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
"Firmware Version(%d), Signature(%#x), Size(%d)\n",
@ -271,23 +280,24 @@ int rtl8723_download_fw(struct ieee80211_hw *hw,
pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
}
if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
if (rtl_read_byte(rtlpriv, REG_MCUFWDL)&BIT(7)) {
if (is_8723be)
rtl8723be_firmware_selfreset(hw);
else
rtl8723ae_firmware_selfreset(hw);
rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
}
rtl8723_enable_fw_download(hw, true);
rtl8723_write_fw(hw, version, pfwdata, fwsize);
rtl8723_write_fw(hw, version, pfwdata, fwsize, max_page);
rtl8723_enable_fw_download(hw, false);
err = rtl8723_fw_free_to_go(hw, is_8723be);
err = rtl8723_fw_free_to_go(hw, is_8723be, max_count);
if (err) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Firmware is not ready to run!\n");
} else {
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
"Firmware is ready to run!\n");
}
return 0;

39
drivers/net/wireless/rtlwifi/rtl8723com/fw_common.h
View File

@ -30,7 +30,7 @@
#define REG_MCUFWDL 0x0080
#define FW_8192C_START_ADDRESS 0x1000
#define FW_8192C_PAGE_SIZE 4096
#define FW_8192C_POLLING_TIMEOUT_COUNT 6000
#define FW_8723A_POLLING_TIMEOUT_COUNT 6000
#define FW_8192C_POLLING_DELAY 5
#define MCUFWDL_RDY BIT(1)
@ -49,16 +49,23 @@ enum version_8723e {
VERSION_UNKNOWN = 0xFF,
};
enum rtl8723ae_h2c_cmd {
H2C_AP_OFFLOAD = 0,
H2C_SETPWRMODE = 1,
H2C_JOINBSSRPT = 2,
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 4,
H2C_P2P_PS_CTW_CMD = 5,
H2C_P2P_PS_OFFLOAD = 6,
H2C_RA_MASK = 7,
MAX_H2CCMD
struct rtl8723e_firmware_header {
u16 signature;
u8 category;
u8 function;
u16 version;
u8 subversion;
u8 rsvd1;
u8 month;
u8 date;
u8 hour;
u8 minute;
u16 ramcodesize;
u16 rsvd2;
u32 svnindex;
u32 rsvd3;
u32 rsvd4;
u32 rsvd5;
};
enum rtl8723be_cmd {
@ -120,7 +127,11 @@ void rtl8723_fw_page_write(struct ieee80211_hw *hw,
u32 page, const u8 *buffer, u32 size);
void rtl8723_write_fw(struct ieee80211_hw *hw,
enum version_8723e version,
u8 *buffer, u32 size);
int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be);
int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be);
u8 *buffer, u32 size, u8 max_page);
int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be, int count);
int rtl8723_download_fw(struct ieee80211_hw *hw, bool is_8723be, int count);
bool rtl8723_cmd_send_packet(struct ieee80211_hw *hw,
struct sk_buff *skb);
void rtl8723_fill_dummy(u8 *pfwbuf, u32 *pfwlen);
#endif

46
drivers/net/wireless/rtlwifi/rtl8723com/phy_common.c
View File

@ -43,9 +43,8 @@ u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
returnvalue = (originalvalue & bitmask) >> bitshift;
RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
"BBR MASK = 0x%x Addr[0x%x]= 0x%x\n",
bitmask, regaddr, originalvalue);
"BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
regaddr, originalvalue);
return returnvalue;
}
EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
@ -57,8 +56,8 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
u32 originalvalue, bitshift;
RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
"regaddr(%#x), bitmask(%#x), data(%#x)\n",
regaddr, bitmask, data);
"regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
data);
if (bitmask != MASKDWORD) {
originalvalue = rtl_read_dword(rtlpriv, regaddr);
@ -70,7 +69,7 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
"regaddr(%#x), bitmask(%#x), data(%#x)\n",
regaddr, bitmask, data);
regaddr, bitmask, data);
}
EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
@ -97,7 +96,7 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
u8 rfpi_enable = 0;
u32 retvalue;
offset &= 0xff;
offset &= 0x3f;
newoffset = offset;
if (RT_CANNOT_IO(hw)) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
@ -109,12 +108,15 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
else
tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
(newoffset << 23) | BLSSIREADEDGE;
(newoffset << 23) | BLSSIREADEDGE;
rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
tmplong & (~BLSSIREADEDGE));
mdelay(1);
rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
mdelay(2);
mdelay(1);
rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
tmplong | BLSSIREADEDGE);
mdelay(1);
if (rfpath == RF90_PATH_A)
rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
BIT(8));
@ -128,8 +130,8 @@ u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
BLSSIREADBACKDATA);
RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
"RFR-%d Addr[0x%x]= 0x%x\n",
rfpath, pphyreg->rf_rb, retvalue);
"RFR-%d Addr[0x%x]=0x%x\n",
rfpath, pphyreg->rf_rb, retvalue);
return retvalue;
}
EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
@ -148,13 +150,14 @@ void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
return;
}
offset &= 0xff;
offset &= 0x3f;
newoffset = offset;
data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
"RFW-%d Addr[0x%x]= 0x%x\n", rfpath,
pphyreg->rf3wire_offset, data_and_addr);
"RFW-%d Addr[0x%x]=0x%x\n",
rfpath, pphyreg->rf3wire_offset,
data_and_addr);
}
EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
@ -171,6 +174,8 @@ long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
break;
case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G:
offset = -8;
break;
default:
offset = -8;
break;
@ -202,14 +207,14 @@ void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
RFPGA0_XA_LSSIPARAMETER;
RFPGA0_XA_LSSIPARAMETER;
rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
RFPGA0_XB_LSSIPARAMETER;
RFPGA0_XB_LSSIPARAMETER;
rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
@ -264,6 +269,7 @@ void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
}
EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);

19
drivers/net/wireless/rtlwifi/wifi.h
View File

@ -143,6 +143,21 @@
#define FCS_LEN 4
#define EM_HDR_LEN 8
enum rtl8192c_h2c_cmd {
H2C_AP_OFFLOAD = 0,
H2C_SETPWRMODE = 1,
H2C_JOINBSSRPT = 2,
H2C_RSVDPAGE = 3,
H2C_RSSI_REPORT = 5,
H2C_RA_MASK = 6,
H2C_MACID_PS_MODE = 7,
H2C_P2P_PS_OFFLOAD = 8,
H2C_MAC_MODE_SEL = 9,
H2C_PWRM = 15,
H2C_P2P_PS_CTW_CMD = 24,
MAX_H2CCMD
};
#define MAX_TX_COUNT 4
#define MAX_REGULATION_NUM 4
#define MAX_RF_PATH_NUM 4
@ -2041,6 +2056,8 @@ struct rtl_wow_pattern {
u32 mask[4];
};
struct rtl8723e_firmware_header;
struct rtl_hal_ops {
int (*init_sw_vars) (struct ieee80211_hw *hw);
void (*deinit_sw_vars) (struct ieee80211_hw *hw);
@ -2145,7 +2162,7 @@ struct rtl_hal_ops {
void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
bool (*get_btc_status) (void);
bool (*is_fw_header) (struct rtl92c_firmware_header *hdr);
bool (*is_fw_header)(struct rtl8723e_firmware_header *hdr);
u32 (*rx_command_packet)(struct ieee80211_hw *hw,
struct rtl_stats status, struct sk_buff *skb);
void (*add_wowlan_pattern)(struct ieee80211_hw *hw,