mmc: tmio: add flag to reduce delay after changing clock status

The docs for RCar Gen2 & 3 I have access to, mention delays of 5ms after
stop and 1ms after start. Make it possible to apply these values.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Wolfram Sang 2016-01-19 12:28:31 +01:00 committed by Ulf Hansson
parent 2bf8ab6ba2
commit 04e24b80a3
2 changed files with 8 additions and 3 deletions

View File

@ -172,7 +172,8 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
host->set_clk_div(host->pdev, (clk>>22) & 1);
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
msleep(10);
if (!(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG))
msleep(10);
}
static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
@ -185,14 +186,14 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
msleep(10);
msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 5 : 10);
}
static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
{
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
msleep(10);
msleep(host->pdata->flags & TMIO_MMC_FAST_CLK_CHG ? 1 : 10);
/* implicit BUG_ON(!res) */
if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {

View File

@ -65,6 +65,10 @@
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ (1 << 2)
/* Some controllers don't need to wait 10ms for clock changes */
#define TMIO_MMC_FAST_CLK_CHG (1 << 3)
/*
* Some controllers require waiting for the SD bus to become
* idle before writing to some registers.