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m68knommu: simplify ColdFire "timers" clock initialization 

The ColdFire "timers" clock setup can be simplified. There is really no
need for the flexible per-platform setup code. The clock interrupt can be
hard defined per CPU platform (in CPU include files). This makes the
actual timer code simpler.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2009-05-19 14:52:40 +10:00
parent f9311f2643
commit 04b75b10dc
12 changed files with 92 additions and 122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/m68k/include/asm/m5206sim.h
View File

@ -88,12 +88,19 @@
#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Generic GPIO
*/
#define MCFGPIO_PIN_MAX 8
#define MCFGPIO_IRQ_VECBASE -1
#define MCFGPIO_IRQ_MAX -1
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
@ -117,11 +124,5 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
/*
* Let the common interrupt handler code know that the ColdFire 5206*
* family of CPU's only has a 16bit sized IMR register.
*/
#define MCFSIM_IMR_IS_16BITS
/****************************************************************************/
#endif /* m5206sim_h */

6
arch/m68k/include/asm/m5249sim.h
View File

@ -70,6 +70,12 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* General purpose IO registers (in MBAR2).
*/

5
arch/m68k/include/asm/m5272sim.h
View File

@ -73,6 +73,11 @@
#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 69 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 70 /* Timer1, Level 7 */
/*
* Generic GPIO support

6
arch/m68k/include/asm/m5307sim.h
View File

@ -124,6 +124,7 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
@ -139,6 +140,11 @@
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.

5
arch/m68k/include/asm/m5407sim.h
View File

@ -111,6 +111,11 @@
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
/*
* Define the Cache register flags.

23
arch/m68knommu/platform/5206/config.c
View File

@ -68,21 +68,17 @@ static void __init m5206_uarts_init(void)
/***************************************************************************/
void mcf_settimericr(unsigned int timer, unsigned int level)
static void __init m5206_timers_init(void)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_clrimr(imr);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
#endif
}
/***************************************************************************/
@ -101,6 +97,7 @@ void m5206_cpu_reset(void)
void __init config_BSP(char *commandp, int size)
{
mach_reset = m5206_cpu_reset;
m5206_timers_init();
}
/***************************************************************************/

23
arch/m68knommu/platform/5206e/config.c
View File

@ -69,21 +69,17 @@ static void __init m5206e_uarts_init(void)
/***************************************************************************/
void mcf_settimericr(unsigned int timer, unsigned int level)
static void __init m5206e_timers_init(void)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_clrimr(imr);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
#endif
}
/***************************************************************************/
@ -108,6 +104,7 @@ void __init config_BSP(char *commandp, int size)
#endif /* CONFIG_NETtel */
mach_reset = m5206e_cpu_reset;
m5206e_timers_init();
}
/***************************************************************************/

24
arch/m68knommu/platform/5249/config.c
View File

@ -65,24 +65,19 @@ static void __init m5249_uarts_init(void)
m5249_uart_init_line(line, m5249_uart_platform[line].irq);
}
/***************************************************************************/
void mcf_settimericr(unsigned int timer, unsigned int level)
static void __init m5249_timers_init(void)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_clrimr(imr);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
#endif
}
/***************************************************************************/
@ -101,6 +96,7 @@ void m5249_cpu_reset(void)
void __init config_BSP(char *commandp, int size)
{
mach_reset = m5249_cpu_reset;
m5249_timers_init();
}
/***************************************************************************/

22
arch/m68knommu/platform/5272/config.c
View File

@ -20,12 +20,6 @@
/***************************************************************************/
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
/*
* Some platforms need software versions of the GPIO data registers.
*/
@ -148,14 +142,15 @@ void mcf_disableall(void)
/***************************************************************************/
void mcf_settimericr(int timer, int level)
static void __init m5272_timers_init(void)
{
volatile unsigned long *icrp;
/* Timer1 @ level6 is always used as system timer */
writel((0x8 | 0x6) << ((4 - 1) * 4), MCF_MBAR + MCFSIM_ICR1);
if ((timer >= 1 ) && (timer <= 4)) {
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = (0x8 | level) << ((4 - timer) * 4);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 @ level7 is to be used as a high speed profile timer */
writel((0x8 | 0x7) << ((4 - 2) * 4), MCF_MBAR + MCFSIM_ICR1);
#endif
}
/***************************************************************************/
@ -195,9 +190,8 @@ void __init config_BSP(char *commandp, int size)
commandp[size-1] = 0;
#endif
mcf_timervector = 69;
mcf_profilevector = 70;
mach_reset = m5272_cpu_reset;
m5272_timers_init();
}
/***************************************************************************/

33
arch/m68knommu/platform/5307/config.c
View File

@ -21,12 +21,6 @@
/***************************************************************************/
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
/*
* Some platforms need software versions of the GPIO data registers.
*/
@ -83,21 +77,17 @@ static void __init m5307_uarts_init(void)
/***************************************************************************/
void mcf_settimericr(unsigned int timer, unsigned int level)
static void __init m5307_timers_init(void)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_clrimr(imr);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
#endif
}
/***************************************************************************/
@ -120,13 +110,10 @@ void __init config_BSP(char *commandp, int size)
/* Copy command line from FLASH to local buffer... */
memcpy(commandp, (char *) 0xf0004000, size);
commandp[size-1] = 0;
/* Different timer setup - to prevent device clash */
mcf_timervector = 30;
mcf_profilevector = 31;
mcf_timerlevel = 6;
#endif
mach_reset = m5307_cpu_reset;
m5307_timers_init();
#ifdef CONFIG_BDM_DISABLE
/*

37
arch/m68knommu/platform/5407/config.c
View File

@ -20,12 +20,6 @@
/***************************************************************************/
extern unsigned int mcf_timervector;
extern unsigned int mcf_profilevector;
extern unsigned int mcf_timerlevel;
/***************************************************************************/
static struct mcf_platform_uart m5407_uart_platform[] = {
{
.mapbase = MCF_MBAR + MCFUART_BASE1,
@ -59,6 +53,7 @@ static void __init m5407_uart_init_line(int line, int irq)
} else if (line == 1) {
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
mcf_clrimr(MCFINTC_UART1);
}
}
@ -74,21 +69,17 @@ static void __init m5407_uarts_init(void)
/***************************************************************************/
void mcf_settimericr(unsigned int timer, unsigned int level)
static void __init m5407_timers_init(void)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFINTC_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFINTC_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_clrimr(imr);
}
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
#endif
}
/***************************************************************************/
@ -106,14 +97,8 @@ void m5407_cpu_reset(void)
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_CLEOPATRA)
/* Different timer setup - to prevent device clash */
mcf_timervector = 30;
mcf_profilevector = 31;
mcf_timerlevel = 6;
#endif
mach_reset = m5407_cpu_reset;
m5407_timers_init();
}
/***************************************************************************/

17
arch/m68knommu/platform/coldfire/timers.c
View File

@ -30,15 +30,6 @@
#define FREQ (MCF_BUSCLK / 16)
#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
/*
* Default the timer and vector to use for ColdFire. Some ColdFire
* CPU's and some boards may want different. Their sub-architecture
* startup code (in config.c) can change these if they want.
*/
unsigned int mcf_timervector = 29;
unsigned int mcf_profilevector = 31;
unsigned int mcf_timerlevel = 5;
/*
* These provide the underlying interrupt vector support.
* Unfortunately it is a little different on each ColdFire.
@ -107,7 +98,7 @@ static struct clocksource mcftmr_clk = {
void hw_timer_init(void)
{
setup_irq(mcf_timervector, &mcftmr_timer_irq);
setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcftmr_cycles_per_jiffy = FREQ / HZ;
@ -124,7 +115,7 @@ void hw_timer_init(void)
mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
clocksource_register(&mcftmr_clk);
mcf_settimericr(1, mcf_timerlevel);
mcf_clrimr(MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
@ -171,7 +162,7 @@ void coldfire_profile_init(void)
printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
PROFILEHZ);
setup_irq(mcf_profilevector, &coldfire_profile_irq);
setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
/* Set up TIMER 2 as high speed profile clock */
__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
@ -180,7 +171,7 @@ void coldfire_profile_init(void)
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
mcf_settimericr(2, 7);
mcf_clrimr(MCFINTC_TIMER2);
}
/***************************************************************************/