ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6
- Add L2 cache topology - Use Cortex specific device node for pmu - Append all gicv3 ITS entries - Append gpio nodes - Append power button node for D02 board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWzv94AAoJEAvIV27ZiWZcMAgP/2SURsSAQz1m9CabPD78gqPx R4PUtAbcrz8f5BbYxGXEXdoDY7AExvjWkZoH5XIP2+xDSB26SRgdkvAqisMYD7RU FG78LKJ7vYbAAiJtoqkcwG6GdvdyXYhw3HqCsyfT8cH+PFy4QgiDexrzFgSTh1Sv x1CG69ddLjg0Uc0LQx7JUmzdxsZN+jt8lfLCAU9zZBzsVAtxadrxcT/y/V1SXNMI sblknpv3I5XPDsQd1Sho0cLU7sGI2rWz5HqXTrW1febw6AMCTkmljZhbq4ezjQG0 GtB20LiuM3hYtZoQDAUAb/plABhfQOZ0nybjqDhGxvyUb6vuNHHLicA7CsrWsYgE 5T5KR2nZv3fnYFW1dprgrpuirUdBSk125p7gTwBFmcWv2fMcNKVZROkrjP6I0cwB Qu9sUa8jQ0oQqKkPa8KVtNZMRSVwAI+G0aeoJAbAV8Zs7ux4kzkaRZOiROxklWtI HFIiFsKmgPcenYbyrH6/b60/GIKIUQBdEN1kbPHSqF6zIt/IoLZhfAL5DHBMuwWE aP4mFxPaLUrSNpXGFmSMs737oatHK4lvb2Z1F9YOHXHQ20ttTKFWwQi0SMc1iLEf E/KDZedI6aud2DheDl9P7+w9JhFflHMlL0ZT3KWSn7pJ5qelTgxhGE7aPEc2hPXt ojSxNrtTqI8Vx7FJdK6C =IxPW -----END PGP SIGNATURE----- Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into next/dt64 Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu: - Add L2 cache topology - Use Cortex specific device node for pmu - Append all gicv3 ITS entries - Append gpio nodes - Append power button node for D02 board * tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi: arm64: dts: hip05: Append power button node for D02 board arm64: dts: hip05: Append gpio nodes arm64: dts: hip05: Append all gicv3 ITS entries arm64: dts: hip05: Use Cortex specific device node for pmu arm64: dts: hip05: Add L2 cache topology
This commit is contained in:
Arnd Bergmann
commit
047b2f6d7b
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "hip05.dtsi"
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/ {
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@ -29,8 +30,25 @@
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio_keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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pwrbutton {
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label = "Power Button";
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gpios = <&porta 8 GPIO_ACTIVE_LOW>;
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linux,code = <116>;
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debounce-interval = <0>;
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};
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};
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};
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&uart0 {
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status = "ok";
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};
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&peri_gpio0 {
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status = "ok";
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};
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@ -90,6 +90,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20000>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu1: cpu@20001 {
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@ -97,6 +98,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20001>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@20002 {
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@ -104,6 +106,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20002>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu3: cpu@20003 {
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@ -111,6 +114,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20003>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu4: cpu@20100 {
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@ -118,6 +122,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20100>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu5: cpu@20101 {
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@ -125,6 +130,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20101>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu6: cpu@20102 {
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@ -132,6 +138,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20102>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu7: cpu@20103 {
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@ -139,6 +146,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20103>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu8: cpu@20200 {
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@ -146,6 +154,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20200>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu9: cpu@20201 {
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@ -153,6 +162,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20201>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu10: cpu@20202 {
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@ -160,6 +170,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20202>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu11: cpu@20203 {
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@ -167,6 +178,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20203>;
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enable-method = "psci";
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next-level-cache = <&cluster2_l2>;
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};
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cpu12: cpu@20300 {
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@ -174,6 +186,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20300>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu13: cpu@20301 {
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@ -181,6 +194,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20301>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu14: cpu@20302 {
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@ -188,6 +202,7 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20302>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cpu15: cpu@20303 {
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@ -195,6 +210,23 @@
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x20303>;
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enable-method = "psci";
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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};
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@ -214,11 +246,29 @@
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<0x0 0xfe020000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its_totems: interrupt-controller@8c000000 {
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its_peri: interrupt-controller@8c000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x8c000000 0x0 0x40000>;
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};
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its_m3: interrupt-controller@a3000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xa3000000 0x0 0x40000>;
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};
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its_pcie: interrupt-controller@b7000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xb7000000 0x0 0x40000>;
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};
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its_dsa: interrupt-controller@c6000000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xc6000000 0x0 0x40000>;
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};
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};
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timer {
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@ -230,7 +280,7 @@
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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compatible = "arm,cortex-a57-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -272,5 +322,43 @@
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reg-io-width = <4>;
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status = "disabled";
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};
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peri_gpio0: gpio@802e0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x802e0000 0x0 0x10000>;
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status = "disabled";
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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peri_gpio1: gpio@802f0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x802f0000 0x0 0x10000>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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