thunderbolt: Add MSI-X support
Intel Thunderbolt controllers support up to 16 MSI-X vectors. Using MSI-X is preferred over MSI or legacy interrupt and may bring additional performance because there is no need to check the status registers which interrupt was triggered. While there we convert comments in structs tb_ring and tb_nhi to follow kernel-doc format more closely. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet <michael.jamet@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Yehezkel Bernat <yehezkel.bernat@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mika Westerberg
Greg Kroah-Hartman
parent
b2466355c0
commit
046bee1f9a
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@ -488,11 +488,11 @@ struct tb_ctl *tb_ctl_alloc(struct tb_nhi *nhi, hotplug_cb cb, void *cb_data)
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if (!ctl->frame_pool)
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goto err;
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ctl->tx = ring_alloc_tx(nhi, 0, 10);
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ctl->tx = ring_alloc_tx(nhi, 0, 10, RING_FLAG_NO_SUSPEND);
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if (!ctl->tx)
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goto err;
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ctl->rx = ring_alloc_rx(nhi, 0, 10);
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ctl->rx = ring_alloc_rx(nhi, 0, 10, RING_FLAG_NO_SUSPEND);
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if (!ctl->rx)
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goto err;
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@ -21,6 +21,12 @@
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#define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
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/*
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* Minimal number of vectors when we use MSI-X. Two for control channel
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* Rx/Tx and the rest four are for cross domain DMA paths.
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*/
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#define MSIX_MIN_VECS 6
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#define MSIX_MAX_VECS 16
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static int ring_interrupt_index(struct tb_ring *ring)
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{
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@ -42,6 +48,37 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active)
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int bit = ring_interrupt_index(ring) & 31;
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int mask = 1 << bit;
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u32 old, new;
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if (ring->irq > 0) {
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u32 step, shift, ivr, misc;
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void __iomem *ivr_base;
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int index;
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if (ring->is_tx)
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index = ring->hop;
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else
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index = ring->hop + ring->nhi->hop_count;
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/*
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* Ask the hardware to clear interrupt status bits automatically
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* since we already know which interrupt was triggered.
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*/
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misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
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if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
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misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
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iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
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}
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ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
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step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
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shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
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ivr = ioread32(ivr_base + step);
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ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
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if (active)
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ivr |= ring->vector << shift;
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iowrite32(ivr, ivr_base + step);
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}
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old = ioread32(ring->nhi->iobase + reg);
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if (active)
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new = old | mask;
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@ -239,8 +276,50 @@ int __ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
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return ret;
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}
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static irqreturn_t ring_msix(int irq, void *data)
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{
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struct tb_ring *ring = data;
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schedule_work(&ring->work);
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return IRQ_HANDLED;
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}
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static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
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{
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struct tb_nhi *nhi = ring->nhi;
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unsigned long irqflags;
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int ret;
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if (!nhi->pdev->msix_enabled)
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return 0;
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ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
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if (ret < 0)
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return ret;
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ring->vector = ret;
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ring->irq = pci_irq_vector(ring->nhi->pdev, ring->vector);
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if (ring->irq < 0)
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return ring->irq;
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irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
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return request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
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}
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static void ring_release_msix(struct tb_ring *ring)
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{
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if (ring->irq <= 0)
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return;
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free_irq(ring->irq, ring);
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ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
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ring->vector = 0;
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ring->irq = 0;
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}
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static struct tb_ring *ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
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bool transmit)
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bool transmit, unsigned int flags)
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{
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struct tb_ring *ring = NULL;
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dev_info(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
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@ -271,9 +350,14 @@ static struct tb_ring *ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
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ring->hop = hop;
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ring->is_tx = transmit;
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ring->size = size;
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ring->flags = flags;
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ring->head = 0;
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ring->tail = 0;
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ring->running = false;
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if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
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goto err;
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ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
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size * sizeof(*ring->descriptors),
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&ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
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@ -295,14 +379,16 @@ err:
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return NULL;
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}
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struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size)
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struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags)
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{
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return ring_alloc(nhi, hop, size, true);
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return ring_alloc(nhi, hop, size, true, flags);
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}
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struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size)
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struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags)
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{
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return ring_alloc(nhi, hop, size, false);
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return ring_alloc(nhi, hop, size, false, flags);
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}
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/**
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@ -413,6 +499,8 @@ void ring_free(struct tb_ring *ring)
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RING_TYPE(ring), ring->hop);
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}
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ring_release_msix(ring);
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dma_free_coherent(&ring->nhi->pdev->dev,
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ring->size * sizeof(*ring->descriptors),
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ring->descriptors, ring->descriptors_dma);
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@ -428,9 +516,9 @@ void ring_free(struct tb_ring *ring)
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mutex_unlock(&ring->nhi->lock);
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/**
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* ring->work can no longer be scheduled (it is scheduled only by
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* nhi_interrupt_work and ring_stop). Wait for it to finish before
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* freeing the ring.
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* ring->work can no longer be scheduled (it is scheduled only
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* by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
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* to finish before freeing the ring.
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*/
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flush_work(&ring->work);
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mutex_destroy(&ring->lock);
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@ -528,9 +616,52 @@ static void nhi_shutdown(struct tb_nhi *nhi)
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* We have to release the irq before calling flush_work. Otherwise an
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* already executing IRQ handler could call schedule_work again.
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*/
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devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
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flush_work(&nhi->interrupt_work);
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if (!nhi->pdev->msix_enabled) {
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devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
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flush_work(&nhi->interrupt_work);
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}
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mutex_destroy(&nhi->lock);
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ida_destroy(&nhi->msix_ida);
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}
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static int nhi_init_msi(struct tb_nhi *nhi)
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{
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struct pci_dev *pdev = nhi->pdev;
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int res, irq, nvec;
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/* In case someone left them on. */
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nhi_disable_interrupts(nhi);
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ida_init(&nhi->msix_ida);
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/*
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* The NHI has 16 MSI-X vectors or a single MSI. We first try to
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* get all MSI-X vectors and if we succeed, each ring will have
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* one MSI-X. If for some reason that does not work out, we
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* fallback to a single MSI.
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*/
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nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
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PCI_IRQ_MSIX);
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if (nvec < 0) {
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nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
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if (nvec < 0)
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return nvec;
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INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
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irq = pci_irq_vector(nhi->pdev, 0);
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if (irq < 0)
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return irq;
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res = devm_request_irq(&pdev->dev, irq, nhi_msi,
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IRQF_NO_SUSPEND, "thunderbolt", nhi);
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if (res) {
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dev_err(&pdev->dev, "request_irq failed, aborting\n");
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return res;
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}
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}
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return 0;
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}
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static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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@ -545,12 +676,6 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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return res;
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}
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res = pci_enable_msi(pdev);
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if (res) {
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dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
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return res;
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}
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res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
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if (res) {
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dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
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@ -568,7 +693,6 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (nhi->hop_count != 12 && nhi->hop_count != 32)
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dev_warn(&pdev->dev, "unexpected hop count: %d\n",
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nhi->hop_count);
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INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
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nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
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sizeof(*nhi->tx_rings), GFP_KERNEL);
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@ -577,12 +701,9 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (!nhi->tx_rings || !nhi->rx_rings)
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return -ENOMEM;
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nhi_disable_interrupts(nhi); /* In case someone left them on. */
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res = devm_request_irq(&pdev->dev, pdev->irq, nhi_msi,
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IRQF_NO_SUSPEND, /* must work during _noirq */
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"thunderbolt", nhi);
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res = nhi_init_msi(nhi);
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if (res) {
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dev_err(&pdev->dev, "request_irq failed, aborting\n");
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dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
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return res;
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}
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@ -7,45 +7,75 @@
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#ifndef DSL3510_H_
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#define DSL3510_H_
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#include <linux/idr.h>
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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/**
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* struct tb_nhi - thunderbolt native host interface
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* @lock: Must be held during ring creation/destruction. Is acquired by
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* interrupt_work when dispatching interrupts to individual rings.
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* @pdev: Pointer to the PCI device
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* @iobase: MMIO space of the NHI
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* @tx_rings: All Tx rings available on this host controller
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* @rx_rings: All Rx rings available on this host controller
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* @msix_ida: Used to allocate MSI-X vectors for rings
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* @interrupt_work: Work scheduled to handle ring interrupt when no
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* MSI-X is used.
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* @hop_count: Number of rings (end point hops) supported by NHI.
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*/
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struct tb_nhi {
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struct mutex lock; /*
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* Must be held during ring creation/destruction.
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* Is acquired by interrupt_work when dispatching
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* interrupts to individual rings.
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**/
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struct mutex lock;
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struct pci_dev *pdev;
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void __iomem *iobase;
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struct tb_ring **tx_rings;
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struct tb_ring **rx_rings;
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struct ida msix_ida;
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struct work_struct interrupt_work;
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u32 hop_count; /* Number of rings (end point hops) supported by NHI. */
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u32 hop_count;
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};
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/**
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* struct tb_ring - thunderbolt TX or RX ring associated with a NHI
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* @lock: Lock serializing actions to this ring. Must be acquired after
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* nhi->lock.
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* @nhi: Pointer to the native host controller interface
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* @size: Size of the ring
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* @hop: Hop (DMA channel) associated with this ring
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* @head: Head of the ring (write next descriptor here)
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* @tail: Tail of the ring (complete next descriptor here)
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* @descriptors: Allocated descriptors for this ring
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* @queue: Queue holding frames to be transferred over this ring
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* @in_flight: Queue holding frames that are currently in flight
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* @work: Interrupt work structure
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* @is_tx: Is the ring Tx or Rx
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* @running: Is the ring running
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* @irq: MSI-X irq number if the ring uses MSI-X. %0 otherwise.
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* @vector: MSI-X vector number the ring uses (only set if @irq is > 0)
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* @flags: Ring specific flags
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*/
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struct tb_ring {
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struct mutex lock; /* must be acquired after nhi->lock */
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struct mutex lock;
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struct tb_nhi *nhi;
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int size;
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int hop;
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int head; /* write next descriptor here */
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int tail; /* complete next descriptor here */
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int head;
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int tail;
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struct ring_desc *descriptors;
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dma_addr_t descriptors_dma;
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struct list_head queue;
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struct list_head in_flight;
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struct work_struct work;
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bool is_tx:1; /* rx otherwise */
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bool is_tx:1;
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bool running:1;
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int irq;
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u8 vector;
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unsigned int flags;
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};
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/* Leave ring interrupt enabled on suspend */
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#define RING_FLAG_NO_SUSPEND BIT(0)
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struct ring_frame;
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typedef void (*ring_cb)(struct tb_ring*, struct ring_frame*, bool canceled);
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@ -64,8 +94,10 @@ struct ring_frame {
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#define TB_FRAME_SIZE 0x100 /* minimum size for ring_rx */
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struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size);
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struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size);
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struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags);
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struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags);
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void ring_start(struct tb_ring *ring);
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void ring_stop(struct tb_ring *ring);
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void ring_free(struct tb_ring *ring);
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@ -95,7 +95,16 @@ struct ring_desc {
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#define REG_RING_INTERRUPT_BASE 0x38200
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#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
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/* Interrupt Vector Allocation */
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#define REG_INT_VEC_ALLOC_BASE 0x38c40
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#define REG_INT_VEC_ALLOC_BITS 4
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#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
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#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
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/* The last 11 bits contain the number of hops supported by the NHI port. */
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#define REG_HOP_COUNT 0x39640
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#define REG_DMA_MISC 0x39864
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#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
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#endif
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