From 9c811209eb87f26e83f1b1afea186d4797f8b71e Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 21 Sep 2015 20:56:58 +0530 Subject: [PATCH 01/77] dmaengine: xgene-dma: use dma_pool_zalloc We should use shiny new dma_pool_zalloc instead of dma_pool_alloc/memset Reported-by: Julia Lawall Reported-by: kbuild test robot Signed-off-by: Vinod Koul --- drivers/dma/xgene-dma.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c index b23e8d52d126..dc84ed1f7541 100644 --- a/drivers/dma/xgene-dma.c +++ b/drivers/dma/xgene-dma.c @@ -556,14 +556,12 @@ static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor( struct xgene_dma_desc_sw *desc; dma_addr_t phys; - desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys); + desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); if (!desc) { chan_err(chan, "Failed to allocate LDs\n"); return NULL; } - memset(desc, 0, sizeof(*desc)); - INIT_LIST_HEAD(&desc->tx_list); desc->tx.phys = phys; desc->tx.tx_submit = xgene_dma_tx_submit; From ad4a7b5065c1b4f5176e7d031c3cc2b36f776884 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Wed, 26 Aug 2015 13:17:24 -0700 Subject: [PATCH 02/77] dmaengine: ioatdma: adding shutdown support The ioatdma needs to be queisced and block all additional op submission during reboots. When NET_DMA was used, this caused issue as ops were still being sent to ioatdma during reboots even though PCI BME has been turned off. Even though NET_DMA has been deprecated, we need to prevent similar situations. The shutdown handler should address that. Signed-off-by: Dave Jiang Signed-off-by: Vinod Koul --- drivers/dma/ioat/dma.c | 3 ++- drivers/dma/ioat/dma.h | 6 ++++-- drivers/dma/ioat/init.c | 26 ++++++++++++++++++++++++++ drivers/dma/ioat/prep.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/dma/ioat/dma.c b/drivers/dma/ioat/dma.c index f66b7e640610..1d5df2ef148b 100644 --- a/drivers/dma/ioat/dma.c +++ b/drivers/dma/ioat/dma.c @@ -197,7 +197,8 @@ static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan) void ioat_start_null_desc(struct ioatdma_chan *ioat_chan) { spin_lock_bh(&ioat_chan->prep_lock); - __ioat_start_null_desc(ioat_chan); + if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + __ioat_start_null_desc(ioat_chan); spin_unlock_bh(&ioat_chan->prep_lock); } diff --git a/drivers/dma/ioat/dma.h b/drivers/dma/ioat/dma.h index 1bc084986646..8f4e607d5817 100644 --- a/drivers/dma/ioat/dma.h +++ b/drivers/dma/ioat/dma.h @@ -82,8 +82,9 @@ struct ioatdma_device { struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; struct dma_device dma_dev; u8 version; - struct msix_entry msix_entries[4]; - struct ioatdma_chan *idx[4]; +#define IOAT_MAX_CHANS 4 + struct msix_entry msix_entries[IOAT_MAX_CHANS]; + struct ioatdma_chan *idx[IOAT_MAX_CHANS]; struct dca_provider *dca; enum ioat_irq_mode irq_mode; u32 cap; @@ -95,6 +96,7 @@ struct ioatdma_chan { dma_addr_t last_completion; spinlock_t cleanup_lock; unsigned long state; + #define IOAT_CHAN_DOWN 0 #define IOAT_COMPLETION_ACK 1 #define IOAT_RESET_PENDING 2 #define IOAT_KOBJ_INIT_FAIL 3 diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c index 1c3c9b0abf4e..793c5dd6a0e7 100644 --- a/drivers/dma/ioat/init.c +++ b/drivers/dma/ioat/init.c @@ -1186,6 +1186,31 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca) return 0; } +static void ioat_shutdown(struct pci_dev *pdev) +{ + struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); + struct ioatdma_chan *ioat_chan; + int i; + + if (!ioat_dma) + return; + + for (i = 0; i < IOAT_MAX_CHANS; i++) { + ioat_chan = ioat_dma->idx[i]; + if (!ioat_chan) + continue; + + spin_lock_bh(&ioat_chan->prep_lock); + set_bit(IOAT_CHAN_DOWN, &ioat_chan->state); + del_timer_sync(&ioat_chan->timer); + spin_unlock_bh(&ioat_chan->prep_lock); + /* this should quiesce then reset */ + ioat_reset_hw(ioat_chan); + } + + ioat_disable_interrupts(ioat_dma); +} + #define DRV_NAME "ioatdma" static struct pci_driver ioat_pci_driver = { @@ -1193,6 +1218,7 @@ static struct pci_driver ioat_pci_driver = { .id_table = ioat_pci_tbl, .probe = ioat_pci_probe, .remove = ioat_remove, + .shutdown = ioat_shutdown, }; static struct ioatdma_device * diff --git a/drivers/dma/ioat/prep.c b/drivers/dma/ioat/prep.c index ad4fb41cd23b..6bb4a13a8fbd 100644 --- a/drivers/dma/ioat/prep.c +++ b/drivers/dma/ioat/prep.c @@ -121,6 +121,9 @@ ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, size_t total_len = len; int num_descs, idx, i; + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + num_descs = ioat_xferlen_to_descs(ioat_chan, len); if (likely(num_descs) && ioat_check_space_lock(ioat_chan, num_descs) == 0) @@ -254,6 +257,11 @@ struct dma_async_tx_descriptor * ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, size_t len, unsigned long flags) { + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + return __ioat_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); } @@ -262,6 +270,11 @@ ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, size_t len, enum sum_check_flags *result, unsigned long flags) { + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + /* the cleanup routine only sets bits on validate failure, it * does not clear bits on validate success... so clear it here */ @@ -574,6 +587,11 @@ ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, unsigned int src_cnt, const unsigned char *scf, size_t len, unsigned long flags) { + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + /* specify valid address for disabled result */ if (flags & DMA_PREP_PQ_DISABLE_P) dst[0] = dst[1]; @@ -614,6 +632,11 @@ ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, unsigned int src_cnt, const unsigned char *scf, size_t len, enum sum_check_flags *pqres, unsigned long flags) { + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + /* specify valid address for disabled result */ if (flags & DMA_PREP_PQ_DISABLE_P) pq[0] = pq[1]; @@ -638,6 +661,10 @@ ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, { unsigned char scf[MAX_SCF]; dma_addr_t pq[2]; + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; if (src_cnt > MAX_SCF) return NULL; @@ -661,6 +688,10 @@ ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, { unsigned char scf[MAX_SCF]; dma_addr_t pq[2]; + struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); + + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; if (src_cnt > MAX_SCF) return NULL; @@ -689,6 +720,9 @@ ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) struct ioat_ring_ent *desc; struct ioat_dma_descriptor *hw; + if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) + return NULL; + if (ioat_check_space_lock(ioat_chan, 1) == 0) desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); else From 4222a9074339fccc59526cbf30d8d2ec41468574 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Wed, 26 Aug 2015 13:17:30 -0700 Subject: [PATCH 03/77] dmaengine: ioatdma: add PCIe AER handlers Adding AER handlers in order to handle any PCIe errors. Signed-off-by: Dave Jiang Signed-off-by: Vinod Koul --- drivers/dma/ioat/init.c | 88 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c index 793c5dd6a0e7..4ef0c5e07912 100644 --- a/drivers/dma/ioat/init.c +++ b/drivers/dma/ioat/init.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dma.h" #include "registers.h" #include "hw.h" @@ -1211,14 +1212,91 @@ static void ioat_shutdown(struct pci_dev *pdev) ioat_disable_interrupts(ioat_dma); } +void ioat_resume(struct ioatdma_device *ioat_dma) +{ + struct ioatdma_chan *ioat_chan; + u32 chanerr; + int i; + + for (i = 0; i < IOAT_MAX_CHANS; i++) { + ioat_chan = ioat_dma->idx[i]; + if (!ioat_chan) + continue; + + spin_lock_bh(&ioat_chan->prep_lock); + clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state); + spin_unlock_bh(&ioat_chan->prep_lock); + + chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); + + /* no need to reset as shutdown already did that */ + } +} + #define DRV_NAME "ioatdma" +static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev, + enum pci_channel_state error) +{ + dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error); + + /* quiesce and block I/O */ + ioat_shutdown(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev) +{ + pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; + int err; + + dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME); + + if (pci_enable_device_mem(pdev) < 0) { + dev_err(&pdev->dev, + "Failed to enable PCIe device after reset.\n"); + result = PCI_ERS_RESULT_DISCONNECT; + } else { + pci_set_master(pdev); + pci_restore_state(pdev); + pci_save_state(pdev); + pci_wake_from_d3(pdev, false); + } + + err = pci_cleanup_aer_uncorrect_error_status(pdev); + if (err) { + dev_err(&pdev->dev, + "AER uncorrect error status clear failed: %#x\n", err); + } + + return result; +} + +static void ioat_pcie_error_resume(struct pci_dev *pdev) +{ + struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev); + + dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME); + + /* initialize and bring everything back */ + ioat_resume(ioat_dma); +} + +static const struct pci_error_handlers ioat_err_handler = { + .error_detected = ioat_pcie_error_detected, + .slot_reset = ioat_pcie_error_slot_reset, + .resume = ioat_pcie_error_resume, +}; + static struct pci_driver ioat_pci_driver = { .name = DRV_NAME, .id_table = ioat_pci_tbl, .probe = ioat_pci_probe, .remove = ioat_remove, .shutdown = ioat_shutdown, + .err_handler = &ioat_err_handler, }; static struct ioatdma_device * @@ -1271,13 +1349,17 @@ static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_set_drvdata(pdev, device); device->version = readb(device->reg_base + IOAT_VER_OFFSET); - if (device->version >= IOAT_VER_3_0) + if (device->version >= IOAT_VER_3_0) { err = ioat3_dma_probe(device, ioat_dca_enabled); - else + + if (device->version >= IOAT_VER_3_3) + pci_enable_pcie_error_reporting(pdev); + } else return -ENODEV; if (err) { dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n"); + pci_disable_pcie_error_reporting(pdev); return -ENODEV; } @@ -1297,6 +1379,8 @@ static void ioat_remove(struct pci_dev *pdev) free_dca_provider(device->dca); device->dca = NULL; } + + pci_disable_pcie_error_reporting(pdev); ioat_dma_remove(device); } From 240eb916076c8deb206c7e66d1ee9eb37d6a499a Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sun, 13 Sep 2015 14:15:19 +0200 Subject: [PATCH 04/77] dmaengine: drop null test before destroy functions Remove unneeded NULL test. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // @@ expression x; @@ -if (x != NULL) \(kmem_cache_destroy\|mempool_destroy\|dma_pool_destroy\)(x); // Signed-off-by: Julia Lawall Signed-off-by: Vinod Koul --- drivers/dma/dmaengine.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 3ff284c8e3d5..45df9a47c891 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -1066,11 +1066,9 @@ static void dmaengine_destroy_unmap_pool(void) for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) { struct dmaengine_unmap_pool *p = &unmap_pool[i]; - if (p->pool) - mempool_destroy(p->pool); + mempool_destroy(p->pool); p->pool = NULL; - if (p->cache) - kmem_cache_destroy(p->cache); + kmem_cache_destroy(p->cache); p->cache = NULL; } } From 9ab8b4e7cacfc4a03e4f39fe8a090436ce456720 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 21 Sep 2015 22:18:45 +0530 Subject: [PATCH 05/77] dmaengine: idma: rename to INTEL_IDMA64 the symbol CONFIG_IDMA64 should rather be CONFIG_INTEL_IDMA64 to conform to rest of the intel dmaengine drivers. This was found after sorting the entries and trying to place this odd one Suggested-by: Linus Torvalds Acked-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/Kconfig | 2 +- drivers/dma/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index b4584757dae0..5c931d45fdca 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -229,7 +229,7 @@ config IMX_SDMA Support the i.MX SDMA engine. This engine is integrated into Freescale i.MX25/31/35/51/53/6 chips. -config IDMA64 +config INTEL_IDMA64 tristate "Intel integrated DMA 64-bit support" select DMA_ENGINE select DMA_VIRTUAL_CHANNELS diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 7711a7180726..ef9c099bd2b6 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/ obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o obj-$(CONFIG_IMX_DMA) += imx-dma.o obj-$(CONFIG_IMX_SDMA) += imx-sdma.o -obj-$(CONFIG_IDMA64) += idma64.o +obj-$(CONFIG_INTEL_IDMA64) += idma64.o obj-$(CONFIG_INTEL_IOATDMA) += ioat/ obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o From 87b045969ad3fe021ccbd1ed88e7cb90adf4ca80 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:37 +0300 Subject: [PATCH 06/77] dmaengine: idma64: convert to __ffs() We replace __fls() by __ffs() since we have to find a *minimum* data width that satisfies both source and destination. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index 18c14e1f1414..13c52b87d59b 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -257,15 +257,15 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, dar = config->dst_addr; ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | IDMA64C_CTLL_FC_M2P; - src_width = min_t(u32, 2, __fls(sar | hw->len)); - dst_width = __fls(config->dst_addr_width); + src_width = min_t(u32, 2, __ffs(sar | hw->len)); + dst_width = __ffs(config->dst_addr_width); } else { /* DMA_DEV_TO_MEM */ sar = config->src_addr; dar = hw->phys; ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | IDMA64C_CTLL_FC_P2M; - src_width = __fls(config->src_addr_width); - dst_width = min_t(u32, 2, __fls(dar | hw->len)); + src_width = __ffs(config->src_addr_width); + dst_width = min_t(u32, 2, __ffs(dar | hw->len)); } lli->sar = sar; From 22b74406c5ac1829cd60f75c8c6a4ed1e0f4da03 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:38 +0300 Subject: [PATCH 07/77] dmaengine: idma64: useless use of min_t() We use a pattern x = min_t(u32, , __ffs(expr)); There is no need to use min_t() since we can replace it by x = __ffs(expr | <2^LOG2_CONST>); and moreover guarantee that argument of __ffs() will be not zero. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index 13c52b87d59b..e91e499b0d91 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -257,7 +257,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, dar = config->dst_addr; ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | IDMA64C_CTLL_FC_M2P; - src_width = min_t(u32, 2, __ffs(sar | hw->len)); + src_width = __ffs(sar | hw->len | 4); dst_width = __ffs(config->dst_addr_width); } else { /* DMA_DEV_TO_MEM */ sar = config->src_addr; @@ -265,7 +265,7 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | IDMA64C_CTLL_FC_P2M; src_width = __ffs(config->src_addr_width); - dst_width = min_t(u32, 2, __ffs(dar | hw->len)); + dst_width = __ffs(dar | hw->len | 4); } lli->sar = sar; From 581ec089a5476a9ddc8d0707e47315a2609297ad Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:39 +0300 Subject: [PATCH 08/77] dmaengine: idma64: this is not DesignWare This patch fixes a comment where DesignWare is wrongly mentioned. There is no functional change. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h index a4d99685a7c4..323c3f13ba2f 100644 --- a/drivers/dma/idma64.h +++ b/drivers/dma/idma64.h @@ -217,7 +217,7 @@ static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value) idma64_writel(idma64, IDMA64_##reg, (value)) /** - * struct idma64_chip - representation of DesignWare DMA controller hardware + * struct idma64_chip - representation of iDMA 64-bit controller hardware * @dev: struct device of the DMA controller * @irq: irq line * @regs: memory mapped I/O space From 2e9b55becc905207eb01e24bc282f8062cc497b5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:40 +0300 Subject: [PATCH 09/77] dmaengine: idma64: make better performance on pause / resume Accordingly to the documentation the CH_DRAIN bit enforses single bursts when channel is going to be suspended. This, in case when channel will be resumed, makes data to flow in non-optimal mode until DMA returns to full burst mode. The fix differentiates pause / resume cycle from pause / terminate and sets CH_DRAIN bit accordingly. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c index e91e499b0d91..39e6ab1d01fb 100644 --- a/drivers/dma/idma64.c +++ b/drivers/dma/idma64.c @@ -65,9 +65,6 @@ static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c) u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0); u32 cfglo = 0; - /* Enforce FIFO drain when channel is suspended */ - cfglo |= IDMA64C_CFGL_CH_DRAIN; - /* Set default burst alignment */ cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN; @@ -428,12 +425,17 @@ static int idma64_slave_config(struct dma_chan *chan, return 0; } -static void idma64_chan_deactivate(struct idma64_chan *idma64c) +static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain) { unsigned short count = 100; u32 cfglo; cfglo = channel_readl(idma64c, CFG_LO); + if (drain) + cfglo |= IDMA64C_CFGL_CH_DRAIN; + else + cfglo &= ~IDMA64C_CFGL_CH_DRAIN; + channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); do { udelay(1); @@ -456,7 +458,7 @@ static int idma64_pause(struct dma_chan *chan) spin_lock_irqsave(&idma64c->vchan.lock, flags); if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) { - idma64_chan_deactivate(idma64c); + idma64_chan_deactivate(idma64c, false); idma64c->desc->status = DMA_PAUSED; } spin_unlock_irqrestore(&idma64c->vchan.lock, flags); @@ -486,7 +488,7 @@ static int idma64_terminate_all(struct dma_chan *chan) LIST_HEAD(head); spin_lock_irqsave(&idma64c->vchan.lock, flags); - idma64_chan_deactivate(idma64c); + idma64_chan_deactivate(idma64c, true); idma64_stop_transfer(idma64c); if (idma64c->desc) { idma64_vdesc_free(&idma64c->desc->vdesc); From 97c37accd38f6136fa0abbdef01b5f864e91e6c7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 14 Sep 2015 11:55:41 +0300 Subject: [PATCH 10/77] dmaengine: idma64: use lo_hi_readq() / lo_hi_writeq() There are already helper functions to do 64-bit I/O on 32-bit machines, thus we don't need to reinvent the wheel. In our case we can't use readq() / writeq() even on 64-bit kernel since there is a hardware limitation (OCP bus is a 32-bit bus). Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/idma64.h | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h index 323c3f13ba2f..f6aeff0af8a5 100644 --- a/drivers/dma/idma64.h +++ b/drivers/dma/idma64.h @@ -16,6 +16,8 @@ #include #include +#include + #include "virt-dma.h" /* Channel registers */ @@ -166,19 +168,13 @@ static inline void idma64c_writel(struct idma64_chan *idma64c, int offset, static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset) { - u64 l, h; - - l = idma64c_readl(idma64c, offset); - h = idma64c_readl(idma64c, offset + 4); - - return l | (h << 32); + return lo_hi_readq(idma64c->regs + offset); } static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset, u64 value) { - idma64c_writel(idma64c, offset, value); - idma64c_writel(idma64c, offset + 4, value >> 32); + lo_hi_writeq(value, idma64c->regs + offset); } #define channel_readq(idma64c, reg) \ From ddfe4d0cce7828d79f3e3762c664342658c3f254 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 30 Sep 2015 12:06:36 +0530 Subject: [PATCH 11/77] dmaengine: edma: remove redundant conditions in edma_callback, driver was doing redundant check for desc, so remove that Reported-by: David Binderman Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 3e5d4f193005..558b0b4e7536 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -726,7 +726,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) edesc = echan->edesc; /* Pause the channel for non-cyclic */ - if (!edesc || (edesc && !edesc->cyclic)) + if (!edesc || !edesc->cyclic) edma_pause(echan->ch_num); switch (ch_status) { From aff1e0cee36ab679552846a18d15dcb6d2e3fc4c Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 4 Sep 2015 16:12:30 +0300 Subject: [PATCH 12/77] dmaengine: acpi: Use ACPI_COMPANION() instead of acpi_bus_get_device() Get pointer to the struct acpi_device by using ACPI_COMPANION() macro. This is more efficient than using ACPI_HANDLE() and acpi_bus_get_device(). Signed-off-by: Jarkko Nikula Acked-by: Rafael J. Wysocki Signed-off-by: Vinod Koul --- drivers/dma/acpi-dma.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/dma/acpi-dma.c b/drivers/dma/acpi-dma.c index 5a635646e05c..04257432c482 100644 --- a/drivers/dma/acpi-dma.c +++ b/drivers/dma/acpi-dma.c @@ -160,10 +160,8 @@ int acpi_dma_controller_register(struct device *dev, return -EINVAL; /* Check if the device was enumerated by ACPI */ - if (!ACPI_HANDLE(dev)) - return -EINVAL; - - if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev)) + adev = ACPI_COMPANION(dev); + if (!adev) return -EINVAL; adma = kzalloc(sizeof(*adma), GFP_KERNEL); @@ -358,10 +356,11 @@ struct dma_chan *acpi_dma_request_slave_chan_by_index(struct device *dev, int found; /* Check if the device was enumerated by ACPI */ - if (!dev || !ACPI_HANDLE(dev)) + if (!dev) return ERR_PTR(-ENODEV); - if (acpi_bus_get_device(ACPI_HANDLE(dev), &adev)) + adev = ACPI_COMPANION(dev); + if (!adev) return ERR_PTR(-ENODEV); memset(&pdata, 0, sizeof(pdata)); From 39416677b95bf1ab8bbfa229ec7e511c96ad5d0c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 28 Sep 2015 18:57:04 +0300 Subject: [PATCH 13/77] dmaengine: dw: convert to __ffs() We replace __fls() by __ffs() since we have to find a *minimum* data width that satisfies both source and destination. While here, rename dwc_fast_fls() to dwc_fast_ffs() which it really is. Fixes: 4c2d56c574db (dw_dmac: introduce dwc_fast_fls()) Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/dw/core.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index cf1c87fa1edd..46859f738fcf 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -163,7 +163,7 @@ static void dwc_initialize(struct dw_dma_chan *dwc) /*----------------------------------------------------------------------*/ -static inline unsigned int dwc_fast_fls(unsigned long long v) +static inline unsigned int dwc_fast_ffs(unsigned long long v) { /* * We can be a lot more clever here, but this should take care @@ -712,7 +712,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, dw->data_width[dwc->dst_master]); src_width = dst_width = min_t(unsigned int, data_width, - dwc_fast_fls(src | dest | len)); + dwc_fast_ffs(src | dest | len)); ctllo = DWC_DEFAULT_CTLLO(chan) | DWC_CTLL_DST_WIDTH(dst_width) @@ -791,7 +791,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, switch (direction) { case DMA_MEM_TO_DEV: - reg_width = __fls(sconfig->dst_addr_width); + reg_width = __ffs(sconfig->dst_addr_width); reg = sconfig->dst_addr; ctllo = (DWC_DEFAULT_CTLLO(chan) | DWC_CTLL_DST_WIDTH(reg_width) @@ -811,7 +811,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, len = sg_dma_len(sg); mem_width = min_t(unsigned int, - data_width, dwc_fast_fls(mem | len)); + data_width, dwc_fast_ffs(mem | len)); slave_sg_todev_fill_desc: desc = dwc_desc_get(dwc); @@ -848,7 +848,7 @@ slave_sg_todev_fill_desc: } break; case DMA_DEV_TO_MEM: - reg_width = __fls(sconfig->src_addr_width); + reg_width = __ffs(sconfig->src_addr_width); reg = sconfig->src_addr; ctllo = (DWC_DEFAULT_CTLLO(chan) | DWC_CTLL_SRC_WIDTH(reg_width) @@ -868,7 +868,7 @@ slave_sg_todev_fill_desc: len = sg_dma_len(sg); mem_width = min_t(unsigned int, - data_width, dwc_fast_fls(mem | len)); + data_width, dwc_fast_ffs(mem | len)); slave_sg_fromdev_fill_desc: desc = dwc_desc_get(dwc); From 6dbd80a919db24f5a1c66460838bb10ebe188d21 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 28 Sep 2015 18:57:05 +0300 Subject: [PATCH 14/77] dmaengine: dw: use dw_dmac autoconfiguration in PCI driver Instead of hardconding a platform data for dw_dmac let's use it's own autoconfiguration feature. Thus, remove hardcoded values. Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- drivers/dma/dw/pci.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c index b144706b3d85..4c30fdd092b3 100644 --- a/drivers/dma/dw/pci.c +++ b/drivers/dma/dw/pci.c @@ -15,12 +15,6 @@ #include "internal.h" -static struct dw_dma_platform_data dw_pci_pdata = { - .is_private = 1, - .chan_allocation_order = CHAN_ALLOCATION_ASCENDING, - .chan_priority = CHAN_PRIORITY_ASCENDING, -}; - static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { struct dw_dma_chip *chip; @@ -101,19 +95,19 @@ static const struct dev_pm_ops dw_pci_dev_pm_ops = { static const struct pci_device_id dw_pci_id_table[] = { /* Medfield */ - { PCI_VDEVICE(INTEL, 0x0827), (kernel_ulong_t)&dw_pci_pdata }, - { PCI_VDEVICE(INTEL, 0x0830), (kernel_ulong_t)&dw_pci_pdata }, + { PCI_VDEVICE(INTEL, 0x0827) }, + { PCI_VDEVICE(INTEL, 0x0830) }, /* BayTrail */ - { PCI_VDEVICE(INTEL, 0x0f06), (kernel_ulong_t)&dw_pci_pdata }, - { PCI_VDEVICE(INTEL, 0x0f40), (kernel_ulong_t)&dw_pci_pdata }, + { PCI_VDEVICE(INTEL, 0x0f06) }, + { PCI_VDEVICE(INTEL, 0x0f40) }, /* Braswell */ - { PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_pdata }, - { PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_pdata }, + { PCI_VDEVICE(INTEL, 0x2286) }, + { PCI_VDEVICE(INTEL, 0x22c0) }, /* Haswell */ - { PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_pdata }, + { PCI_VDEVICE(INTEL, 0x9c60) }, { } }; MODULE_DEVICE_TABLE(pci, dw_pci_id_table); From 49dfebebfb6811693a9e883423585f079b5941fa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 28 Sep 2015 18:57:07 +0300 Subject: [PATCH 15/77] avr32: use dw_dmac autoconfiguration Instead of hardcoding a platform data for dw_dmac let's use it's own autoconfiguration feature. Thus, remove hardcoded values. Tested on ATNGW100. Acked-by: Hans-Christian Egtvedt Signed-off-by: Andy Shevchenko Signed-off-by: Vinod Koul --- arch/avr32/mach-at32ap/at32ap700x.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index 1d8b147282cf..b4cb3bd89d8a 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -603,18 +603,11 @@ static void __init genclk_init_parent(struct clk *clk) clk->parent = parent; } -static struct dw_dma_platform_data dw_dmac0_data = { - .nr_channels = 3, - .block_size = 4095U, - .nr_masters = 2, - .data_width = { 2, 2 }, -}; - static struct resource dw_dmac0_resource[] = { PBMEM(0xff200000), IRQ(2), }; -DEFINE_DEV_DATA(dw_dmac, 0); +DEFINE_DEV(dw_dmac, 0); DEV_CLK(hclk, dw_dmac0, hsb, 10); /* -------------------------------------------------------------------- From 1a492ac2b87b05c8a175478e79d3c74511c74921 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 1 Oct 2015 07:11:48 +0530 Subject: [PATCH 16/77] dmaengine: zxdma: fix memset call Fix the call to memset in this driver [linux-4.2-next-20150911/drivers/dma/zx296702_dma.c:444]: (warning) memset() called to fill 0 bytes of 'ds'. Reported-by: David Binderman Signed-off-by: Vinod Koul --- drivers/dma/zx296702_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/zx296702_dma.c b/drivers/dma/zx296702_dma.c index 39915a6b7986..5c824f562f2b 100644 --- a/drivers/dma/zx296702_dma.c +++ b/drivers/dma/zx296702_dma.c @@ -441,7 +441,7 @@ static struct zx_dma_desc_sw *zx_alloc_desc_resource(int num, kfree(ds); return NULL; } - memset(ds->desc_hw, sizeof(struct zx_desc_hw) * num, 0); + memset(ds->desc_hw, 0, sizeof(struct zx_desc_hw) * num); ds->desc_num = num; return ds; } From 4e5385784e69e448efca0998aa188404d5e8d313 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 15 Sep 2015 15:29:27 +0200 Subject: [PATCH 17/77] dmaengine: at_xdmac: handle numf > 1 Handle 'numf > 1' case for interleaved mode. Signed-off-by: Maxime Ripard Signed-off-by: Ludovic Desroches Signed-off-by: Vinod Koul --- drivers/dma/at_xdmac.c | 112 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 58 deletions(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index a165b4bfd330..0190d1ca3004 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -929,13 +929,19 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, { struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); struct at_xdmac_desc *prev = NULL, *first = NULL; - struct data_chunk *chunk, *prev_chunk = NULL; dma_addr_t dst_addr, src_addr; - size_t dst_skip, src_skip, len = 0; - size_t prev_dst_icg = 0, prev_src_icg = 0; + size_t src_skip = 0, dst_skip = 0, len = 0; + struct data_chunk *chunk; int i; - if (!xt || (xt->numf != 1) || (xt->dir != DMA_MEM_TO_MEM)) + if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM)) + return NULL; + + /* + * TODO: Handle the case where we have to repeat a chain of + * descriptors... + */ + if ((xt->numf > 1) && (xt->frame_size > 1)) return NULL; dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n", @@ -945,66 +951,56 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, src_addr = xt->src_start; dst_addr = xt->dst_start; - for (i = 0; i < xt->frame_size; i++) { - struct at_xdmac_desc *desc; - size_t src_icg, dst_icg; + if (xt->numf > 1) { + first = at_xdmac_interleaved_queue_desc(chan, atchan, + NULL, + src_addr, dst_addr, + xt, xt->sgl); + for (i = 0; i < xt->numf; i++) + at_xdmac_increment_block_count(chan, first); + } else { + for (i = 0; i < xt->frame_size; i++) { + size_t src_icg = 0, dst_icg = 0; + struct at_xdmac_desc *desc; - chunk = xt->sgl + i; + chunk = xt->sgl + i; - dst_icg = dmaengine_get_dst_icg(xt, chunk); - src_icg = dmaengine_get_src_icg(xt, chunk); + dst_icg = dmaengine_get_dst_icg(xt, chunk); + src_icg = dmaengine_get_src_icg(xt, chunk); - src_skip = chunk->size + src_icg; - dst_skip = chunk->size + dst_icg; + src_skip = chunk->size + src_icg; + dst_skip = chunk->size + dst_icg; - dev_dbg(chan2dev(chan), - "%s: chunk size=%d, src icg=%d, dst icg=%d\n", - __func__, chunk->size, src_icg, dst_icg); - - /* - * Handle the case where we just have the same - * transfer to setup, we can just increase the - * block number and reuse the same descriptor. - */ - if (prev_chunk && prev && - (prev_chunk->size == chunk->size) && - (prev_src_icg == src_icg) && - (prev_dst_icg == dst_icg)) { dev_dbg(chan2dev(chan), - "%s: same configuration that the previous chunk, merging the descriptors...\n", - __func__); - at_xdmac_increment_block_count(chan, prev); - continue; + "%s: chunk size=%d, src icg=%d, dst icg=%d\n", + __func__, chunk->size, src_icg, dst_icg); + + desc = at_xdmac_interleaved_queue_desc(chan, atchan, + prev, + src_addr, dst_addr, + xt, chunk); + if (!desc) { + list_splice_init(&first->descs_list, + &atchan->free_descs_list); + return NULL; + } + + if (!first) + first = desc; + + dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + __func__, desc, first); + list_add_tail(&desc->desc_node, &first->descs_list); + + if (xt->src_sgl) + src_addr += src_skip; + + if (xt->dst_sgl) + dst_addr += dst_skip; + + len += chunk->size; + prev = desc; } - - desc = at_xdmac_interleaved_queue_desc(chan, atchan, - prev, - src_addr, dst_addr, - xt, chunk); - if (!desc) { - list_splice_init(&first->descs_list, - &atchan->free_descs_list); - return NULL; - } - - if (!first) - first = desc; - - dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", - __func__, desc, first); - list_add_tail(&desc->desc_node, &first->descs_list); - - if (xt->src_sgl) - src_addr += src_skip; - - if (xt->dst_sgl) - dst_addr += dst_skip; - - len += chunk->size; - prev_chunk = chunk; - prev_dst_icg = dst_icg; - prev_src_icg = src_icg; - prev = desc; } first->tx_dma_desc.cookie = -EBUSY; From 62b5cb757f1d6c875293958535952dd38ff9e675 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Tue, 15 Sep 2015 15:38:24 +0200 Subject: [PATCH 18/77] dmaengine: at_xdmac: fix memory leak in interleaved mode In interleaved mode, when numf > 1, we have only one descriptor for the transfer but this descriptor has to be added to the descs_list. If not, when doing remove_xfer, the descriptor won't be put back in the free_descs_list. Signed-off-by: Ludovic Desroches Signed-off-by: Vinod Koul --- drivers/dma/at_xdmac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index 0190d1ca3004..2ab6fe7339e6 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -958,6 +958,10 @@ at_xdmac_prep_interleaved(struct dma_chan *chan, xt, xt->sgl); for (i = 0; i < xt->numf; i++) at_xdmac_increment_block_count(chan, first); + + dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", + __func__, first, first); + list_add_tail(&first->desc_node, &first->descs_list); } else { for (i = 0; i < xt->frame_size; i++) { size_t src_icg = 0, dst_icg = 0; From 7522c2402aca2cb032ee1de7efde657491c3e4f5 Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 22:57:17 +0200 Subject: [PATCH 19/77] dmaengine: fsldma: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Signed-off-by: Vinod Koul --- drivers/dma/fsldma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 300f821f1890..2209f75fdf05 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c @@ -1512,6 +1512,7 @@ static const struct of_device_id fsldma_of_ids[] = { { .compatible = "fsl,elo-dma", }, {} }; +MODULE_DEVICE_TABLE(of, fsldma_of_ids); static struct platform_driver fsldma_of_driver = { .driver = { From 981ec2b248688968cd42734773add4c168326356 Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 22:57:51 +0200 Subject: [PATCH 20/77] dmaengine: moxart-dma: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Signed-off-by: Vinod Koul --- drivers/dma/moxart-dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/moxart-dma.c b/drivers/dma/moxart-dma.c index b4634109e010..631c4435e075 100644 --- a/drivers/dma/moxart-dma.c +++ b/drivers/dma/moxart-dma.c @@ -652,6 +652,7 @@ static const struct of_device_id moxart_dma_match[] = { { .compatible = "moxa,moxart-dma" }, { } }; +MODULE_DEVICE_TABLE(of, moxart_dma_match); static struct platform_driver moxart_driver = { .probe = moxart_probe, From 9ace300c98fd0b7280968195caaa7e7bbebefad1 Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 22:58:22 +0200 Subject: [PATCH 21/77] dmaengine: mpc512x: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Signed-off-by: Vinod Koul --- drivers/dma/mpc512x_dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c index e6281e7aa46e..aae76fb39adc 100644 --- a/drivers/dma/mpc512x_dma.c +++ b/drivers/dma/mpc512x_dma.c @@ -1073,6 +1073,7 @@ static const struct of_device_id mpc_dma_match[] = { { .compatible = "fsl,mpc8308-dma", }, {}, }; +MODULE_DEVICE_TABLE(of, mpc_dma_match); static struct platform_driver mpc_dma_driver = { .probe = mpc_dma_probe, From e0c26f22069e559b4c84dcc5060355e402f37744 Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 22:58:53 +0200 Subject: [PATCH 22/77] dmaengine: sirf: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Signed-off-by: Vinod Koul --- drivers/dma/sirf-dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/sirf-dma.c b/drivers/dma/sirf-dma.c index 7d5598d874e1..22ea2419ee56 100644 --- a/drivers/dma/sirf-dma.c +++ b/drivers/dma/sirf-dma.c @@ -1149,6 +1149,7 @@ static const struct of_device_id sirfsoc_dma_match[] = { { .compatible = "sirf,atlas7-dmac-v2", .data = &sirfsoc_dmadata_a7v2,}, {}, }; +MODULE_DEVICE_TABLE(of, sirfsoc_dma_match); static struct platform_driver sirfsoc_dma_driver = { .probe = sirfsoc_dma_probe, From c719d7fa81f18c9fd179f36c672d9648bd723504 Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 22:59:31 +0200 Subject: [PATCH 23/77] dmaengine: sun6i: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Acked-by: Maxime Ripard Signed-off-by: Vinod Koul --- drivers/dma/sun6i-dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 73e0be6e2100..2db12e493c53 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -908,6 +908,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, sun6i_dma_match); static int sun6i_dma_probe(struct platform_device *pdev) { From ad577e4642e7168f47146895db5791462b096c0f Mon Sep 17 00:00:00 2001 From: Luis de Bethencourt Date: Wed, 16 Sep 2015 23:00:17 +0200 Subject: [PATCH 24/77] dmaengine: xilinx: Fix module autoload for OF platform driver This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt Acked-by: Laurent Pinchart Acked-by: Moritz Fischer Signed-off-by: Vinod Koul --- drivers/dma/xilinx/xilinx_vdma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/xilinx/xilinx_vdma.c b/drivers/dma/xilinx/xilinx_vdma.c index d8434d465885..6f4b5017ca3b 100644 --- a/drivers/dma/xilinx/xilinx_vdma.c +++ b/drivers/dma/xilinx/xilinx_vdma.c @@ -1349,6 +1349,7 @@ static const struct of_device_id xilinx_vdma_of_ids[] = { { .compatible = "xlnx,axi-vdma-1.00.a",}, {} }; +MODULE_DEVICE_TABLE(of, xilinx_vdma_of_ids); static struct platform_driver xilinx_vdma_driver = { .driver = { From 9290a16cf19301224556bc7bcb913c0c2a45bb9a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 21 Aug 2015 11:48:37 +0000 Subject: [PATCH 25/77] dmaengine: OF DMAEngine API based on CONFIG_DMA_OF instead of CONFIG_OF 5fa422c ("dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c") moved OF base DMAEngine code to of-dma.c, then it based on CONFIG_DMA_OF. But, OF base DMAEngine API on of_dma.h still based on CONFIG_OF now. So, current kernel can't find OF base DMAEngine API if .config has CONFIG_OF, but not have CONFIG_DMA_OF. This patch tidyup it. Signed-off-by: Kuninori Morimoto Signed-off-by: Vinod Koul --- include/linux/of_dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/of_dma.h b/include/linux/of_dma.h index 98ba7525929e..36112cdd665a 100644 --- a/include/linux/of_dma.h +++ b/include/linux/of_dma.h @@ -34,7 +34,7 @@ struct of_dma_filter_info { dma_filter_fn filter_fn; }; -#ifdef CONFIG_OF +#ifdef CONFIG_DMA_OF extern int of_dma_controller_register(struct device_node *np, struct dma_chan *(*of_dma_xlate) (struct of_phandle_args *, struct of_dma *), From 47fac2415db653a79e005d4fa25948d3667b8e02 Mon Sep 17 00:00:00 2001 From: Misael Lopez Cruz Date: Mon, 14 Sep 2015 15:31:05 +0300 Subject: [PATCH 26/77] dmaengine: omap-dma: Enable packed accesses for cyclic transfers The L3 throughput can be higher than expected when packed access is not enabled. The ratio depends on the number of bytes in a transaction and the EMIF interface width. The throughput was measured for the following settings/cases: * Case 1: Burst size of 64 bytes, packed access disabled * Case 2: Burst size of 64 bytes, packed access enabled * Case 3: Burst disabled, packed access disabled Throughput measurements were done during McASP-based audio playback on the Jacinto6 EVM using the omapconf tool [1]: $ omapconf trace bw -m sdma_rd --------------------------------------------------------- Throughput (MB/s) Audio parameters Case 1 Case 2 Case 3 --------------------------------------------------------- 44.1kHz, 16-bits, stereo 1.41 0.18 1.41 44.1kHz, 32-bits, stereo 1.41 0.35 1.41 44.1kHz, 16-bits, 4-chan 2.82 0.35 2.82 44.1kHz, 16-bits, 6-chan 4.23 0.53 4.23 44.1kHz, 16-bits, 8-chan 5.64 0.71 5.64 --------------------------------------------------------- From above measurements, case 2 is the only one that delivers the expected throughput for the given audio parameters. For that reason, the packed accesses are now enabled. It's worth to mention that packed accesses cannot be enabled for all addressing modes. In cyclic transfers, it can be enabled in the source for MEM_TO_DEV and in dest for DEV_TO_MEM, as they use post-increment mode which supports packed accesses. Peter Ujfalusi: From the TRM regarding to this: "NOTE: Except in the constant addressing mode, the source or destination must be specified as packed for burst transactions to occur." So w/o the packed setting the burst on the MEM side was not enabled, this explains the numbers. [1] https://github.com/omapconf/omapconf Signed-off-by: Misael Lopez Cruz Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/omap-dma.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c index 249445c8a4c6..1dfc71c90123 100644 --- a/drivers/dma/omap-dma.c +++ b/drivers/dma/omap-dma.c @@ -935,8 +935,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( else d->ccr |= CCR_SYNC_ELEMENT; - if (dir == DMA_DEV_TO_MEM) + if (dir == DMA_DEV_TO_MEM) { d->ccr |= CCR_TRIGGER_SRC; + d->csdp |= CSDP_DST_PACKED; + } else { + d->csdp |= CSDP_SRC_PACKED; + } d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; From ce078af76faffc5353256ce487dbd85a6f1ad3a4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 3 Oct 2015 19:37:58 -0300 Subject: [PATCH 27/77] dmaengine: imx-sdma: Move message level to debug Since commit d078cd1b4185 ("dmaengine: imx-sdma: Add imx6sx platform support") we get this message on every boot on mx6q: imx-sdma 20ec000.sdma: no event needs to be remapped , which is not very helpful. Move the message to debug level instead. Cc: Zidan Wang Signed-off-by: Fabio Estevam Signed-off-by: Vinod Koul --- drivers/dma/imx-sdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 9d375bc7590a..b34b0a6d0cac 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -1478,7 +1478,7 @@ static int __init sdma_event_remap(struct sdma_engine *sdma) event_remap = of_find_property(np, propname, NULL); num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; if (!num_map) { - dev_warn(sdma->dev, "no event needs to be remapped\n"); + dev_dbg(sdma->dev, "no event needs to be remapped\n"); goto out; } else if (num_map % EVENT_REMAP_CELLS) { dev_err(sdma->dev, "the property %s must modulo %d\n", From 5ec9555ed065addc598244084c7e0e950b34890a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 3 Oct 2015 19:37:59 -0300 Subject: [PATCH 28/77] dmaengine: imx-sdma: Remove unneeded dev_info() There is no need to print that the driver has been initialized or removed, so remove such messages. Signed-off-by: Fabio Estevam Signed-off-by: Vinod Koul --- drivers/dma/imx-sdma.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index b34b0a6d0cac..7058d58ba588 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -1826,8 +1826,6 @@ static int sdma_probe(struct platform_device *pdev) of_node_put(spba_bus); } - dev_info(sdma->dev, "initialized\n"); - return 0; err_register: @@ -1852,7 +1850,6 @@ static int sdma_remove(struct platform_device *pdev) } platform_set_drvdata(pdev, NULL); - dev_info(&pdev->dev, "Removed...\n"); return 0; } From 696d8b70c09dd421c4d037fab04341e5b30585cf Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:43 +0300 Subject: [PATCH 29/77] ARM: common: edma: Fix channel parameter for irq callbacks In case when the interrupt happened for the second eDMA the channel number was incorrectly passed to the client driver. Signed-off-by: Peter Ujfalusi CC: Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 873dbfcc7dc9..56fc339571f9 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -406,7 +406,8 @@ static irqreturn_t dma_irq_handler(int irq, void *data) BIT(slot)); if (edma_cc[ctlr]->intr_data[channel].callback) edma_cc[ctlr]->intr_data[channel].callback( - channel, EDMA_DMA_COMPLETE, + EDMA_CTLR_CHAN(ctlr, channel), + EDMA_DMA_COMPLETE, edma_cc[ctlr]->intr_data[channel].data); } } while (sh_ipr); @@ -460,7 +461,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) if (edma_cc[ctlr]->intr_data[k]. callback) { edma_cc[ctlr]->intr_data[k]. - callback(k, + callback( + EDMA_CTLR_CHAN(ctlr, k), EDMA_DMA_CC_ERROR, edma_cc[ctlr]->intr_data [k].data); From d28c2b36d6027702585ca93773b3edd6e5f1a5bd Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:44 +0300 Subject: [PATCH 30/77] ARM: common: edma: Remove unused functions We no longer have users for these functions so they can be removed. Remove also unused enums from the header file. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 376 ----------------------------- include/linux/platform_data/edma.h | 33 --- 2 files changed, 409 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 56fc339571f9..e9c4cb16a47e 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -510,62 +510,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_HANDLED; } -static int reserve_contiguous_slots(int ctlr, unsigned int id, - unsigned int num_slots, - unsigned int start_slot) -{ - int i, j; - unsigned int count = num_slots; - int stop_slot = start_slot; - DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); - - for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { - j = EDMA_CHAN_SLOT(i); - if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { - /* Record our current beginning slot */ - if (count == num_slots) - stop_slot = i; - - count--; - set_bit(j, tmp_inuse); - - if (count == 0) - break; - } else { - clear_bit(j, tmp_inuse); - - if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { - stop_slot = i; - break; - } else { - count = num_slots; - } - } - } - - /* - * We have to clear any bits that we set - * if we run out parameter RAM slots, i.e we do find a set - * of contiguous parameter RAM slots but do not find the exact number - * requested as we may reach the total number of parameter RAM slots - */ - if (i == edma_cc[ctlr]->num_slots) - stop_slot = i; - - j = start_slot; - for_each_set_bit_from(j, tmp_inuse, stop_slot) - clear_bit(j, edma_cc[ctlr]->edma_inuse); - - if (count) - return -EBUSY; - - for (j = i - num_slots + 1; j <= i; ++j) - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), - &dummy_paramset, PARM_SIZE); - - return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); -} - static int prepare_unused_channel_list(struct device *dev, void *data) { struct platform_device *pdev = to_platform_device(dev); @@ -818,185 +762,10 @@ void edma_free_slot(unsigned slot) } EXPORT_SYMBOL(edma_free_slot); - -/** - * edma_alloc_cont_slots- alloc contiguous parameter RAM slots - * The API will return the starting point of a set of - * contiguous parameter RAM slots that have been requested - * - * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT - * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT - * @count: number of contiguous Paramter RAM slots - * @slot - the start value of Parameter RAM slot that should be passed if id - * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT - * - * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of - * contiguous Parameter RAM slots from parameter RAM 64 in the case of - * DaVinci SOCs and 32 in the case of DA8xx SOCs. - * - * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a - * set of contiguous parameter RAM slots from the "slot" that is passed as an - * argument to the API. - * - * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries - * starts looking for a set of contiguous parameter RAMs from the "slot" - * that is passed as an argument to the API. On failure the API will try to - * find a set of contiguous Parameter RAM slots from the remaining Parameter - * RAM slots - */ -int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) -{ - /* - * The start slot requested should be greater than - * the number of channels and lesser than the total number - * of slots - */ - if ((id != EDMA_CONT_PARAMS_ANY) && - (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots)) - return -EINVAL; - - /* - * The number of parameter RAM slots requested cannot be less than 1 - * and cannot be more than the number of slots minus the number of - * channels - */ - if (count < 1 || count > - (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) - return -EINVAL; - - switch (id) { - case EDMA_CONT_PARAMS_ANY: - return reserve_contiguous_slots(ctlr, id, count, - edma_cc[ctlr]->num_channels); - case EDMA_CONT_PARAMS_FIXED_EXACT: - case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: - return reserve_contiguous_slots(ctlr, id, count, slot); - default: - return -EINVAL; - } - -} -EXPORT_SYMBOL(edma_alloc_cont_slots); - -/** - * edma_free_cont_slots - deallocate DMA parameter RAM slots - * @slot: first parameter RAM of a set of parameter RAM slots to be freed - * @count: the number of contiguous parameter RAM slots to be freed - * - * This deallocates the parameter RAM slots allocated by - * edma_alloc_cont_slots. - * Callers/applications need to keep track of sets of contiguous - * parameter RAM slots that have been allocated using the edma_alloc_cont_slots - * API. - * Callers are responsible for ensuring the slots are inactive, and will - * not be activated. - */ -int edma_free_cont_slots(unsigned slot, int count) -{ - unsigned ctlr, slot_to_free; - int i; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots || - count < 1) - return -EINVAL; - - for (i = slot; i < slot + count; ++i) { - ctlr = EDMA_CTLR(i); - slot_to_free = EDMA_CHAN_SLOT(i); - - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), - &dummy_paramset, PARM_SIZE); - clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); - } - - return 0; -} -EXPORT_SYMBOL(edma_free_cont_slots); - /*-----------------------------------------------------------------------*/ /* Parameter RAM operations (i) -- read/write partial slots */ -/** - * edma_set_src - set initial DMA source address in parameter RAM slot - * @slot: parameter RAM slot being configured - * @src_port: physical address of source (memory, controller FIFO, etc) - * @addressMode: INCR, except in very rare cases - * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) - * - * Note that the source address is modified during the DMA transfer - * according to edma_set_src_index(). - */ -void edma_set_src(unsigned slot, dma_addr_t src_port, - enum address_mode mode, enum fifo_width width) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - - if (mode) { - /* set SAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); - } else { - /* clear SAM */ - i &= ~SAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - - /* set the source port address - in source register of param structure */ - edma_parm_write(ctlr, PARM_SRC, slot, src_port); - } -} -EXPORT_SYMBOL(edma_set_src); - -/** - * edma_set_dest - set initial DMA destination address in parameter RAM slot - * @slot: parameter RAM slot being configured - * @dest_port: physical address of destination (memory, controller FIFO, etc) - * @addressMode: INCR, except in very rare cases - * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) - * - * Note that the destination address is modified during the DMA transfer - * according to edma_set_dest_index(). - */ -void edma_set_dest(unsigned slot, dma_addr_t dest_port, - enum address_mode mode, enum fifo_width width) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - - if (mode) { - /* set DAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); - } else { - /* clear DAM */ - i &= ~DAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the destination port address - in dest register of param structure */ - edma_parm_write(ctlr, PARM_DST, slot, dest_port); - } -} -EXPORT_SYMBOL(edma_set_dest); - /** * edma_get_position - returns the current transfer point * @slot: parameter RAM slot being examined @@ -1016,110 +785,6 @@ dma_addr_t edma_get_position(unsigned slot, bool dst) return edma_read(ctlr, offs); } -/** - * edma_set_src_index - configure DMA source address indexing - * @slot: parameter RAM slot being configured - * @src_bidx: byte offset between source arrays in a frame - * @src_cidx: byte offset between source frames in a block - * - * Offsets are specified to support either contiguous or discontiguous - * memory transfers, or repeated access to a hardware register, as needed. - * When accessing hardware registers, both offsets are normally zero. - */ -void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0xffff0000, src_bidx); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0xffff0000, src_cidx); - } -} -EXPORT_SYMBOL(edma_set_src_index); - -/** - * edma_set_dest_index - configure DMA destination address indexing - * @slot: parameter RAM slot being configured - * @dest_bidx: byte offset between destination arrays in a frame - * @dest_cidx: byte offset between destination frames in a block - * - * Offsets are specified to support either contiguous or discontiguous - * memory transfers, or repeated access to a hardware register, as needed. - * When accessing hardware registers, both offsets are normally zero. - */ -void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0x0000ffff, dest_bidx << 16); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0x0000ffff, dest_cidx << 16); - } -} -EXPORT_SYMBOL(edma_set_dest_index); - -/** - * edma_set_transfer_params - configure DMA transfer parameters - * @slot: parameter RAM slot being configured - * @acnt: how many bytes per array (at least one) - * @bcnt: how many arrays per frame (at least one) - * @ccnt: how many frames per block (at least one) - * @bcnt_rld: used only for A-Synchronized transfers; this specifies - * the value to reload into bcnt when it decrements to zero - * @sync_mode: ASYNC or ABSYNC - * - * See the EDMA3 documentation to understand how to configure and link - * transfers using the fields in PaRAM slots. If you are not doing it - * all at once with edma_write_slot(), you will use this routine - * plus two calls each for source and destination, setting the initial - * address and saying how to index that address. - * - * An example of an A-Synchronized transfer is a serial link using a - * single word shift register. In that case, @acnt would be equal to - * that word size; the serial controller issues a DMA synchronization - * event to transfer each word, and memory access by the DMA transfer - * controller will be word-at-a-time. - * - * An example of an AB-Synchronized transfer is a device using a FIFO. - * In that case, @acnt equals the FIFO width and @bcnt equals its depth. - * The controller with the FIFO issues DMA synchronization events when - * the FIFO threshold is reached, and the DMA transfer controller will - * transfer one frame to (or from) the FIFO. It will probably use - * efficient burst modes to access memory. - */ -void edma_set_transfer_params(unsigned slot, - u16 acnt, u16 bcnt, u16 ccnt, - u16 bcnt_rld, enum sync_dimension sync_mode) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, - 0x0000ffff, bcnt_rld << 16); - if (sync_mode == ASYNC) - edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); - else - edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); - /* Set the acount, bcount, ccount registers */ - edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); - } -} -EXPORT_SYMBOL(edma_set_transfer_params); - /** * edma_link - link one parameter RAM slot to another * @from: parameter RAM slot originating the link @@ -1145,26 +810,6 @@ void edma_link(unsigned from, unsigned to) } EXPORT_SYMBOL(edma_link); -/** - * edma_unlink - cut link from one parameter RAM slot - * @from: parameter RAM slot originating the link - * - * The originating slot should not be part of any active DMA transfer. - * Its link is set to 0xffff. - */ -void edma_unlink(unsigned from) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); - - if (from >= edma_cc[ctlr]->num_slots) - return; - edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); -} -EXPORT_SYMBOL(edma_unlink); - /*-----------------------------------------------------------------------*/ /* Parameter RAM operations (ii) -- read/write whole parameter sets */ @@ -1401,27 +1046,6 @@ void edma_clean_channel(unsigned channel) } EXPORT_SYMBOL(edma_clean_channel); -/* - * edma_clear_event - clear an outstanding event on the DMA channel - * Arguments: - * channel - channel number - */ -void edma_clear_event(unsigned channel) -{ - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= edma_cc[ctlr]->num_channels) - return; - if (channel < 32) - edma_write(ctlr, EDMA_ECR, BIT(channel)); - else - edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); -} -EXPORT_SYMBOL(edma_clear_event); - /* * edma_assign_channel_eventq - move given channel to desired eventq * Arguments: diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index bdb2710e2aab..c1862423b356 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h @@ -72,20 +72,6 @@ struct edmacc_param { #define EDMA_DMA_TC1_ERROR 3 #define EDMA_DMA_TC2_ERROR 4 -enum address_mode { - INCR = 0, - FIFO = 1 -}; - -enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 -}; - enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, @@ -94,11 +80,6 @@ enum dma_event_q { EVENTQ_DEFAULT = -1 }; -enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 -}; - #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) #define EDMA_CTLR(i) ((i) >> 16) #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) @@ -121,22 +102,9 @@ void edma_free_channel(unsigned channel); int edma_alloc_slot(unsigned ctlr, int slot); void edma_free_slot(unsigned slot); -/* alloc/free a set of contiguous parameter RAM slots */ -int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count); -int edma_free_cont_slots(unsigned slot, int count); - /* calls that operate on part of a parameter RAM slot */ -void edma_set_src(unsigned slot, dma_addr_t src_port, - enum address_mode mode, enum fifo_width); -void edma_set_dest(unsigned slot, dma_addr_t dest_port, - enum address_mode mode, enum fifo_width); dma_addr_t edma_get_position(unsigned slot, bool dst); -void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); -void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); -void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, - u16 bcnt_rld, enum sync_dimension sync_mode); void edma_link(unsigned from, unsigned to); -void edma_unlink(unsigned from); /* calls that operate on an entire parameter RAM slot */ void edma_write_slot(unsigned slot, const struct edmacc_param *params); @@ -146,7 +114,6 @@ void edma_read_slot(unsigned slot, struct edmacc_param *params); int edma_start(unsigned channel); void edma_stop(unsigned channel); void edma_clean_channel(unsigned channel); -void edma_clear_event(unsigned channel); void edma_pause(unsigned channel); void edma_resume(unsigned channel); From 8fa7ff4fc01d7f43cd03143e4ec58323865bfacf Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:45 +0300 Subject: [PATCH 31/77] dmaengine: edma: Simplify and optimize the edma_execute path The code path in edma_execute() and edma_callback() can be simplified and make it more optimal. There is not need to call in to edma_execute() when the transfer has been finished for example. Also the handling of missed/first or next batch of paRAMs can be done in a more optimal way. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 76 ++++++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 47 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 3e5d4f193005..19fa49d6f555 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -154,15 +154,11 @@ static void edma_execute(struct edma_chan *echan) struct device *dev = echan->vchan.chan.device->dev; int i, j, left, nslots; - /* If either we processed all psets or we're still not started */ - if (!echan->edesc || - echan->edesc->pset_nr == echan->edesc->processed) { - /* Get next vdesc */ + if (!echan->edesc) { + /* Setup is needed for the first transfer */ vdesc = vchan_next_desc(&echan->vchan); - if (!vdesc) { - echan->edesc = NULL; + if (!vdesc) return; - } list_del(&vdesc->node); echan->edesc = to_edma_desc(&vdesc->tx); } @@ -220,7 +216,19 @@ static void edma_execute(struct edma_chan *echan) echan->ecc->dummy_slot); } - if (edesc->processed <= MAX_NR_SG) { + if (echan->missed) { + /* + * This happens due to setup times between intermediate + * transfers in long SG lists which have to be broken up into + * transfers of MAX_NR_SG + */ + dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); + edma_clean_channel(echan->ch_num); + edma_stop(echan->ch_num); + edma_start(echan->ch_num); + edma_trigger_channel(echan->ch_num); + echan->missed = 0; + } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); edma_start(echan->ch_num); @@ -229,20 +237,6 @@ static void edma_execute(struct edma_chan *echan) echan->ch_num, edesc->processed); edma_resume(echan->ch_num); } - - /* - * This happens due to setup times between intermediate transfers - * in long SG lists which have to be broken up into transfers of - * MAX_NR_SG - */ - if (echan->missed) { - dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(echan->ch_num); - edma_stop(echan->ch_num); - edma_start(echan->ch_num); - edma_trigger_channel(echan->ch_num); - echan->missed = 0; - } } static int edma_terminate_all(struct dma_chan *chan) @@ -259,20 +253,17 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - int cyclic = echan->edesc->cyclic; - + edma_stop(echan->ch_num); + /* Move the cyclic channel back to default queue */ + if (echan->edesc->cyclic) + edma_assign_channel_eventq(echan->ch_num, + EVENTQ_DEFAULT); /* * free the running request descriptor * since it is not in any of the vdesc lists */ edma_desc_free(&echan->edesc->vdesc); - echan->edesc = NULL; - edma_stop(echan->ch_num); - /* Move the cyclic channel back to default queue */ - if (cyclic) - edma_assign_channel_eventq(echan->ch_num, - EVENTQ_DEFAULT); } vchan_get_all_descriptors(&echan->vchan, &head); @@ -725,41 +716,33 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) edesc = echan->edesc; - /* Pause the channel for non-cyclic */ - if (!edesc || (edesc && !edesc->cyclic)) - edma_pause(echan->ch_num); - + spin_lock(&echan->vchan.lock); switch (ch_status) { case EDMA_DMA_COMPLETE: - spin_lock(&echan->vchan.lock); - if (edesc) { if (edesc->cyclic) { vchan_cyclic_callback(&edesc->vdesc); + goto out; } else if (edesc->processed == edesc->pset_nr) { dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); edesc->residue = 0; edma_stop(echan->ch_num); vchan_cookie_complete(&edesc->vdesc); - edma_execute(echan); + echan->edesc = NULL; } else { dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); + edma_pause(echan->ch_num); + /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; edesc->residue_stat = edesc->residue; edesc->processed_stat = edesc->processed; - - edma_execute(echan); } + edma_execute(echan); } - - spin_unlock(&echan->vchan.lock); - break; case EDMA_DMA_CC_ERROR: - spin_lock(&echan->vchan.lock); - edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); /* @@ -788,13 +771,12 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) edma_start(echan->ch_num); edma_trigger_channel(echan->ch_num); } - - spin_unlock(&echan->vchan.lock); - break; default: break; } +out: + spin_unlock(&echan->vchan.lock); } /* Alloc channel resources */ From d4cb7f404247173e2c760a01bf06fd1016a8b0d4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:46 +0300 Subject: [PATCH 32/77] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver Currently we have one device created to handle all (maximum 2) eDMAs in the system. With this change all eDMA instance will have it's own device/driver. This change is needed for further cleanups in the eDMA driver stack since the one device/driver to handle all eDMAs in the system was not flexible enough and prevents the upcoming work. Signed-off-by: Peter Ujfalusi Acked-by: Sekhar Nori Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 406 ++++++++++++-------------- arch/arm/mach-davinci/devices-da8xx.c | 110 +++---- arch/arm/mach-davinci/dm355.c | 21 +- arch/arm/mach-davinci/dm365.c | 25 +- arch/arm/mach-davinci/dm644x.c | 21 +- arch/arm/mach-davinci/dm646x.c | 27 +- 6 files changed, 259 insertions(+), 351 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index e9c4cb16a47e..7c2fe527e53b 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -235,6 +235,7 @@ static inline void clear_bits(int offset, int len, unsigned long *p) /* actual number of DMA channels and slots on this silicon */ struct edma { + struct device *dev; /* how many dma resources of each type */ unsigned num_channels; unsigned num_region; @@ -246,6 +247,7 @@ struct edma { const s8 *noevent; struct edma_soc_info *info; + int id; /* The edma_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. @@ -258,9 +260,6 @@ struct edma { */ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); - unsigned irq_res_start; - unsigned irq_res_end; - struct dma_interrupt_data { void (*callback)(unsigned channel, unsigned short ch_status, void *data); @@ -349,17 +348,6 @@ setup_dma_interrupt(unsigned lch, } } -static int irq2ctlr(int irq) -{ - if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) - return 0; - else if (irq >= edma_cc[1]->irq_res_start && - irq <= edma_cc[1]->irq_res_end) - return 1; - - return -1; -} - /****************************************************************************** * * DMA interrupt handler @@ -367,16 +355,17 @@ static int irq2ctlr(int irq) *****************************************************************************/ static irqreturn_t dma_irq_handler(int irq, void *data) { + struct edma *cc = data; int ctlr; u32 sh_ier; u32 sh_ipr; u32 bank; - ctlr = irq2ctlr(irq); + ctlr = cc->id; if (ctlr < 0) return IRQ_NONE; - dev_dbg(data, "dma_irq_handler\n"); + dev_dbg(cc->dev, "dma_irq_handler\n"); sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); if (!sh_ipr) { @@ -394,7 +383,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) u32 slot; u32 channel; - dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr); + dev_dbg(cc->dev, "IPR%d %08x\n", bank, sh_ipr); slot = __ffs(sh_ipr); sh_ipr &= ~(BIT(slot)); @@ -404,11 +393,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data) /* Clear the corresponding IPR bits */ edma_shadow0_write_array(ctlr, SH_ICR, bank, BIT(slot)); - if (edma_cc[ctlr]->intr_data[channel].callback) - edma_cc[ctlr]->intr_data[channel].callback( + if (cc->intr_data[channel].callback) + cc->intr_data[channel].callback( EDMA_CTLR_CHAN(ctlr, channel), EDMA_DMA_COMPLETE, - edma_cc[ctlr]->intr_data[channel].data); + cc->intr_data[channel].data); } } while (sh_ipr); @@ -423,15 +412,16 @@ static irqreturn_t dma_irq_handler(int irq, void *data) *****************************************************************************/ static irqreturn_t dma_ccerr_handler(int irq, void *data) { + struct edma *cc = data; int i; int ctlr; unsigned int cnt = 0; - ctlr = irq2ctlr(irq); + ctlr = cc->id; if (ctlr < 0) return IRQ_NONE; - dev_dbg(data, "dma_ccerr_handler\n"); + dev_dbg(cc->dev, "dma_ccerr_handler\n"); if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && @@ -446,8 +436,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) else if (edma_read_array(ctlr, EDMA_EMR, 1)) j = 1; if (j >= 0) { - dev_dbg(data, "EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); + dev_dbg(cc->dev, "EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; if (edma_read_array(ctlr, EDMA_EMR, j) & @@ -458,19 +448,16 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) /* Clear any SER */ edma_shadow0_write_array(ctlr, SH_SECR, j, BIT(i)); - if (edma_cc[ctlr]->intr_data[k]. - callback) { - edma_cc[ctlr]->intr_data[k]. - callback( - EDMA_CTLR_CHAN(ctlr, k), - EDMA_DMA_CC_ERROR, - edma_cc[ctlr]->intr_data - [k].data); + if (cc->intr_data[k].callback) { + cc->intr_data[k].callback( + EDMA_CTLR_CHAN(ctlr, k), + EDMA_DMA_CC_ERROR, + cc->intr_data[k].data); } } } } else if (edma_read(ctlr, EDMA_QEMR)) { - dev_dbg(data, "QEMR %02x\n", + dev_dbg(cc->dev, "QEMR %02x\n", edma_read(ctlr, EDMA_QEMR)); for (i = 0; i < 8; i++) { if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { @@ -483,7 +470,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) } } } else if (edma_read(ctlr, EDMA_CCERR)) { - dev_dbg(data, "CCERR %08x\n", + dev_dbg(cc->dev, "CCERR %08x\n", edma_read(ctlr, EDMA_CCERR)); /* FIXME: CCERR.BIT(16) ignored! much better * to just write CCERRCLR with CCERR value... @@ -1239,21 +1226,19 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, static int edma_probe(struct platform_device *pdev) { - struct edma_soc_info **info = pdev->dev.platform_data; - struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL}; + struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; - int i, j, off, ln, found = 0; - int status = -1; + int i, off, ln; const s16 (*rsv_chans)[2]; const s16 (*rsv_slots)[2]; const s16 (*xbar_chans)[2]; - int irq[EDMA_MAX_CC] = {0, 0}; - int err_irq[EDMA_MAX_CC] = {0, 0}; - struct resource *r[EDMA_MAX_CC] = {NULL}; - struct resource res[EDMA_MAX_CC]; - char res_name[10]; + int irq; + char *irq_name; + struct resource *mem; struct device_node *node = pdev->dev.of_node; struct device *dev = &pdev->dev; + int dev_id = pdev->id; + struct edma *cc; int ret; struct platform_device_info edma_dev_info = { .name = "edma-dma-engine", @@ -1261,6 +1246,17 @@ static int edma_probe(struct platform_device *pdev) .parent = &pdev->dev, }; + /* When booting with DT the pdev->id is -1 */ + if (dev_id < 0) + dev_id = arch_num_cc; + + if (dev_id >= EDMA_MAX_CC) { + dev_err(dev, + "eDMA3 with device id 0 and 1 is supported (id: %d)\n", + dev_id); + return -EINVAL; + } + if (node) { /* Check if this is a second instance registered */ if (arch_num_cc) { @@ -1268,13 +1264,11 @@ static int edma_probe(struct platform_device *pdev) return -ENODEV; } - ninfo[0] = edma_setup_info_from_dt(dev, node); - if (IS_ERR(ninfo[0])) { + info = edma_setup_info_from_dt(dev, node); + if (IS_ERR(info)) { dev_err(dev, "failed to get DT data\n"); - return PTR_ERR(ninfo[0]); + return PTR_ERR(info); } - - info = ninfo; } if (!info) @@ -1287,193 +1281,163 @@ static int edma_probe(struct platform_device *pdev) return ret; } - for (j = 0; j < EDMA_MAX_CC; j++) { - if (!info[j]) { - if (!found) - return -ENODEV; - break; + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); + if (!mem) { + dev_dbg(dev, "mem resource not found, using index 0\n"); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mem resource?\n"); + return -ENODEV; } - if (node) { - ret = of_address_to_resource(node, j, &res[j]); - if (!ret) - r[j] = &res[j]; - } else { - sprintf(res_name, "edma_cc%d", j); - r[j] = platform_get_resource_byname(pdev, - IORESOURCE_MEM, - res_name); - } - if (!r[j]) { - if (found) - break; - else - return -ENODEV; - } else { - found = 1; - } - - edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]); - if (IS_ERR(edmacc_regs_base[j])) - return PTR_ERR(edmacc_regs_base[j]); - - edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma), - GFP_KERNEL); - if (!edma_cc[j]) - return -ENOMEM; - - /* Get eDMA3 configuration from IP */ - ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j); - if (ret) - return ret; - - edma_cc[j]->default_queue = info[j]->default_queue; - - dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", - edmacc_regs_base[j]); - - for (i = 0; i < edma_cc[j]->num_slots; i++) - memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), - &dummy_paramset, PARM_SIZE); - - /* Mark all channels as unused */ - memset(edma_cc[j]->edma_unused, 0xff, - sizeof(edma_cc[j]->edma_unused)); - - if (info[j]->rsv) { - - /* Clear the reserved channels in unused list */ - rsv_chans = info[j]->rsv->rsv_chans; - if (rsv_chans) { - for (i = 0; rsv_chans[i][0] != -1; i++) { - off = rsv_chans[i][0]; - ln = rsv_chans[i][1]; - clear_bits(off, ln, - edma_cc[j]->edma_unused); - } - } - - /* Set the reserved slots in inuse list */ - rsv_slots = info[j]->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) { - off = rsv_slots[i][0]; - ln = rsv_slots[i][1]; - set_bits(off, ln, - edma_cc[j]->edma_inuse); - } - } - } - - /* Clear the xbar mapped channels in unused list */ - xbar_chans = info[j]->xbar_chans; - if (xbar_chans) { - for (i = 0; xbar_chans[i][1] != -1; i++) { - off = xbar_chans[i][1]; - clear_bits(off, 1, - edma_cc[j]->edma_unused); - } - } - - if (node) { - irq[j] = irq_of_parse_and_map(node, 0); - err_irq[j] = irq_of_parse_and_map(node, 2); - } else { - char irq_name[10]; - - sprintf(irq_name, "edma%d", j); - irq[j] = platform_get_irq_byname(pdev, irq_name); - - sprintf(irq_name, "edma%d_err", j); - err_irq[j] = platform_get_irq_byname(pdev, irq_name); - } - edma_cc[j]->irq_res_start = irq[j]; - edma_cc[j]->irq_res_end = err_irq[j]; - - status = devm_request_irq(dev, irq[j], dma_irq_handler, 0, - "edma", dev); - if (status < 0) { - dev_dbg(&pdev->dev, - "devm_request_irq %d failed --> %d\n", - irq[j], status); - return status; - } - - status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0, - "edma_error", dev); - if (status < 0) { - dev_dbg(&pdev->dev, - "devm_request_irq %d failed --> %d\n", - err_irq[j], status); - return status; - } - - for (i = 0; i < edma_cc[j]->num_channels; i++) - map_dmach_queue(j, i, info[j]->default_queue); - - queue_priority_mapping = info[j]->queue_priority_mapping; - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(j, - queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - /* Map the channel to param entry if channel mapping logic - * exist - */ - if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(j); - - for (i = 0; i < edma_cc[j]->num_region; i++) { - edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); - edma_write_array(j, EDMA_QRAE, i, 0x0); - } - edma_cc[j]->info = info[j]; - arch_num_cc++; - - edma_dev_info.id = j; - platform_device_register_full(&edma_dev_info); } + edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem); + if (IS_ERR(edmacc_regs_base[dev_id])) + return PTR_ERR(edmacc_regs_base[dev_id]); + + edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL); + if (!edma_cc[dev_id]) + return -ENOMEM; + + cc = edma_cc[dev_id]; + cc->dev = dev; + cc->id = dev_id; + dev_set_drvdata(dev, cc); + + /* Get eDMA3 configuration from IP */ + ret = edma_setup_from_hw(dev, info, cc, dev_id); + if (ret) + return ret; + + cc->default_queue = info->default_queue; + + dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]); + + for (i = 0; i < cc->num_slots; i++) + memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i), + &dummy_paramset, PARM_SIZE); + + /* Mark all channels as unused */ + memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused)); + + if (info->rsv) { + + /* Clear the reserved channels in unused list */ + rsv_chans = info->rsv->rsv_chans; + if (rsv_chans) { + for (i = 0; rsv_chans[i][0] != -1; i++) { + off = rsv_chans[i][0]; + ln = rsv_chans[i][1]; + clear_bits(off, ln, cc->edma_unused); + } + } + + /* Set the reserved slots in inuse list */ + rsv_slots = info->rsv->rsv_slots; + if (rsv_slots) { + for (i = 0; rsv_slots[i][0] != -1; i++) { + off = rsv_slots[i][0]; + ln = rsv_slots[i][1]; + set_bits(off, ln, cc->edma_inuse); + } + } + } + + /* Clear the xbar mapped channels in unused list */ + xbar_chans = info->xbar_chans; + if (xbar_chans) { + for (i = 0; xbar_chans[i][1] != -1; i++) { + off = xbar_chans[i][1]; + clear_bits(off, 1, cc->edma_unused); + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 0); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, + cc); + if (ret) { + dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 2); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, + cc); + if (ret) { + dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + for (i = 0; i < cc->num_channels; i++) + map_dmach_queue(dev_id, i, info->default_queue); + + queue_priority_mapping = info->queue_priority_mapping; + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(dev_id, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic exist */ + if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(dev_id); + + for (i = 0; i < cc->num_region; i++) { + edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0); + edma_write_array(dev_id, EDMA_QRAE, i, 0x0); + } + cc->info = info; + arch_num_cc++; + + edma_dev_info.id = dev_id; + + platform_device_register_full(&edma_dev_info); + return 0; } #ifdef CONFIG_PM_SLEEP static int edma_pm_resume(struct device *dev) { - int i, j; + struct edma *cc = dev_get_drvdata(dev); + int i; + s8 (*queue_priority_mapping)[2]; - for (j = 0; j < arch_num_cc; j++) { - struct edma *cc = edma_cc[j]; + queue_priority_mapping = cc->info->queue_priority_mapping; - s8 (*queue_priority_mapping)[2]; + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(cc->id, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); - queue_priority_mapping = cc->info->queue_priority_mapping; + /* Map the channel to param entry if channel mapping logic */ + if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(cc->id); - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(j, - queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); + for (i = 0; i < cc->num_channels; i++) { + if (test_bit(i, cc->edma_inuse)) { + /* ensure access through shadow region 0 */ + edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5, + BIT(i & 0x1f)); - /* - * Map the channel to param entry if channel mapping logic - * exist - */ - if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(j); - - for (i = 0; i < cc->num_channels; i++) { - if (test_bit(i, cc->edma_inuse)) { - /* ensure access through shadow region 0 */ - edma_or_array2(j, EDMA_DRAE, 0, i >> 5, - BIT(i & 0x1f)); - - setup_dma_interrupt(i, - cc->intr_data[i].callback, - cc->intr_data[i].data); - } + setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i), + cc->intr_data[i].callback, + cc->intr_data[i].data); } } diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 29e08aac8294..9ae049ae816a 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -147,150 +147,114 @@ static s8 da850_queue_priority_mapping[][2] = { {-1, -1} }; -static struct edma_soc_info da830_edma_cc0_info = { +static struct edma_soc_info da8xx_edma0_pdata = { .queue_priority_mapping = da8xx_queue_priority_mapping, .default_queue = EVENTQ_1, }; -static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { - &da830_edma_cc0_info, +static struct edma_soc_info da850_edma1_pdata = { + .queue_priority_mapping = da850_queue_priority_mapping, + .default_queue = EVENTQ_0, }; -static struct edma_soc_info da850_edma_cc_info[] = { +static struct resource da8xx_edma0_resources[] = { { - .queue_priority_mapping = da8xx_queue_priority_mapping, - .default_queue = EVENTQ_1, - }, - { - .queue_priority_mapping = da850_queue_priority_mapping, - .default_queue = EVENTQ_0, - }, -}; - -static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = { - &da850_edma_cc_info[0], - &da850_edma_cc_info[1], -}; - -static struct resource da830_edma_resources[] = { - { - .name = "edma_cc0", + .name = "edma3_cc", .start = DA8XX_TPCC_BASE, .end = DA8XX_TPCC_BASE + SZ_32K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc0", + .name = "edma3_tc0", .start = DA8XX_TPTC0_BASE, .end = DA8XX_TPTC0_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc1", + .name = "edma3_tc1", .start = DA8XX_TPTC1_BASE, .end = DA8XX_TPTC1_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", + .name = "edma3_ccint", .start = IRQ_DA8XX_CCINT0, .flags = IORESOURCE_IRQ, }, { - .name = "edma0_err", + .name = "edma3_ccerrint", .start = IRQ_DA8XX_CCERRINT, .flags = IORESOURCE_IRQ, }, }; -static struct resource da850_edma_resources[] = { +static struct resource da850_edma1_resources[] = { { - .name = "edma_cc0", - .start = DA8XX_TPCC_BASE, - .end = DA8XX_TPCC_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc0", - .start = DA8XX_TPTC0_BASE, - .end = DA8XX_TPTC0_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_tc1", - .start = DA8XX_TPTC1_BASE, - .end = DA8XX_TPTC1_BASE + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "edma_cc1", + .name = "edma3_cc", .start = DA850_TPCC1_BASE, .end = DA850_TPCC1_BASE + SZ_32K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc2", + .name = "edma3_tc0", .start = DA850_TPTC2_BASE, .end = DA850_TPTC2_BASE + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", - .start = IRQ_DA8XX_CCINT0, - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma0_err", - .start = IRQ_DA8XX_CCERRINT, - .flags = IORESOURCE_IRQ, - }, - { - .name = "edma1", + .name = "edma3_ccint", .start = IRQ_DA850_CCINT1, .flags = IORESOURCE_IRQ, }, { - .name = "edma1_err", + .name = "edma3_ccerrint", .start = IRQ_DA850_CCERRINT1, .flags = IORESOURCE_IRQ, }, }; -static struct platform_device da830_edma_device = { +static struct platform_device da8xx_edma0_device = { .name = "edma", - .id = -1, + .id = 0, .dev = { - .platform_data = da830_edma_info, + .platform_data = &da8xx_edma0_pdata, }, - .num_resources = ARRAY_SIZE(da830_edma_resources), - .resource = da830_edma_resources, + .num_resources = ARRAY_SIZE(da8xx_edma0_resources), + .resource = da8xx_edma0_resources, }; -static struct platform_device da850_edma_device = { +static struct platform_device da850_edma1_device = { .name = "edma", - .id = -1, + .id = 1, .dev = { - .platform_data = da850_edma_info, + .platform_data = &da850_edma1_pdata, }, - .num_resources = ARRAY_SIZE(da850_edma_resources), - .resource = da850_edma_resources, + .num_resources = ARRAY_SIZE(da850_edma1_resources), + .resource = da850_edma1_resources, }; int __init da830_register_edma(struct edma_rsv_info *rsv) { - da830_edma_cc0_info.rsv = rsv; + da8xx_edma0_pdata.rsv = rsv; - return platform_device_register(&da830_edma_device); + return platform_device_register(&da8xx_edma0_device); } int __init da850_register_edma(struct edma_rsv_info *rsv[2]) { + int ret; + if (rsv) { - da850_edma_cc_info[0].rsv = rsv[0]; - da850_edma_cc_info[1].rsv = rsv[1]; + da8xx_edma0_pdata.rsv = rsv[0]; + da850_edma1_pdata.rsv = rsv[1]; } - return platform_device_register(&da850_edma_device); + ret = platform_device_register(&da8xx_edma0_device); + if (ret) { + pr_warn("%s: Failed to register eDMA0\n", __func__); + return ret; + } + return platform_device_register(&da850_edma1_device); } static struct resource da8xx_i2c_resources0[] = { diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 567dc56fe8cd..a50bb9c66952 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -569,49 +569,44 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static s8 -queue_priority_mapping[][2] = { +static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, {1, 7}, {-1, -1}, }; -static struct edma_soc_info edma_cc0_info = { +static struct edma_soc_info dm355_edma_pdata = { .queue_priority_mapping = queue_priority_mapping, .default_queue = EVENTQ_1, }; -static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - static struct resource edma_resources[] = { { - .name = "edma_cc0", + .name = "edma3_cc", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc0", + .name = "edma3_tc0", .start = 0x01c10000, .end = 0x01c10000 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc1", + .name = "edma3_tc1", .start = 0x01c10400, .end = 0x01c10400 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", + .name = "edma3_ccint", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { - .name = "edma0_err", + .name = "edma3_ccerrint", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -621,7 +616,7 @@ static struct resource edma_resources[] = { static struct platform_device dm355_edma_device = { .name = "edma", .id = 0, - .dev.platform_data = dm355_edma_info, + .dev.platform_data = &dm355_edma_pdata, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6a890a8486d0..2068cbeaeb03 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -853,8 +853,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { }; /* Four Transfer Controllers on DM365 */ -static s8 -dm365_queue_priority_mapping[][2] = { +static s8 dm365_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 7}, {1, 7}, @@ -863,53 +862,49 @@ dm365_queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info edma_cc0_info = { +static struct edma_soc_info dm365_edma_pdata = { .queue_priority_mapping = dm365_queue_priority_mapping, .default_queue = EVENTQ_3, }; -static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - static struct resource edma_resources[] = { { - .name = "edma_cc0", + .name = "edma3_cc", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc0", + .name = "edma3_tc0", .start = 0x01c10000, .end = 0x01c10000 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc1", + .name = "edma3_tc1", .start = 0x01c10400, .end = 0x01c10400 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc2", + .name = "edma3_tc2", .start = 0x01c10800, .end = 0x01c10800 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc3", + .name = "edma3_tc3", .start = 0x01c10c00, .end = 0x01c10c00 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", + .name = "edma3_ccint", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { - .name = "edma0_err", + .name = "edma3_ccerrint", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -919,7 +914,7 @@ static struct resource edma_resources[] = { static struct platform_device dm365_edma_device = { .name = "edma", .id = 0, - .dev.platform_data = dm365_edma_info, + .dev.platform_data = &dm365_edma_pdata, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index dc52657909c4..d759ca8e58e8 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -498,49 +498,44 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ -static s8 -queue_priority_mapping[][2] = { +static s8 queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 3}, {1, 7}, {-1, -1}, }; -static struct edma_soc_info edma_cc0_info = { +static struct edma_soc_info dm644x_edma_pdata = { .queue_priority_mapping = queue_priority_mapping, .default_queue = EVENTQ_1, }; -static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - static struct resource edma_resources[] = { { - .name = "edma_cc0", + .name = "edma3_cc", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc0", + .name = "edma3_tc0", .start = 0x01c10000, .end = 0x01c10000 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc1", + .name = "edma3_tc1", .start = 0x01c10400, .end = 0x01c10400 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", + .name = "edma3_ccint", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { - .name = "edma0_err", + .name = "edma3_ccerrint", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -550,7 +545,7 @@ static struct resource edma_resources[] = { static struct platform_device dm644x_edma_device = { .name = "edma", .id = 0, - .dev.platform_data = dm644x_edma_info, + .dev.platform_data = &dm644x_edma_pdata, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 3f842bb266d6..219ebc8f674a 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -531,8 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { /*----------------------------------------------------------------------*/ /* Four Transfer Controllers on DM646x */ -static s8 -dm646x_queue_priority_mapping[][2] = { +static s8 dm646x_queue_priority_mapping[][2] = { /* {event queue no, Priority} */ {0, 4}, {1, 0}, @@ -541,53 +540,49 @@ dm646x_queue_priority_mapping[][2] = { {-1, -1}, }; -static struct edma_soc_info edma_cc0_info = { +static struct edma_soc_info dm646x_edma_pdata = { .queue_priority_mapping = dm646x_queue_priority_mapping, .default_queue = EVENTQ_1, }; -static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, -}; - static struct resource edma_resources[] = { { - .name = "edma_cc0", + .name = "edma3_cc", .start = 0x01c00000, .end = 0x01c00000 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc0", + .name = "edma3_tc0", .start = 0x01c10000, .end = 0x01c10000 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc1", + .name = "edma3_tc1", .start = 0x01c10400, .end = 0x01c10400 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc2", + .name = "edma3_tc2", .start = 0x01c10800, .end = 0x01c10800 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma_tc3", + .name = "edma3_tc3", .start = 0x01c10c00, .end = 0x01c10c00 + SZ_1K - 1, .flags = IORESOURCE_MEM, }, { - .name = "edma0", + .name = "edma3_ccint", .start = IRQ_CCINT0, .flags = IORESOURCE_IRQ, }, { - .name = "edma0_err", + .name = "edma3_ccerrint", .start = IRQ_CCERRINT, .flags = IORESOURCE_IRQ, }, @@ -597,7 +592,7 @@ static struct resource edma_resources[] = { static struct platform_device dm646x_edma_device = { .name = "edma", .id = 0, - .dev.platform_data = dm646x_edma_info, + .dev.platform_data = &dm646x_edma_pdata, .num_resources = ARRAY_SIZE(edma_resources), .resource = edma_resources, }; @@ -936,7 +931,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config, int __init dm646x_init_edma(struct edma_rsv_info *rsv) { - edma_cc0_info.rsv = rsv; + dm646x_edma_pdata.rsv = rsv; return platform_device_register(&dm646x_edma_device); } From dc9b60552f6a6a56b1defb88aa9f7f1498fcc045 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:47 +0300 Subject: [PATCH 33/77] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver If the of_dma_controller is registered in the non dmaengine driver we could have race condition: the of_dma_controller has been registered, but the dmaengine driver is not yet probed. Drivers requesting DMA channels during this window will fail since we do not yet have dmaengine drivers registered. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 10 ---------- drivers/dma/edma.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 7c2fe527e53b..d82fceda13a3 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -1191,10 +1190,6 @@ static int edma_of_parse_dt(struct device *dev, return ret; } -static struct of_dma_filter_info edma_filter_info = { - .filter_fn = edma_filter_fn, -}; - static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, struct device_node *node) { @@ -1209,11 +1204,6 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, if (ret) return ERR_PTR(ret); - dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); - dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); - of_dma_controller_register(dev->of_node, of_dma_simple_xlate, - &edma_filter_info); - return info; } #else diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 19fa49d6f555..fcb4680efed7 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -987,9 +988,14 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } +static struct of_dma_filter_info edma_filter_info = { + .filter_fn = edma_filter_fn, +}; + static int edma_probe(struct platform_device *pdev) { struct edma_cc *ecc; + struct device_node *parent_node = pdev->dev.parent->of_node; int ret; ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); @@ -1024,6 +1030,13 @@ static int edma_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ecc); + if (parent_node) { + dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); + dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); + of_dma_controller_register(parent_node, of_dma_simple_xlate, + &edma_filter_info); + } + dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); return 0; @@ -1037,7 +1050,10 @@ static int edma_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); + struct device_node *parent_node = pdev->dev.parent->of_node; + if (parent_node) + of_dma_controller_free(parent_node); dma_async_device_unregister(&ecc->dma_slave); edma_free_slot(ecc->dummy_slot); From 700c371913072fc891650a6dafacfd147ce805a7 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:48 +0300 Subject: [PATCH 34/77] ARM: common: edma: Internal API to use pointer to 'struct edma' Merge the iomem into the 'struct edma' and change the internal (static) functions to use pointer to the edma_cc instead of the ctlr number. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 478 ++++++++++++++++++++--------------------- 1 file changed, 236 insertions(+), 242 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index d82fceda13a3..0b4c0ee59ed9 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -114,127 +114,10 @@ #define EDMA_MAX_PARAMENTRY 512 /*****************************************************************************/ - -static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; - -static inline unsigned int edma_read(unsigned ctlr, int offset) -{ - return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); -} - -static inline void edma_write(unsigned ctlr, int offset, int val) -{ - __raw_writel(val, edmacc_regs_base[ctlr] + offset); -} -static inline void edma_modify(unsigned ctlr, int offset, unsigned and, - unsigned or) -{ - unsigned val = edma_read(ctlr, offset); - val &= and; - val |= or; - edma_write(ctlr, offset, val); -} -static inline void edma_and(unsigned ctlr, int offset, unsigned and) -{ - unsigned val = edma_read(ctlr, offset); - val &= and; - edma_write(ctlr, offset, val); -} -static inline void edma_or(unsigned ctlr, int offset, unsigned or) -{ - unsigned val = edma_read(ctlr, offset); - val |= or; - edma_write(ctlr, offset, val); -} -static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) -{ - return edma_read(ctlr, offset + (i << 2)); -} -static inline void edma_write_array(unsigned ctlr, int offset, int i, - unsigned val) -{ - edma_write(ctlr, offset + (i << 2), val); -} -static inline void edma_modify_array(unsigned ctlr, int offset, int i, - unsigned and, unsigned or) -{ - edma_modify(ctlr, offset + (i << 2), and, or); -} -static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) -{ - edma_or(ctlr, offset + (i << 2), or); -} -static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, - unsigned or) -{ - edma_or(ctlr, offset + ((i*2 + j) << 2), or); -} -static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, - unsigned val) -{ - edma_write(ctlr, offset + ((i*2 + j) << 2), val); -} -static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) -{ - return edma_read(ctlr, EDMA_SHADOW0 + offset); -} -static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, - int i) -{ - return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); -} -static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) -{ - edma_write(ctlr, EDMA_SHADOW0 + offset, val); -} -static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, - unsigned val) -{ - edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); -} -static inline unsigned int edma_parm_read(unsigned ctlr, int offset, - int param_no) -{ - return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); -} -static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, - unsigned val) -{ - edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); -} -static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, - unsigned and, unsigned or) -{ - edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); -} -static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, - unsigned and) -{ - edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); -} -static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, - unsigned or) -{ - edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); -} - -static inline void set_bits(int offset, int len, unsigned long *p) -{ - for (; len > 0; len--) - set_bit(offset + (len - 1), p); -} - -static inline void clear_bits(int offset, int len, unsigned long *p) -{ - for (; len > 0; len--) - clear_bit(offset + (len - 1), p); -} - -/*****************************************************************************/ - -/* actual number of DMA channels and slots on this silicon */ struct edma { struct device *dev; + void __iomem *base; + /* how many dma resources of each type */ unsigned num_channels; unsigned num_region; @@ -265,7 +148,122 @@ struct edma { void *data; } intr_data[EDMA_MAX_DMACH]; }; +/*****************************************************************************/ +static inline unsigned int edma_read(struct edma *cc, int offset) +{ + return (unsigned int)__raw_readl(cc->base + offset); +} + +static inline void edma_write(struct edma *cc, int offset, int val) +{ + __raw_writel(val, cc->base + offset); +} +static inline void edma_modify(struct edma *cc, int offset, unsigned and, + unsigned or) +{ + unsigned val = edma_read(cc, offset); + val &= and; + val |= or; + edma_write(cc, offset, val); +} +static inline void edma_and(struct edma *cc, int offset, unsigned and) +{ + unsigned val = edma_read(cc, offset); + val &= and; + edma_write(cc, offset, val); +} +static inline void edma_or(struct edma *cc, int offset, unsigned or) +{ + unsigned val = edma_read(cc, offset); + val |= or; + edma_write(cc, offset, val); +} +static inline unsigned int edma_read_array(struct edma *cc, int offset, int i) +{ + return edma_read(cc, offset + (i << 2)); +} +static inline void edma_write_array(struct edma *cc, int offset, int i, + unsigned val) +{ + edma_write(cc, offset + (i << 2), val); +} +static inline void edma_modify_array(struct edma *cc, int offset, int i, + unsigned and, unsigned or) +{ + edma_modify(cc, offset + (i << 2), and, or); +} +static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or) +{ + edma_or(cc, offset + (i << 2), or); +} +static inline void edma_or_array2(struct edma *cc, int offset, int i, int j, + unsigned or) +{ + edma_or(cc, offset + ((i*2 + j) << 2), or); +} +static inline void edma_write_array2(struct edma *cc, int offset, int i, int j, + unsigned val) +{ + edma_write(cc, offset + ((i*2 + j) << 2), val); +} +static inline unsigned int edma_shadow0_read(struct edma *cc, int offset) +{ + return edma_read(cc, EDMA_SHADOW0 + offset); +} +static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset, + int i) +{ + return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2)); +} +static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val) +{ + edma_write(cc, EDMA_SHADOW0 + offset, val); +} +static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i, + unsigned val) +{ + edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val); +} +static inline unsigned int edma_parm_read(struct edma *cc, int offset, + int param_no) +{ + return edma_read(cc, EDMA_PARM + offset + (param_no << 5)); +} +static inline void edma_parm_write(struct edma *cc, int offset, int param_no, + unsigned val) +{ + edma_write(cc, EDMA_PARM + offset + (param_no << 5), val); +} +static inline void edma_parm_modify(struct edma *cc, int offset, int param_no, + unsigned and, unsigned or) +{ + edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or); +} +static inline void edma_parm_and(struct edma *cc, int offset, int param_no, + unsigned and) +{ + edma_and(cc, EDMA_PARM + offset + (param_no << 5), and); +} +static inline void edma_parm_or(struct edma *cc, int offset, int param_no, + unsigned or) +{ + edma_or(cc, EDMA_PARM + offset + (param_no << 5), or); +} + +static inline void set_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + set_bit(offset + (len - 1), p); +} + +static inline void clear_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); +} + +/*****************************************************************************/ static struct edma *edma_cc[EDMA_MAX_CC]; static int arch_num_cc; @@ -282,26 +280,25 @@ static const struct of_device_id edma_of_ids[] = { /*****************************************************************************/ -static void map_dmach_queue(unsigned ctlr, unsigned ch_no, - enum dma_event_q queue_no) +static void map_dmach_queue(struct edma *cc, unsigned ch_no, + enum dma_event_q queue_no) { int bit = (ch_no & 0x7) * 4; /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) - queue_no = edma_cc[ctlr]->default_queue; + queue_no = cc->default_queue; queue_no &= 7; - edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), - ~(0x7 << bit), queue_no << bit); + edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); } -static void assign_priority_to_queue(unsigned ctlr, int queue_no, - int priority) +static void assign_priority_to_queue(struct edma *cc, int queue_no, + int priority) { int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), - ((priority & 0x7) << bit)); + edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } /** @@ -315,35 +312,30 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no, * included in that particular EDMA variant (Eg : dm646x) * */ -static void map_dmach_param(unsigned ctlr) +static void map_dmach_param(struct edma *cc) { int i; for (i = 0; i < EDMA_MAX_DMACH; i++) - edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); + edma_write_array(cc, EDMA_DCHMAP , i , (i << 5)); } -static inline void -setup_dma_interrupt(unsigned lch, +static inline void setup_dma_interrupt(struct edma *cc, unsigned lch, void (*callback)(unsigned channel, u16 ch_status, void *data), void *data) { - unsigned ctlr; - - ctlr = EDMA_CTLR(lch); lch = EDMA_CHAN_SLOT(lch); if (!callback) - edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(cc, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); - edma_cc[ctlr]->intr_data[lch].callback = callback; - edma_cc[ctlr]->intr_data[lch].data = data; + cc->intr_data[lch].callback = callback; + cc->intr_data[lch].data = data; if (callback) { - edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f)); + edma_shadow0_write_array(cc, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); } } @@ -366,15 +358,15 @@ static irqreturn_t dma_irq_handler(int irq, void *data) dev_dbg(cc->dev, "dma_irq_handler\n"); - sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); + sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0); if (!sh_ipr) { - sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); + sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1); if (!sh_ipr) return IRQ_NONE; - sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); + sh_ier = edma_shadow0_read_array(cc, SH_IER, 1); bank = 1; } else { - sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); + sh_ier = edma_shadow0_read_array(cc, SH_IER, 0); bank = 0; } @@ -390,8 +382,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) if (sh_ier & BIT(slot)) { channel = (bank << 5) | slot; /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ctlr, SH_ICR, bank, - BIT(slot)); + edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot)); if (cc->intr_data[channel].callback) cc->intr_data[channel].callback( EDMA_CTLR_CHAN(ctlr, channel), @@ -400,7 +391,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) } } while (sh_ipr); - edma_shadow0_write(ctlr, SH_IEVAL, 1); + edma_shadow0_write(cc, SH_IEVAL, 1); return IRQ_HANDLED; } @@ -422,30 +413,30 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) dev_dbg(cc->dev, "dma_ccerr_handler\n"); - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) + if ((edma_read_array(cc, EDMA_EMR, 0) == 0) && + (edma_read_array(cc, EDMA_EMR, 1) == 0) && + (edma_read(cc, EDMA_QEMR) == 0) && + (edma_read(cc, EDMA_CCERR) == 0)) return IRQ_NONE; while (1) { int j = -1; - if (edma_read_array(ctlr, EDMA_EMR, 0)) + if (edma_read_array(cc, EDMA_EMR, 0)) j = 0; - else if (edma_read_array(ctlr, EDMA_EMR, 1)) + else if (edma_read_array(cc, EDMA_EMR, 1)) j = 1; if (j >= 0) { dev_dbg(cc->dev, "EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); + edma_read_array(cc, EDMA_EMR, j)); for (i = 0; i < 32; i++) { int k = (j << 5) + i; - if (edma_read_array(ctlr, EDMA_EMR, j) & + if (edma_read_array(cc, EDMA_EMR, j) & BIT(i)) { /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, - BIT(i)); + edma_write_array(cc, EDMA_EMCR, j, + BIT(i)); /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, + edma_shadow0_write_array(cc, SH_SECR, j, BIT(i)); if (cc->intr_data[k].callback) { cc->intr_data[k].callback( @@ -455,44 +446,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) } } } - } else if (edma_read(ctlr, EDMA_QEMR)) { + } else if (edma_read(cc, EDMA_QEMR)) { dev_dbg(cc->dev, "QEMR %02x\n", - edma_read(ctlr, EDMA_QEMR)); + edma_read(cc, EDMA_QEMR)); for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { + if (edma_read(cc, EDMA_QEMR) & BIT(i)) { /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ctlr, SH_QSECR, - BIT(i)); + edma_write(cc, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(cc, SH_QSECR, + BIT(i)); /* NOTE: not reported!! */ } } - } else if (edma_read(ctlr, EDMA_CCERR)) { + } else if (edma_read(cc, EDMA_CCERR)) { dev_dbg(cc->dev, "CCERR %08x\n", - edma_read(ctlr, EDMA_CCERR)); + edma_read(cc, EDMA_CCERR)); /* FIXME: CCERR.BIT(16) ignored! much better * to just write CCERRCLR with CCERR value... */ for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { + if (edma_read(cc, EDMA_CCERR) & BIT(i)) { /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); + edma_write(cc, EDMA_CCERRCLR, BIT(i)); /* NOTE: not reported!! */ } } } - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) + if ((edma_read_array(cc, EDMA_EMR, 0) == 0) && + (edma_read_array(cc, EDMA_EMR, 1) == 0) && + (edma_read(cc, EDMA_QEMR) == 0) && + (edma_read(cc, EDMA_CCERR) == 0)) break; cnt++; if (cnt > 10) break; } - edma_write(ctlr, EDMA_EEVAL, 1); + edma_write(cc, EDMA_EEVAL, 1); return IRQ_HANDLED; } @@ -629,18 +620,19 @@ int edma_alloc_channel(int channel, } /* ensure access through shadow region 0 */ - edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); /* ensure no events are pending */ edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), - &dummy_paramset, PARM_SIZE); + memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset, + PARM_SIZE); if (callback) - setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), - callback, data); + setup_dma_interrupt(edma_cc[ctlr], + EDMA_CTLR_CHAN(ctlr, channel), callback, + data); - map_dmach_queue(ctlr, channel, eventq_no); + map_dmach_queue(edma_cc[ctlr], channel, eventq_no); return EDMA_CTLR_CHAN(ctlr, channel); } @@ -668,11 +660,11 @@ void edma_free_channel(unsigned channel) if (channel >= edma_cc[ctlr]->num_channels) return; - setup_dma_interrupt(channel, NULL, NULL); + setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), - &dummy_paramset, PARM_SIZE); + memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset, + PARM_SIZE); clear_bit(channel, edma_cc[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_channel); @@ -716,8 +708,8 @@ int edma_alloc_slot(unsigned ctlr, int slot) return -EBUSY; } - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), - &dummy_paramset, PARM_SIZE); + memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset, + PARM_SIZE); return EDMA_CTLR_CHAN(ctlr, slot); } @@ -742,8 +734,8 @@ void edma_free_slot(unsigned slot) slot >= edma_cc[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), - &dummy_paramset, PARM_SIZE); + memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset, + PARM_SIZE); clear_bit(slot, edma_cc[ctlr]->edma_inuse); } EXPORT_SYMBOL(edma_free_slot); @@ -768,7 +760,7 @@ dma_addr_t edma_get_position(unsigned slot, bool dst) offs = PARM_OFFSET(slot); offs += dst ? PARM_DST : PARM_SRC; - return edma_read(ctlr, offs); + return edma_read(edma_cc[ctlr], offs); } /** @@ -791,7 +783,7 @@ void edma_link(unsigned from, unsigned to) return; if (to >= edma_cc[ctlr_to]->num_slots) return; - edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to)); } EXPORT_SYMBOL(edma_link); @@ -819,8 +811,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) if (slot >= edma_cc[ctlr]->num_slots) return; - memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, - PARM_SIZE); + memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE); } EXPORT_SYMBOL(edma_write_slot); @@ -841,8 +832,8 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) if (slot >= edma_cc[ctlr]->num_slots) return; - memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), - PARM_SIZE); + memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot), + PARM_SIZE); } EXPORT_SYMBOL(edma_read_slot); @@ -867,7 +858,8 @@ void edma_pause(unsigned channel) if (channel < edma_cc[ctlr]->num_channels) { unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); + edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5, + mask); } } EXPORT_SYMBOL(edma_pause); @@ -888,7 +880,8 @@ void edma_resume(unsigned channel) if (channel < edma_cc[ctlr]->num_channels) { unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); + edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5, + mask); } } EXPORT_SYMBOL(edma_resume); @@ -902,10 +895,11 @@ int edma_trigger_channel(unsigned channel) channel = EDMA_CHAN_SLOT(channel); mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask); + edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask); pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5))); + edma_shadow0_read_array(edma_cc[ctlr], SH_ESR, + (channel >> 5))); return 0; } EXPORT_SYMBOL(edma_trigger_channel); @@ -929,28 +923,29 @@ int edma_start(unsigned channel) channel = EDMA_CHAN_SLOT(channel); if (channel < edma_cc[ctlr]->num_channels) { + struct edma *cc = edma_cc[ctlr]; int j = channel >> 5; unsigned int mask = BIT(channel & 0x1f); /* EDMA channels without event association */ - if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { + if (test_bit(channel, cc->edma_unused)) { pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ESR, j)); - edma_shadow0_write_array(ctlr, SH_ESR, j, mask); + edma_shadow0_read_array(cc, SH_ESR, j)); + edma_shadow0_write_array(cc, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ER, j)); + edma_shadow0_read_array(cc, SH_ER, j)); /* Clear any pending event or error */ - edma_write_array(ctlr, EDMA_ECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_write_array(cc, EDMA_ECR, j, mask); + edma_write_array(cc, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_shadow0_write_array(ctlr, SH_EESR, j, mask); + edma_shadow0_write_array(cc, SH_SECR, j, mask); + edma_shadow0_write_array(cc, SH_EESR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); + edma_shadow0_read_array(cc, SH_EER, j)); return 0; } @@ -975,19 +970,20 @@ void edma_stop(unsigned channel) channel = EDMA_CHAN_SLOT(channel); if (channel < edma_cc[ctlr]->num_channels) { + struct edma *cc = edma_cc[ctlr]; int j = channel >> 5; unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, j, mask); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_shadow0_write_array(cc, SH_EECR, j, mask); + edma_shadow0_write_array(cc, SH_ECR, j, mask); + edma_shadow0_write_array(cc, SH_SECR, j, mask); + edma_write_array(cc, EDMA_EMCR, j, mask); /* clear possibly pending completion interrupt */ - edma_shadow0_write_array(ctlr, SH_ICR, j, mask); + edma_shadow0_write_array(cc, SH_ICR, j, mask); pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); + edma_shadow0_read_array(cc, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -1017,17 +1013,18 @@ void edma_clean_channel(unsigned channel) channel = EDMA_CHAN_SLOT(channel); if (channel < edma_cc[ctlr]->num_channels) { + struct edma *cc = edma_cc[ctlr]; int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_read_array(cc, EDMA_EMR, j)); + edma_shadow0_write_array(cc, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_write_array(cc, EDMA_EMCR, j, mask); /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + edma_shadow0_write_array(cc, SH_SECR, j, mask); + edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } } EXPORT_SYMBOL(edma_clean_channel); @@ -1056,7 +1053,7 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no) if (eventq_no >= edma_cc[ctlr]->num_tc) return; - map_dmach_queue(ctlr, channel, eventq_no); + map_dmach_queue(edma_cc[ctlr], channel, eventq_no); } EXPORT_SYMBOL(edma_assign_channel_eventq); @@ -1068,7 +1065,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, s8 (*queue_priority_map)[2]; /* Decode the eDMA3 configuration from CCCFG register */ - cccfg = edma_read(cc_id, EDMA_CCCFG); + cccfg = edma_read(edma_cc, EDMA_CCCFG); value = GET_NUM_REGN(cccfg); edma_cc->num_region = BIT(value); @@ -1281,10 +1278,6 @@ static int edma_probe(struct platform_device *pdev) } } - edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem); - if (IS_ERR(edmacc_regs_base[dev_id])) - return PTR_ERR(edmacc_regs_base[dev_id]); - edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL); if (!edma_cc[dev_id]) return -ENOMEM; @@ -1294,6 +1287,10 @@ static int edma_probe(struct platform_device *pdev) cc->id = dev_id; dev_set_drvdata(dev, cc); + cc->base = devm_ioremap_resource(dev, mem); + if (IS_ERR(cc->base)) + return PTR_ERR(cc->base); + /* Get eDMA3 configuration from IP */ ret = edma_setup_from_hw(dev, info, cc, dev_id); if (ret) @@ -1301,11 +1298,9 @@ static int edma_probe(struct platform_device *pdev) cc->default_queue = info->default_queue; - dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]); - for (i = 0; i < cc->num_slots; i++) - memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i), - &dummy_paramset, PARM_SIZE); + memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset, + PARM_SIZE); /* Mark all channels as unused */ memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused)); @@ -1373,23 +1368,23 @@ static int edma_probe(struct platform_device *pdev) } for (i = 0; i < cc->num_channels; i++) - map_dmach_queue(dev_id, i, info->default_queue); + map_dmach_queue(cc, i, info->default_queue); queue_priority_mapping = info->queue_priority_mapping; /* Event queue priority mapping */ for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(dev_id, queue_priority_mapping[i][0], + assign_priority_to_queue(cc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic exist */ - if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(dev_id); + if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(cc); for (i = 0; i < cc->num_region; i++) { - edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0); - edma_write_array(dev_id, EDMA_QRAE, i, 0x0); + edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0); + edma_write_array(cc, EDMA_QRAE, i, 0x0); } cc->info = info; arch_num_cc++; @@ -1412,20 +1407,19 @@ static int edma_pm_resume(struct device *dev) /* Event queue priority mapping */ for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(cc->id, queue_priority_mapping[i][0], + assign_priority_to_queue(cc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic */ - if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(cc->id); + if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(cc); for (i = 0; i < cc->num_channels; i++) { if (test_bit(i, cc->edma_inuse)) { /* ensure access through shadow region 0 */ - edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5, - BIT(i & 0x1f)); + edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); - setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i), + setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i), cc->intr_data[i].callback, cc->intr_data[i].data); } From ca304fa9bb762f091e851d48de43f623c975d47a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:49 +0300 Subject: [PATCH 35/77] ARM/dmaengine: edma: Public API to use private struct pointer Instead of relying on indexes pointing to edma private date in the global pointer array, pass the private data pointer via the public API. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 305 ++++++++++++++--------------- drivers/dma/edma.c | 79 ++++---- include/linux/platform_data/edma.h | 38 ++-- 3 files changed, 214 insertions(+), 208 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 0b4c0ee59ed9..03692520812a 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -130,7 +130,7 @@ struct edma { struct edma_soc_info *info; int id; - + bool unused_chan_list_done; /* The edma_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ @@ -264,7 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p) } /*****************************************************************************/ -static struct edma *edma_cc[EDMA_MAX_CC]; static int arch_num_cc; /* dummy param set used to (re)initialize parameter RAM slots */ @@ -490,14 +489,18 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) static int prepare_unused_channel_list(struct device *dev, void *data) { struct platform_device *pdev = to_platform_device(dev); - int i, count, ctlr; + struct edma *cc = data; + int i, count; struct of_phandle_args dma_spec; if (dev->of_node) { + struct platform_device *dma_pdev; + count = of_property_count_strings(dev->of_node, "dma-names"); if (count < 0) return 0; for (i = 0; i < count; i++) { + if (of_parse_phandle_with_args(dev->of_node, "dmas", "#dma-cells", i, &dma_spec)) @@ -508,8 +511,12 @@ static int prepare_unused_channel_list(struct device *dev, void *data) continue; } + dma_pdev = of_find_device_by_node(dma_spec.np); + if (&dma_pdev->dev != cc->dev) + continue; + clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - edma_cc[0]->edma_unused); + cc->edma_unused); of_node_put(dma_spec.np); } return 0; @@ -517,11 +524,11 @@ static int prepare_unused_channel_list(struct device *dev, void *data) /* For non-OF case */ for (i = 0; i < pdev->num_resources; i++) { - if ((pdev->resource[i].flags & IORESOURCE_DMA) && - (int)pdev->resource[i].start >= 0) { - ctlr = EDMA_CTLR(pdev->resource[i].start); + struct resource *res = &pdev->resource[i]; + + if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - edma_cc[ctlr]->edma_unused); + cc->edma_unused); } } @@ -530,8 +537,6 @@ static int prepare_unused_channel_list(struct device *dev, void *data) /*-----------------------------------------------------------------------*/ -static bool unused_chan_list_done; - /* Resource alloc/free: dma channels, parameter RAM slots */ /** @@ -564,77 +569,73 @@ static bool unused_chan_list_done; * * Returns the number of the channel, else negative errno. */ -int edma_alloc_channel(int channel, +int edma_alloc_channel(struct edma *cc, int channel, void (*callback)(unsigned channel, u16 ch_status, void *data), void *data, enum dma_event_q eventq_no) { - unsigned i, done = 0, ctlr = 0; + unsigned done = 0; int ret = 0; - if (!unused_chan_list_done) { + if (!cc->unused_chan_list_done) { /* * Scan all the platform devices to find out the EDMA channels * used and clear them in the unused list, making the rest * available for ARM usage. */ - ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, - prepare_unused_channel_list); + ret = bus_for_each_dev(&platform_bus_type, NULL, cc, + prepare_unused_channel_list); if (ret < 0) return ret; - unused_chan_list_done = true; + cc->unused_chan_list_done = true; } if (channel >= 0) { - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", + __func__, cc->id, EDMA_CTLR(channel)); + return -EINVAL; + } channel = EDMA_CHAN_SLOT(channel); } if (channel < 0) { - for (i = 0; i < arch_num_cc; i++) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_cc[i]->edma_unused, - edma_cc[i]->num_channels, - channel); - if (channel == edma_cc[i]->num_channels) - break; - if (!test_and_set_bit(channel, - edma_cc[i]->edma_inuse)) { - done = 1; - ctlr = i; - break; - } - channel++; - } - if (done) + channel = 0; + for (;;) { + channel = find_next_bit(cc->edma_unused, + cc->num_channels, channel); + if (channel == cc->num_channels) break; + if (!test_and_set_bit(channel, cc->edma_inuse)) { + done = 1; + break; + } + channel++; } if (!done) return -ENOMEM; - } else if (channel >= edma_cc[ctlr]->num_channels) { + } else if (channel >= cc->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { + } else if (test_and_set_bit(channel, cc->edma_inuse)) { return -EBUSY; } /* ensure access through shadow region 0 */ - edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); /* ensure no events are pending */ - edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); - memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset, + edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel)); + memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); if (callback) - setup_dma_interrupt(edma_cc[ctlr], - EDMA_CTLR_CHAN(ctlr, channel), callback, - data); + setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel), + callback, data); - map_dmach_queue(edma_cc[ctlr], channel, eventq_no); + map_dmach_queue(cc, channel, eventq_no); - return EDMA_CTLR_CHAN(ctlr, channel); + return EDMA_CTLR_CHAN(cc->id, channel); } EXPORT_SYMBOL(edma_alloc_channel); @@ -650,22 +651,25 @@ EXPORT_SYMBOL(edma_alloc_channel); * will not be reactivated by linking, chaining, or software calls to * edma_start(). */ -void edma_free_channel(unsigned channel) +void edma_free_channel(struct edma *cc, unsigned channel) { - unsigned ctlr; - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) + if (channel >= cc->num_channels) return; - setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL); + setup_dma_interrupt(cc, channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset, + memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_cc[ctlr]->edma_inuse); + clear_bit(channel, cc->edma_inuse); } EXPORT_SYMBOL(edma_free_channel); @@ -683,35 +687,29 @@ EXPORT_SYMBOL(edma_free_channel); * * Returns the number of the slot, else negative errno. */ -int edma_alloc_slot(unsigned ctlr, int slot) +int edma_alloc_slot(struct edma *cc, int slot) { - if (!edma_cc[ctlr]) - return -EINVAL; - - if (slot >= 0) + if (slot > 0) slot = EDMA_CHAN_SLOT(slot); - if (slot < 0) { - slot = edma_cc[ctlr]->num_channels; + slot = cc->num_channels; for (;;) { - slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, - edma_cc[ctlr]->num_slots, slot); - if (slot == edma_cc[ctlr]->num_slots) + slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots, + slot); + if (slot == cc->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) + if (!test_and_set_bit(slot, cc->edma_inuse)) break; } - } else if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) { + } else if (slot < cc->num_channels || slot >= cc->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { + } else if (test_and_set_bit(slot, cc->edma_inuse)) { return -EBUSY; } - memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset, - PARM_SIZE); + memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - return EDMA_CTLR_CHAN(ctlr, slot); + return slot; } EXPORT_SYMBOL(edma_alloc_slot); @@ -723,20 +721,15 @@ EXPORT_SYMBOL(edma_alloc_slot); * Callers are responsible for ensuring the slot is inactive, and will * not be activated. */ -void edma_free_slot(unsigned slot) +void edma_free_slot(struct edma *cc, unsigned slot) { - unsigned ctlr; - ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) + if (slot < cc->num_channels || slot >= cc->num_slots) return; - memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset, - PARM_SIZE); - clear_bit(slot, edma_cc[ctlr]->edma_inuse); + memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); + clear_bit(slot, cc->edma_inuse); } EXPORT_SYMBOL(edma_free_slot); @@ -751,16 +744,15 @@ EXPORT_SYMBOL(edma_free_slot); * * Returns the position of the current active slot */ -dma_addr_t edma_get_position(unsigned slot, bool dst) +dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst) { - u32 offs, ctlr = EDMA_CTLR(slot); + u32 offs; slot = EDMA_CHAN_SLOT(slot); - offs = PARM_OFFSET(slot); offs += dst ? PARM_DST : PARM_SRC; - return edma_read(edma_cc[ctlr], offs); + return edma_read(cc, offs); } /** @@ -770,21 +762,15 @@ dma_addr_t edma_get_position(unsigned slot, bool dst) * * The originating slot should not be part of any active DMA transfer. */ -void edma_link(unsigned from, unsigned to) +void edma_link(struct edma *cc, unsigned from, unsigned to) { - unsigned ctlr_from, ctlr_to; - - ctlr_from = EDMA_CTLR(from); from = EDMA_CHAN_SLOT(from); - ctlr_to = EDMA_CTLR(to); to = EDMA_CHAN_SLOT(to); + if (from >= cc->num_slots || to >= cc->num_slots) + return; - if (from >= edma_cc[ctlr_from]->num_slots) - return; - if (to >= edma_cc[ctlr_to]->num_slots) - return; - edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } EXPORT_SYMBOL(edma_link); @@ -802,16 +788,13 @@ EXPORT_SYMBOL(edma_link); * calls to set up those parameters in small pieces, and provides * complete control over all transfer options. */ -void edma_write_slot(unsigned slot, const struct edmacc_param *param) +void edma_write_slot(struct edma *cc, unsigned slot, + const struct edmacc_param *param) { - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - - if (slot >= edma_cc[ctlr]->num_slots) + if (slot >= cc->num_slots) return; - memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE); + memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE); } EXPORT_SYMBOL(edma_write_slot); @@ -823,17 +806,12 @@ EXPORT_SYMBOL(edma_write_slot); * Use this to read data from a parameter RAM slot, perhaps to * save them as a template for later reuse. */ -void edma_read_slot(unsigned slot, struct edmacc_param *param) +void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param) { - unsigned ctlr; - - ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - - if (slot >= edma_cc[ctlr]->num_slots) + if (slot >= cc->num_slots) return; - memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot), - PARM_SIZE); + memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE); } EXPORT_SYMBOL(edma_read_slot); @@ -848,18 +826,19 @@ EXPORT_SYMBOL(edma_read_slot); * This temporarily disables EDMA hardware events on the specified channel, * preventing them from triggering new transfers on its behalf */ -void edma_pause(unsigned channel) +void edma_pause(struct edma *cc, unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { + if (channel < cc->num_channels) { unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5, - mask); + edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_pause); @@ -870,36 +849,39 @@ EXPORT_SYMBOL(edma_pause); * * This re-enables EDMA hardware events on the specified channel. */ -void edma_resume(unsigned channel) +void edma_resume(struct edma *cc, unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { + if (channel < cc->num_channels) { unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5, - mask); + edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask); } } EXPORT_SYMBOL(edma_resume); -int edma_trigger_channel(unsigned channel) +int edma_trigger_channel(struct edma *cc, unsigned channel) { - unsigned ctlr; unsigned int mask; - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return -EINVAL; + } channel = EDMA_CHAN_SLOT(channel); mask = BIT(channel & 0x1f); - edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask); + edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask); pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(edma_cc[ctlr], SH_ESR, - (channel >> 5))); + edma_shadow0_read_array(cc, SH_ESR, (channel >> 5))); return 0; } EXPORT_SYMBOL(edma_trigger_channel); @@ -915,15 +897,16 @@ EXPORT_SYMBOL(edma_trigger_channel); * * Returns zero on success, else negative errno. */ -int edma_start(unsigned channel) +int edma_start(struct edma *cc, unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return -EINVAL; + } channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - struct edma *cc = edma_cc[ctlr]; + if (channel < cc->num_channels) { int j = channel >> 5; unsigned int mask = BIT(channel & 0x1f); @@ -962,15 +945,16 @@ EXPORT_SYMBOL(edma_start); * may not be resumed, and the channel's Parameter RAM should be * reinitialized before being reused. */ -void edma_stop(unsigned channel) +void edma_stop(struct edma *cc, unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - struct edma *cc = edma_cc[ctlr]; + if (channel < cc->num_channels) { int j = channel >> 5; unsigned int mask = BIT(channel & 0x1f); @@ -1005,15 +989,16 @@ EXPORT_SYMBOL(edma_stop); * *****************************************************************************/ -void edma_clean_channel(unsigned channel) +void edma_clean_channel(struct edma *cc, unsigned channel) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - struct edma *cc = edma_cc[ctlr]; + if (channel < cc->num_channels) { int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); @@ -1037,26 +1022,35 @@ EXPORT_SYMBOL(edma_clean_channel); * * Can be used to move a channel to a selected event queue. */ -void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no) +void edma_assign_channel_eventq(struct edma *cc, unsigned channel, + enum dma_event_q eventq_no) { - unsigned ctlr; - - ctlr = EDMA_CTLR(channel); + if (cc->id != EDMA_CTLR(channel)) { + dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + cc->id, EDMA_CTLR(channel)); + return; + } channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) + if (channel >= cc->num_channels) return; /* default to low priority queue */ if (eventq_no == EVENTQ_DEFAULT) - eventq_no = edma_cc[ctlr]->default_queue; - if (eventq_no >= edma_cc[ctlr]->num_tc) + eventq_no = cc->default_queue; + if (eventq_no >= cc->num_tc) return; - map_dmach_queue(edma_cc[ctlr], channel, eventq_no); + map_dmach_queue(cc, channel, eventq_no); } EXPORT_SYMBOL(edma_assign_channel_eventq); +struct edma *edma_get_data(struct device *edma_dev) +{ + return dev_get_drvdata(edma_dev); +} + + static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, struct edma *edma_cc, int cc_id) { @@ -1278,11 +1272,10 @@ static int edma_probe(struct platform_device *pdev) } } - edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL); - if (!edma_cc[dev_id]) + cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL); + if (!cc) return -ENOMEM; - cc = edma_cc[dev_id]; cc->dev = dev; cc->id = dev_id; dev_set_drvdata(dev, cc); diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index fcb4680efed7..53d48b2a700d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -119,6 +119,7 @@ struct edma_chan { }; struct edma_cc { + struct edma *cc; int ctlr; struct dma_device dma_slave; struct edma_chan slave_chans[EDMA_CHANS]; @@ -150,6 +151,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc) /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { + struct edma *cc = echan->ecc->cc; struct virt_dma_desc *vdesc; struct edma_desc *edesc; struct device *dev = echan->vchan.chan.device->dev; @@ -174,7 +176,7 @@ static void edma_execute(struct edma_chan *echan) /* Write descriptor PaRAM set(s) */ for (i = 0; i < nslots; i++) { j = i + edesc->processed; - edma_write_slot(echan->slot[i], &edesc->pset[j].param); + edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; dev_vdbg(echan->vchan.chan.device->dev, "\n pset[%d]:\n" @@ -199,7 +201,7 @@ static void edma_execute(struct edma_chan *echan) edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) - edma_link(echan->slot[i], echan->slot[i+1]); + edma_link(cc, echan->slot[i], echan->slot[i+1]); } edesc->processed += nslots; @@ -211,9 +213,9 @@ static void edma_execute(struct edma_chan *echan) */ if (edesc->processed == edesc->pset_nr) { if (edesc->cyclic) - edma_link(echan->slot[nslots-1], echan->slot[1]); + edma_link(cc, echan->slot[nslots-1], echan->slot[1]); else - edma_link(echan->slot[nslots-1], + edma_link(cc, echan->slot[nslots-1], echan->ecc->dummy_slot); } @@ -224,19 +226,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(echan->ch_num); - edma_stop(echan->ch_num); - edma_start(echan->ch_num); - edma_trigger_channel(echan->ch_num); + edma_clean_channel(cc, echan->ch_num); + edma_stop(cc, echan->ch_num); + edma_start(cc, echan->ch_num); + edma_trigger_channel(cc, echan->ch_num); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(echan->ch_num); + edma_start(cc, echan->ch_num); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(echan->ch_num); + edma_resume(cc, echan->ch_num); } } @@ -254,10 +256,11 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ch_num); + edma_stop(echan->ecc->cc, echan->ch_num); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ch_num, + edma_assign_channel_eventq(echan->ecc->cc, + echan->ch_num, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -295,7 +298,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ch_num); + edma_pause(echan->ecc->cc, echan->ch_num); return 0; } @@ -303,7 +306,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ch_num); + edma_resume(echan->ecc->cc, echan->ch_num); return 0; } @@ -485,8 +488,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( for (i = 0; i < nslots; i++) { if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(EDMA_CTLR(echan->ch_num), - EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -641,8 +643,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( /* Allocate a PaRAM slot, if needed */ if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(EDMA_CTLR(echan->ch_num), - EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -703,7 +704,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -711,6 +712,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( static void edma_callback(unsigned ch_num, u16 ch_status, void *data) { struct edma_chan *echan = data; + struct edma *cc = echan->ecc->cc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc; struct edmacc_param p; @@ -727,13 +729,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } else if (edesc->processed == edesc->pset_nr) { dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); edesc->residue = 0; - edma_stop(echan->ch_num); + edma_stop(cc, echan->ch_num); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; } else { dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); - edma_pause(echan->ch_num); + edma_pause(cc, echan->ch_num); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -744,7 +746,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } break; case EDMA_DMA_CC_ERROR: - edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); + edma_read_slot(cc, echan->slot[0], &p); /* * Issue later based on missed flag which will be sure @@ -767,10 +769,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) * missed, so its safe to issue it here. */ dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); - edma_clean_channel(echan->ch_num); - edma_stop(echan->ch_num); - edma_start(echan->ch_num); - edma_trigger_channel(echan->ch_num); + edma_clean_channel(cc, echan->ch_num); + edma_stop(cc, echan->ch_num); + edma_start(cc, echan->ch_num); + edma_trigger_channel(cc, echan->ch_num); } break; default: @@ -789,8 +791,8 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, - echan, EVENTQ_DEFAULT); + a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num, + edma_callback, echan, EVENTQ_DEFAULT); if (a_ch_num < 0) { ret = -ENODEV; @@ -814,7 +816,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) return 0; err_wrong_chan: - edma_free_channel(a_ch_num); + edma_free_channel(echan->ecc->cc, a_ch_num); err_no_chan: return ret; } @@ -827,21 +829,21 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ch_num); + edma_stop(echan->ecc->cc, echan->ch_num); vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ for (i = 1; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { - edma_free_slot(echan->slot[i]); + edma_free_slot(echan->ecc->cc, echan->slot[i]); echan->slot[i] = -1; } } /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ch_num); + edma_free_channel(echan->ecc->cc, echan->ch_num); echan->alloced = false; } @@ -871,7 +873,8 @@ static u32 edma_residue(struct edma_desc *edesc) * We always read the dst/src position from the first RamPar * pset. That's the one which is active now. */ - pos = edma_get_position(edesc->echan->slot[0], dst); + pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0], + dst); /* * Cyclic is simple. Just subtract pset[0].addr from pos. @@ -1008,8 +1011,12 @@ static int edma_probe(struct platform_device *pdev) return -ENOMEM; } + ecc->cc = edma_get_data(pdev->dev.parent); + if (!ecc->cc) + return -ENODEV; + ecc->ctlr = pdev->id; - ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); + ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; @@ -1042,7 +1049,7 @@ static int edma_probe(struct platform_device *pdev) return 0; err_reg1: - edma_free_slot(ecc->dummy_slot); + edma_free_slot(ecc->cc, ecc->dummy_slot); return ret; } @@ -1055,7 +1062,7 @@ static int edma_remove(struct platform_device *pdev) if (parent_node) of_dma_controller_free(parent_node); dma_async_device_unregister(&ecc->dma_slave); - edma_free_slot(ecc->dummy_slot); + edma_free_slot(ecc->cc, ecc->dummy_slot); return 0; } diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index c1862423b356..466021c03169 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h @@ -92,32 +92,40 @@ enum dma_event_q { #define EDMA_MAX_CC 2 +struct edma; + +struct edma *edma_get_data(struct device *edma_dev); + /* alloc/free DMA channels and their dedicated parameter RAM slots */ -int edma_alloc_channel(int channel, +int edma_alloc_channel(struct edma *cc, int channel, void (*callback)(unsigned channel, u16 ch_status, void *data), void *data, enum dma_event_q); -void edma_free_channel(unsigned channel); +void edma_free_channel(struct edma *cc, unsigned channel); /* alloc/free parameter RAM slots */ -int edma_alloc_slot(unsigned ctlr, int slot); -void edma_free_slot(unsigned slot); +int edma_alloc_slot(struct edma *cc, int slot); +void edma_free_slot(struct edma *cc, unsigned slot); /* calls that operate on part of a parameter RAM slot */ -dma_addr_t edma_get_position(unsigned slot, bool dst); -void edma_link(unsigned from, unsigned to); +dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst); +void edma_link(struct edma *cc, unsigned from, unsigned to); /* calls that operate on an entire parameter RAM slot */ -void edma_write_slot(unsigned slot, const struct edmacc_param *params); -void edma_read_slot(unsigned slot, struct edmacc_param *params); +void edma_write_slot(struct edma *cc, unsigned slot, + const struct edmacc_param *params); +void edma_read_slot(struct edma *cc, unsigned slot, + struct edmacc_param *params); /* channel control operations */ -int edma_start(unsigned channel); -void edma_stop(unsigned channel); -void edma_clean_channel(unsigned channel); -void edma_pause(unsigned channel); -void edma_resume(unsigned channel); +int edma_start(struct edma *cc, unsigned channel); +void edma_stop(struct edma *cc, unsigned channel); +void edma_clean_channel(struct edma *cc, unsigned channel); +void edma_pause(struct edma *cc, unsigned channel); +void edma_resume(struct edma *cc, unsigned channel); +int edma_trigger_channel(struct edma *cc, unsigned channel); -void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no); +void edma_assign_channel_eventq(struct edma *cc, unsigned channel, + enum dma_event_q eventq_no); struct edma_rsv_info { @@ -141,6 +149,4 @@ struct edma_soc_info { const s16 (*xbar_chans)[2]; }; -int edma_trigger_channel(unsigned); - #endif From b2c843a196b8f5aca74ebabd16c60d59480d6721 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:50 +0300 Subject: [PATCH 36/77] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Since the driver stack no longer depends on lookup with id number in a global array of pointers, the limitation for the number of eDMAs are no longer needed. We can handle as many eDMAs in legacy and DT boot as we have memory for them to allocate the needed structures. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 22 +++++----------------- drivers/dma/edma.c | 17 ++++++++--------- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 03692520812a..5b747f1bc8b5 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -1227,24 +1227,7 @@ static int edma_probe(struct platform_device *pdev) .parent = &pdev->dev, }; - /* When booting with DT the pdev->id is -1 */ - if (dev_id < 0) - dev_id = arch_num_cc; - - if (dev_id >= EDMA_MAX_CC) { - dev_err(dev, - "eDMA3 with device id 0 and 1 is supported (id: %d)\n", - dev_id); - return -EINVAL; - } - if (node) { - /* Check if this is a second instance registered */ - if (arch_num_cc) { - dev_err(dev, "only one EDMA instance is supported via DT\n"); - return -ENODEV; - } - info = edma_setup_info_from_dt(dev, node); if (IS_ERR(info)) { dev_err(dev, "failed to get DT data\n"); @@ -1278,6 +1261,11 @@ static int edma_probe(struct platform_device *pdev) cc->dev = dev; cc->id = dev_id; + /* When booting with DT the pdev->id is -1 */ + if (dev_id < 0) { + cc->id = 0; + dev_id = arch_num_cc; + } dev_set_drvdata(dev, cc); cc->base = devm_ioremap_resource(dev, mem); diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 53d48b2a700d..fc91ab9dd1bb 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -991,14 +991,12 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } -static struct of_dma_filter_info edma_filter_info = { - .filter_fn = edma_filter_fn, -}; - static int edma_probe(struct platform_device *pdev) { struct edma_cc *ecc; struct device_node *parent_node = pdev->dev.parent->of_node; + struct platform_device *parent_pdev = + to_platform_device(pdev->dev.parent); int ret; ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); @@ -1015,7 +1013,10 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->cc) return -ENODEV; - ecc->ctlr = pdev->id; + ecc->ctlr = parent_pdev->id; + if (ecc->ctlr < 0) + ecc->ctlr = 0; + ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); @@ -1038,10 +1039,8 @@ static int edma_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ecc); if (parent_node) { - dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); - dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); - of_dma_controller_register(parent_node, of_dma_simple_xlate, - &edma_filter_info); + of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id, + &ecc->dma_slave); } dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); From 7ab388e85faa97a35d520720269e7c8e00ad54a0 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:51 +0300 Subject: [PATCH 37/77] ARM: davinci: Use platform_device_register_full() to create pdev for eDMA Convert the eDMA platform device creation to use struct platform_device_info XXXXXX __initconst and platform_device_register_full() This will allow us to cleanly specify the dma_mask for the devices in an upcoming patch. Signed-off-by: Peter Ujfalusi Acked-by: Sekhar Nori Signed-off-by: Vinod Koul --- arch/arm/mach-davinci/devices-da8xx.c | 38 ++++++++++++++------------- arch/arm/mach-davinci/dm355.c | 20 +++++++++----- arch/arm/mach-davinci/dm644x.c | 20 +++++++++----- arch/arm/mach-davinci/dm646x.c | 18 ++++++++----- 4 files changed, 57 insertions(+), 39 deletions(-) diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 9ae049ae816a..9f7d266faa0c 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -213,48 +213,50 @@ static struct resource da850_edma1_resources[] = { }, }; -static struct platform_device da8xx_edma0_device = { +static const struct platform_device_info da8xx_edma0_device __initconst = { .name = "edma", .id = 0, - .dev = { - .platform_data = &da8xx_edma0_pdata, - }, - .num_resources = ARRAY_SIZE(da8xx_edma0_resources), - .resource = da8xx_edma0_resources, + .res = da8xx_edma0_resources, + .num_res = ARRAY_SIZE(da8xx_edma0_resources), + .data = &da8xx_edma0_pdata, + .size_data = sizeof(da8xx_edma0_pdata), }; -static struct platform_device da850_edma1_device = { +static const struct platform_device_info da850_edma1_device __initconst = { .name = "edma", .id = 1, - .dev = { - .platform_data = &da850_edma1_pdata, - }, - .num_resources = ARRAY_SIZE(da850_edma1_resources), - .resource = da850_edma1_resources, + .res = da850_edma1_resources, + .num_res = ARRAY_SIZE(da850_edma1_resources), + .data = &da850_edma1_pdata, + .size_data = sizeof(da850_edma1_pdata), }; int __init da830_register_edma(struct edma_rsv_info *rsv) { + struct platform_device *edma_pdev; + da8xx_edma0_pdata.rsv = rsv; - return platform_device_register(&da8xx_edma0_device); + edma_pdev = platform_device_register_full(&da8xx_edma0_device); + return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0; } int __init da850_register_edma(struct edma_rsv_info *rsv[2]) { - int ret; + struct platform_device *edma_pdev; if (rsv) { da8xx_edma0_pdata.rsv = rsv[0]; da850_edma1_pdata.rsv = rsv[1]; } - ret = platform_device_register(&da8xx_edma0_device); - if (ret) { + edma_pdev = platform_device_register_full(&da8xx_edma0_device); + if (IS_ERR(edma_pdev)) { pr_warn("%s: Failed to register eDMA0\n", __func__); - return ret; + return PTR_ERR(edma_pdev); } - return platform_device_register(&da850_edma1_device); + edma_pdev = platform_device_register_full(&da850_edma1_device); + return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0; } static struct resource da8xx_i2c_resources0[] = { diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index a50bb9c66952..5f10c6695e31 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -613,12 +613,13 @@ static struct resource edma_resources[] = { /* not using (or muxing) TC*_ERR */ }; -static struct platform_device dm355_edma_device = { - .name = "edma", - .id = 0, - .dev.platform_data = &dm355_edma_pdata, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, +static const struct platform_device_info dm355_edma_device __initconst = { + .name = "edma", + .id = 0, + .res = edma_resources, + .num_res = ARRAY_SIZE(edma_resources), + .data = &dm355_edma_pdata, + .size_data = sizeof(dm355_edma_pdata), }; static struct resource dm355_asp1_resources[] = { @@ -1057,13 +1058,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg, static int __init dm355_init_devices(void) { + struct platform_device *edma_pdev; int ret = 0; if (!cpu_is_davinci_dm355()) return 0; davinci_cfg_reg(DM355_INT_EDMA_CC); - platform_device_register(&dm355_edma_device); + edma_pdev = platform_device_register_full(&dm355_edma_device); + if (IS_ERR(edma_pdev)) { + pr_warn("%s: Failed to register eDMA\n", __func__); + return PTR_ERR(edma_pdev); + } ret = davinci_init_wdt(); if (ret) diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index d759ca8e58e8..aa3453b40d5f 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -542,12 +542,13 @@ static struct resource edma_resources[] = { /* not using TC*_ERR */ }; -static struct platform_device dm644x_edma_device = { - .name = "edma", - .id = 0, - .dev.platform_data = &dm644x_edma_pdata, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, +static const struct platform_device_info dm644x_edma_device __initconst = { + .name = "edma", + .id = 0, + .res = edma_resources, + .num_res = ARRAY_SIZE(edma_resources), + .data = &dm644x_edma_pdata, + .size_data = sizeof(dm644x_edma_pdata), }; /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */ @@ -945,12 +946,17 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg, static int __init dm644x_init_devices(void) { + struct platform_device *edma_pdev; int ret = 0; if (!cpu_is_davinci_dm644x()) return 0; - platform_device_register(&dm644x_edma_device); + edma_pdev = platform_device_register_full(&dm644x_edma_device); + if (IS_ERR(edma_pdev)) { + pr_warn("%s: Failed to register eDMA\n", __func__); + return PTR_ERR(edma_pdev); + } platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 219ebc8f674a..79c1d8917dd3 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -589,12 +589,13 @@ static struct resource edma_resources[] = { /* not using TC*_ERR */ }; -static struct platform_device dm646x_edma_device = { - .name = "edma", - .id = 0, - .dev.platform_data = &dm646x_edma_pdata, - .num_resources = ARRAY_SIZE(edma_resources), - .resource = edma_resources, +static const struct platform_device_info dm646x_edma_device __initconst = { + .name = "edma", + .id = 0, + .res = edma_resources, + .num_res = ARRAY_SIZE(edma_resources), + .data = &dm646x_edma_pdata, + .size_data = sizeof(dm646x_edma_pdata), }; static struct resource dm646x_mcasp0_resources[] = { @@ -931,9 +932,12 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config, int __init dm646x_init_edma(struct edma_rsv_info *rsv) { + struct platform_device *edma_pdev; + dm646x_edma_pdata.rsv = rsv; - return platform_device_register(&dm646x_edma_device); + edma_pdev = platform_device_register_full(&dm646x_edma_device); + return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0; } void __init dm646x_init(void) From cef5b0da4019358cb03c9b0a964d4d63cd7deaf6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:52 +0300 Subject: [PATCH 38/77] ARM: davinci: Add dma_mask to eDMA devices The upcoming change to merge the arch/arm/common/edma.c into drivers/dma/edma.c will need this change when booting daVinci devices in no DT mode. Signed-off-by: Peter Ujfalusi Acked-by: Sekhar Nori Signed-off-by: Vinod Koul --- arch/arm/mach-davinci/devices-da8xx.c | 2 ++ arch/arm/mach-davinci/dm355.c | 1 + arch/arm/mach-davinci/dm644x.c | 1 + arch/arm/mach-davinci/dm646x.c | 1 + 4 files changed, 5 insertions(+) diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 9f7d266faa0c..28c90bc372bd 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -216,6 +216,7 @@ static struct resource da850_edma1_resources[] = { static const struct platform_device_info da8xx_edma0_device __initconst = { .name = "edma", .id = 0, + .dma_mask = DMA_BIT_MASK(32), .res = da8xx_edma0_resources, .num_res = ARRAY_SIZE(da8xx_edma0_resources), .data = &da8xx_edma0_pdata, @@ -225,6 +226,7 @@ static const struct platform_device_info da8xx_edma0_device __initconst = { static const struct platform_device_info da850_edma1_device __initconst = { .name = "edma", .id = 1, + .dma_mask = DMA_BIT_MASK(32), .res = da850_edma1_resources, .num_res = ARRAY_SIZE(da850_edma1_resources), .data = &da850_edma1_pdata, diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 5f10c6695e31..609950b8c191 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c @@ -616,6 +616,7 @@ static struct resource edma_resources[] = { static const struct platform_device_info dm355_edma_device __initconst = { .name = "edma", .id = 0, + .dma_mask = DMA_BIT_MASK(32), .res = edma_resources, .num_res = ARRAY_SIZE(edma_resources), .data = &dm355_edma_pdata, diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index aa3453b40d5f..d38f5049d56e 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -545,6 +545,7 @@ static struct resource edma_resources[] = { static const struct platform_device_info dm644x_edma_device __initconst = { .name = "edma", .id = 0, + .dma_mask = DMA_BIT_MASK(32), .res = edma_resources, .num_res = ARRAY_SIZE(edma_resources), .data = &dm644x_edma_pdata, diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 79c1d8917dd3..70eb42725eec 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -592,6 +592,7 @@ static struct resource edma_resources[] = { static const struct platform_device_info dm646x_edma_device __initconst = { .name = "edma", .id = 0, + .dma_mask = DMA_BIT_MASK(32), .res = edma_resources, .num_res = ARRAY_SIZE(edma_resources), .data = &dm646x_edma_pdata, From 2b6b3b7420190888793c49e97276e1e73bd7eaed Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:53 +0300 Subject: [PATCH 39/77] ARM/dmaengine: edma: Merge the two drivers under drivers/dma/ Move the code out from arch/arm/common and merge it inside of the dmaengine driver. This change is done with as minimal (if eny) functional change to the code as possible to avoid introducing regression. Signed-off-by: Peter Ujfalusi Acked-by: Tony Lindgren Signed-off-by: Vinod Koul --- arch/arm/Kconfig | 1 - arch/arm/common/Kconfig | 3 - arch/arm/common/Makefile | 1 - arch/arm/common/edma.c | 1431 -------------------------- arch/arm/mach-omap2/Kconfig | 1 - drivers/dma/Kconfig | 1 - drivers/dma/edma.c | 1506 ++++++++++++++++++++++++++-- include/linux/platform_data/edma.h | 74 -- 8 files changed, 1431 insertions(+), 1587 deletions(-) delete mode 100644 arch/arm/common/edma.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 72ad724c67ae..513e38701418 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -736,7 +736,6 @@ config ARCH_DAVINCI select GENERIC_CLOCKEVENTS select GENERIC_IRQ_CHIP select HAVE_IDE - select TI_PRIV_EDMA select USE_OF select ZONE_DMA help diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index c3a4e9ceba34..9353184d730d 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -17,6 +17,3 @@ config SHARP_PARAM config SHARP_SCOOP bool - -config TI_PRIV_EDMA - bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 6ee5959a813b..27f23b15b1ea 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -15,6 +15,5 @@ obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o CFLAGS_REMOVE_mcpm_entry.o = -pg AFLAGS_mcpm_head.o := -march=armv7-a AFLAGS_vlock.o := -march=armv7-a -obj-$(CONFIG_TI_PRIV_EDMA) += edma.o obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c deleted file mode 100644 index 5b747f1bc8b5..000000000000 --- a/arch/arm/common/edma.c +++ /dev/null @@ -1,1431 +0,0 @@ -/* - * EDMA3 support for DaVinci - * - * Copyright (C) 2006-2009 Texas Instruments. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Offsets matching "struct edmacc_param" */ -#define PARM_OPT 0x00 -#define PARM_SRC 0x04 -#define PARM_A_B_CNT 0x08 -#define PARM_DST 0x0c -#define PARM_SRC_DST_BIDX 0x10 -#define PARM_LINK_BCNTRLD 0x14 -#define PARM_SRC_DST_CIDX 0x18 -#define PARM_CCNT 0x1c - -#define PARM_SIZE 0x20 - -/* Offsets for EDMA CC global channel registers and their shadows */ -#define SH_ER 0x00 /* 64 bits */ -#define SH_ECR 0x08 /* 64 bits */ -#define SH_ESR 0x10 /* 64 bits */ -#define SH_CER 0x18 /* 64 bits */ -#define SH_EER 0x20 /* 64 bits */ -#define SH_EECR 0x28 /* 64 bits */ -#define SH_EESR 0x30 /* 64 bits */ -#define SH_SER 0x38 /* 64 bits */ -#define SH_SECR 0x40 /* 64 bits */ -#define SH_IER 0x50 /* 64 bits */ -#define SH_IECR 0x58 /* 64 bits */ -#define SH_IESR 0x60 /* 64 bits */ -#define SH_IPR 0x68 /* 64 bits */ -#define SH_ICR 0x70 /* 64 bits */ -#define SH_IEVAL 0x78 -#define SH_QER 0x80 -#define SH_QEER 0x84 -#define SH_QEECR 0x88 -#define SH_QEESR 0x8c -#define SH_QSER 0x90 -#define SH_QSECR 0x94 -#define SH_SIZE 0x200 - -/* Offsets for EDMA CC global registers */ -#define EDMA_REV 0x0000 -#define EDMA_CCCFG 0x0004 -#define EDMA_QCHMAP 0x0200 /* 8 registers */ -#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ -#define EDMA_QDMAQNUM 0x0260 -#define EDMA_QUETCMAP 0x0280 -#define EDMA_QUEPRI 0x0284 -#define EDMA_EMR 0x0300 /* 64 bits */ -#define EDMA_EMCR 0x0308 /* 64 bits */ -#define EDMA_QEMR 0x0310 -#define EDMA_QEMCR 0x0314 -#define EDMA_CCERR 0x0318 -#define EDMA_CCERRCLR 0x031c -#define EDMA_EEVAL 0x0320 -#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ -#define EDMA_QRAE 0x0380 /* 4 registers */ -#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ -#define EDMA_QSTAT 0x0600 /* 2 registers */ -#define EDMA_QWMTHRA 0x0620 -#define EDMA_QWMTHRB 0x0624 -#define EDMA_CCSTAT 0x0640 - -#define EDMA_M 0x1000 /* global channel registers */ -#define EDMA_ECR 0x1008 -#define EDMA_ECRH 0x100C -#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ -#define EDMA_PARM 0x4000 /* 128 param entries */ - -#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) - -#define EDMA_DCHMAP 0x0100 /* 64 registers */ - -/* CCCFG register */ -#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ -#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ -#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ -#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ -#define CHMAP_EXIST BIT(24) - -#define EDMA_MAX_DMACH 64 -#define EDMA_MAX_PARAMENTRY 512 - -/*****************************************************************************/ -struct edma { - struct device *dev; - void __iomem *base; - - /* how many dma resources of each type */ - unsigned num_channels; - unsigned num_region; - unsigned num_slots; - unsigned num_tc; - enum dma_event_q default_queue; - - /* list of channels with no even trigger; terminated by "-1" */ - const s8 *noevent; - - struct edma_soc_info *info; - int id; - bool unused_chan_list_done; - /* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); - - /* The edma_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); - - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } intr_data[EDMA_MAX_DMACH]; -}; -/*****************************************************************************/ - -static inline unsigned int edma_read(struct edma *cc, int offset) -{ - return (unsigned int)__raw_readl(cc->base + offset); -} - -static inline void edma_write(struct edma *cc, int offset, int val) -{ - __raw_writel(val, cc->base + offset); -} -static inline void edma_modify(struct edma *cc, int offset, unsigned and, - unsigned or) -{ - unsigned val = edma_read(cc, offset); - val &= and; - val |= or; - edma_write(cc, offset, val); -} -static inline void edma_and(struct edma *cc, int offset, unsigned and) -{ - unsigned val = edma_read(cc, offset); - val &= and; - edma_write(cc, offset, val); -} -static inline void edma_or(struct edma *cc, int offset, unsigned or) -{ - unsigned val = edma_read(cc, offset); - val |= or; - edma_write(cc, offset, val); -} -static inline unsigned int edma_read_array(struct edma *cc, int offset, int i) -{ - return edma_read(cc, offset + (i << 2)); -} -static inline void edma_write_array(struct edma *cc, int offset, int i, - unsigned val) -{ - edma_write(cc, offset + (i << 2), val); -} -static inline void edma_modify_array(struct edma *cc, int offset, int i, - unsigned and, unsigned or) -{ - edma_modify(cc, offset + (i << 2), and, or); -} -static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or) -{ - edma_or(cc, offset + (i << 2), or); -} -static inline void edma_or_array2(struct edma *cc, int offset, int i, int j, - unsigned or) -{ - edma_or(cc, offset + ((i*2 + j) << 2), or); -} -static inline void edma_write_array2(struct edma *cc, int offset, int i, int j, - unsigned val) -{ - edma_write(cc, offset + ((i*2 + j) << 2), val); -} -static inline unsigned int edma_shadow0_read(struct edma *cc, int offset) -{ - return edma_read(cc, EDMA_SHADOW0 + offset); -} -static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset, - int i) -{ - return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2)); -} -static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val) -{ - edma_write(cc, EDMA_SHADOW0 + offset, val); -} -static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i, - unsigned val) -{ - edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val); -} -static inline unsigned int edma_parm_read(struct edma *cc, int offset, - int param_no) -{ - return edma_read(cc, EDMA_PARM + offset + (param_no << 5)); -} -static inline void edma_parm_write(struct edma *cc, int offset, int param_no, - unsigned val) -{ - edma_write(cc, EDMA_PARM + offset + (param_no << 5), val); -} -static inline void edma_parm_modify(struct edma *cc, int offset, int param_no, - unsigned and, unsigned or) -{ - edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or); -} -static inline void edma_parm_and(struct edma *cc, int offset, int param_no, - unsigned and) -{ - edma_and(cc, EDMA_PARM + offset + (param_no << 5), and); -} -static inline void edma_parm_or(struct edma *cc, int offset, int param_no, - unsigned or) -{ - edma_or(cc, EDMA_PARM + offset + (param_no << 5), or); -} - -static inline void set_bits(int offset, int len, unsigned long *p) -{ - for (; len > 0; len--) - set_bit(offset + (len - 1), p); -} - -static inline void clear_bits(int offset, int len, unsigned long *p) -{ - for (; len > 0; len--) - clear_bit(offset + (len - 1), p); -} - -/*****************************************************************************/ -static int arch_num_cc; - -/* dummy param set used to (re)initialize parameter RAM slots */ -static const struct edmacc_param dummy_paramset = { - .link_bcntrld = 0xffff, - .ccnt = 1, -}; - -static const struct of_device_id edma_of_ids[] = { - { .compatible = "ti,edma3", }, - {} -}; - -/*****************************************************************************/ - -static void map_dmach_queue(struct edma *cc, unsigned ch_no, - enum dma_event_q queue_no) -{ - int bit = (ch_no & 0x7) * 4; - - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = cc->default_queue; - - queue_no &= 7; - edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3), - ~(0x7 << bit), queue_no << bit); -} - -static void assign_priority_to_queue(struct edma *cc, int queue_no, - int priority) -{ - int bit = queue_no * 4; - edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); -} - -/** - * map_dmach_param - Maps channel number to param entry number - * - * This maps the dma channel number to param entry numberter. In - * other words using the DMA channel mapping registers a param entry - * can be mapped to any channel - * - * Callers are responsible for ensuring the channel mapping logic is - * included in that particular EDMA variant (Eg : dm646x) - * - */ -static void map_dmach_param(struct edma *cc) -{ - int i; - for (i = 0; i < EDMA_MAX_DMACH; i++) - edma_write_array(cc, EDMA_DCHMAP , i , (i << 5)); -} - -static inline void setup_dma_interrupt(struct edma *cc, unsigned lch, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data) -{ - lch = EDMA_CHAN_SLOT(lch); - - if (!callback) - edma_shadow0_write_array(cc, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); - - cc->intr_data[lch].callback = callback; - cc->intr_data[lch].data = data; - - if (callback) { - edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f)); - edma_shadow0_write_array(cc, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); - } -} - -/****************************************************************************** - * - * DMA interrupt handler - * - *****************************************************************************/ -static irqreturn_t dma_irq_handler(int irq, void *data) -{ - struct edma *cc = data; - int ctlr; - u32 sh_ier; - u32 sh_ipr; - u32 bank; - - ctlr = cc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(cc->dev, "dma_irq_handler\n"); - - sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0); - if (!sh_ipr) { - sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1); - if (!sh_ipr) - return IRQ_NONE; - sh_ier = edma_shadow0_read_array(cc, SH_IER, 1); - bank = 1; - } else { - sh_ier = edma_shadow0_read_array(cc, SH_IER, 0); - bank = 0; - } - - do { - u32 slot; - u32 channel; - - dev_dbg(cc->dev, "IPR%d %08x\n", bank, sh_ipr); - - slot = __ffs(sh_ipr); - sh_ipr &= ~(BIT(slot)); - - if (sh_ier & BIT(slot)) { - channel = (bank << 5) | slot; - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot)); - if (cc->intr_data[channel].callback) - cc->intr_data[channel].callback( - EDMA_CTLR_CHAN(ctlr, channel), - EDMA_DMA_COMPLETE, - cc->intr_data[channel].data); - } - } while (sh_ipr); - - edma_shadow0_write(cc, SH_IEVAL, 1); - return IRQ_HANDLED; -} - -/****************************************************************************** - * - * DMA error interrupt handler - * - *****************************************************************************/ -static irqreturn_t dma_ccerr_handler(int irq, void *data) -{ - struct edma *cc = data; - int i; - int ctlr; - unsigned int cnt = 0; - - ctlr = cc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(cc->dev, "dma_ccerr_handler\n"); - - if ((edma_read_array(cc, EDMA_EMR, 0) == 0) && - (edma_read_array(cc, EDMA_EMR, 1) == 0) && - (edma_read(cc, EDMA_QEMR) == 0) && - (edma_read(cc, EDMA_CCERR) == 0)) - return IRQ_NONE; - - while (1) { - int j = -1; - if (edma_read_array(cc, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(cc, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - dev_dbg(cc->dev, "EMR%d %08x\n", j, - edma_read_array(cc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if (edma_read_array(cc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(cc, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(cc, SH_SECR, - j, BIT(i)); - if (cc->intr_data[k].callback) { - cc->intr_data[k].callback( - EDMA_CTLR_CHAN(ctlr, k), - EDMA_DMA_CC_ERROR, - cc->intr_data[k].data); - } - } - } - } else if (edma_read(cc, EDMA_QEMR)) { - dev_dbg(cc->dev, "QEMR %02x\n", - edma_read(cc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(cc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(cc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(cc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(cc, EDMA_CCERR)) { - dev_dbg(cc->dev, "CCERR %08x\n", - edma_read(cc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(cc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(cc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(cc, EDMA_EMR, 0) == 0) && - (edma_read_array(cc, EDMA_EMR, 1) == 0) && - (edma_read(cc, EDMA_QEMR) == 0) && - (edma_read(cc, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(cc, EDMA_EEVAL, 1); - return IRQ_HANDLED; -} - -static int prepare_unused_channel_list(struct device *dev, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - struct edma *cc = data; - int i, count; - struct of_phandle_args dma_spec; - - if (dev->of_node) { - struct platform_device *dma_pdev; - - count = of_property_count_strings(dev->of_node, "dma-names"); - if (count < 0) - return 0; - for (i = 0; i < count; i++) { - - if (of_parse_phandle_with_args(dev->of_node, "dmas", - "#dma-cells", i, - &dma_spec)) - continue; - - if (!of_match_node(edma_of_ids, dma_spec.np)) { - of_node_put(dma_spec.np); - continue; - } - - dma_pdev = of_find_device_by_node(dma_spec.np); - if (&dma_pdev->dev != cc->dev) - continue; - - clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - cc->edma_unused); - of_node_put(dma_spec.np); - } - return 0; - } - - /* For non-OF case */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *res = &pdev->resource[i]; - - if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - cc->edma_unused); - } - } - - return 0; -} - -/*-----------------------------------------------------------------------*/ - -/* Resource alloc/free: dma channels, parameter RAM slots */ - -/** - * edma_alloc_channel - allocate DMA channel and paired parameter RAM - * @channel: specific channel to allocate; negative for "any unmapped channel" - * @callback: optional; to be issued on DMA completion or errors - * @data: passed to callback - * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. - * - * This allocates a DMA channel and its associated parameter RAM slot. - * The parameter RAM is initialized to hold a dummy transfer. - * - * Normal use is to pass a specific channel number as @channel, to make - * use of hardware events mapped to that channel. When the channel will - * be used only for software triggering or event chaining, channels not - * mapped to hardware events (or mapped to unused events) are preferable. - * - * DMA transfers start from a channel using edma_start(), or by - * chaining. When the transfer described in that channel's parameter RAM - * slot completes, that slot's data may be reloaded through a link. - * - * DMA errors are only reported to the @callback associated with the - * channel driving that transfer, but transfer completion callbacks can - * be sent to another channel under control of the TCC field in - * the option word of the transfer's parameter RAM set. Drivers must not - * use DMA transfer completion callbacks for channels they did not allocate. - * (The same applies to TCC codes used in transfer chaining.) - * - * Returns the number of the channel, else negative errno. - */ -int edma_alloc_channel(struct edma *cc, int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, - enum dma_event_q eventq_no) -{ - unsigned done = 0; - int ret = 0; - - if (!cc->unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - ret = bus_for_each_dev(&platform_bus_type, NULL, cc, - prepare_unused_channel_list); - if (ret < 0) - return ret; - - cc->unused_chan_list_done = true; - } - - if (channel >= 0) { - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", - __func__, cc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - } - - if (channel < 0) { - channel = 0; - for (;;) { - channel = find_next_bit(cc->edma_unused, - cc->num_channels, channel); - if (channel == cc->num_channels) - break; - if (!test_and_set_bit(channel, cc->edma_inuse)) { - done = 1; - break; - } - channel++; - } - if (!done) - return -ENOMEM; - } else if (channel >= cc->num_channels) { - return -EINVAL; - } else if (test_and_set_bit(channel, cc->edma_inuse)) { - return -EBUSY; - } - - /* ensure access through shadow region 0 */ - edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); - - /* ensure no events are pending */ - edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel)); - memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset, - PARM_SIZE); - - if (callback) - setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel), - callback, data); - - map_dmach_queue(cc, channel, eventq_no); - - return EDMA_CTLR_CHAN(cc->id, channel); -} -EXPORT_SYMBOL(edma_alloc_channel); - - -/** - * edma_free_channel - deallocate DMA channel - * @channel: dma channel returned from edma_alloc_channel() - * - * This deallocates the DMA channel and associated parameter RAM slot - * allocated by edma_alloc_channel(). - * - * Callers are responsible for ensuring the channel is inactive, and - * will not be reactivated by linking, chaining, or software calls to - * edma_start(). - */ -void edma_free_channel(struct edma *cc, unsigned channel) -{ - - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= cc->num_channels) - return; - - setup_dma_interrupt(cc, channel, NULL, NULL); - /* REVISIT should probably take out of shadow region 0 */ - - memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset, - PARM_SIZE); - clear_bit(channel, cc->edma_inuse); -} -EXPORT_SYMBOL(edma_free_channel); - -/** - * edma_alloc_slot - allocate DMA parameter RAM - * @slot: specific slot to allocate; negative for "any unused slot" - * - * This allocates a parameter RAM slot, initializing it to hold a - * dummy transfer. Slots allocated using this routine have not been - * mapped to a hardware DMA channel, and will normally be used by - * linking to them from a slot associated with a DMA channel. - * - * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific - * slots may be allocated on behalf of DSP firmware. - * - * Returns the number of the slot, else negative errno. - */ -int edma_alloc_slot(struct edma *cc, int slot) -{ - if (slot > 0) - slot = EDMA_CHAN_SLOT(slot); - if (slot < 0) { - slot = cc->num_channels; - for (;;) { - slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots, - slot); - if (slot == cc->num_slots) - return -ENOMEM; - if (!test_and_set_bit(slot, cc->edma_inuse)) - break; - } - } else if (slot < cc->num_channels || slot >= cc->num_slots) { - return -EINVAL; - } else if (test_and_set_bit(slot, cc->edma_inuse)) { - return -EBUSY; - } - - memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - - return slot; -} -EXPORT_SYMBOL(edma_alloc_slot); - -/** - * edma_free_slot - deallocate DMA parameter RAM - * @slot: parameter RAM slot returned from edma_alloc_slot() - * - * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). - * Callers are responsible for ensuring the slot is inactive, and will - * not be activated. - */ -void edma_free_slot(struct edma *cc, unsigned slot) -{ - - slot = EDMA_CHAN_SLOT(slot); - if (slot < cc->num_channels || slot >= cc->num_slots) - return; - - memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE); - clear_bit(slot, cc->edma_inuse); -} -EXPORT_SYMBOL(edma_free_slot); - -/*-----------------------------------------------------------------------*/ - -/* Parameter RAM operations (i) -- read/write partial slots */ - -/** - * edma_get_position - returns the current transfer point - * @slot: parameter RAM slot being examined - * @dst: true selects the dest position, false the source - * - * Returns the position of the current active slot - */ -dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst) -{ - u32 offs; - - slot = EDMA_CHAN_SLOT(slot); - offs = PARM_OFFSET(slot); - offs += dst ? PARM_DST : PARM_SRC; - - return edma_read(cc, offs); -} - -/** - * edma_link - link one parameter RAM slot to another - * @from: parameter RAM slot originating the link - * @to: parameter RAM slot which is the link target - * - * The originating slot should not be part of any active DMA transfer. - */ -void edma_link(struct edma *cc, unsigned from, unsigned to) -{ - from = EDMA_CHAN_SLOT(from); - to = EDMA_CHAN_SLOT(to); - if (from >= cc->num_slots || to >= cc->num_slots) - return; - - edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); -} -EXPORT_SYMBOL(edma_link); - -/*-----------------------------------------------------------------------*/ - -/* Parameter RAM operations (ii) -- read/write whole parameter sets */ - -/** - * edma_write_slot - write parameter RAM data for slot - * @slot: number of parameter RAM slot being modified - * @param: data to be written into parameter RAM slot - * - * Use this to assign all parameters of a transfer at once. This - * allows more efficient setup of transfers than issuing multiple - * calls to set up those parameters in small pieces, and provides - * complete control over all transfer options. - */ -void edma_write_slot(struct edma *cc, unsigned slot, - const struct edmacc_param *param) -{ - slot = EDMA_CHAN_SLOT(slot); - if (slot >= cc->num_slots) - return; - memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE); -} -EXPORT_SYMBOL(edma_write_slot); - -/** - * edma_read_slot - read parameter RAM data from slot - * @slot: number of parameter RAM slot being copied - * @param: where to store copy of parameter RAM data - * - * Use this to read data from a parameter RAM slot, perhaps to - * save them as a template for later reuse. - */ -void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param) -{ - slot = EDMA_CHAN_SLOT(slot); - if (slot >= cc->num_slots) - return; - memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE); -} -EXPORT_SYMBOL(edma_read_slot); - -/*-----------------------------------------------------------------------*/ - -/* Various EDMA channel control operations */ - -/** - * edma_pause - pause dma on a channel - * @channel: on which edma_start() has been called - * - * This temporarily disables EDMA hardware events on the specified channel, - * preventing them from triggering new transfers on its behalf - */ -void edma_pause(struct edma *cc, unsigned channel) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < cc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask); - } -} -EXPORT_SYMBOL(edma_pause); - -/** - * edma_resume - resumes dma on a paused channel - * @channel: on which edma_pause() has been called - * - * This re-enables EDMA hardware events on the specified channel. - */ -void edma_resume(struct edma *cc, unsigned channel) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < cc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask); - } -} -EXPORT_SYMBOL(edma_resume); - -int edma_trigger_channel(struct edma *cc, unsigned channel) -{ - unsigned int mask; - - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask); - - pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(cc, SH_ESR, (channel >> 5))); - return 0; -} -EXPORT_SYMBOL(edma_trigger_channel); - -/** - * edma_start - start dma on a channel - * @channel: channel being activated - * - * Channels with event associations will be triggered by their hardware - * events, and channels without such associations will be triggered by - * software. (At this writing there is no interface for using software - * triggers except with channels that don't support hardware triggers.) - * - * Returns zero on success, else negative errno. - */ -int edma_start(struct edma *cc, unsigned channel) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < cc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); - - /* EDMA channels without event association */ - if (test_bit(channel, cc->edma_unused)) { - pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(cc, SH_ESR, j)); - edma_shadow0_write_array(cc, SH_ESR, j, mask); - return 0; - } - - /* EDMA channel with event association */ - pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(cc, SH_ER, j)); - /* Clear any pending event or error */ - edma_write_array(cc, EDMA_ECR, j, mask); - edma_write_array(cc, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(cc, SH_SECR, j, mask); - edma_shadow0_write_array(cc, SH_EESR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(cc, SH_EER, j)); - return 0; - } - - return -EINVAL; -} -EXPORT_SYMBOL(edma_start); - -/** - * edma_stop - stops dma on the channel passed - * @channel: channel being deactivated - * - * When @lch is a channel, any active transfer is paused and - * all pending hardware events are cleared. The current transfer - * may not be resumed, and the channel's Parameter RAM should be - * reinitialized before being reused. - */ -void edma_stop(struct edma *cc, unsigned channel) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < cc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(cc, SH_EECR, j, mask); - edma_shadow0_write_array(cc, SH_ECR, j, mask); - edma_shadow0_write_array(cc, SH_SECR, j, mask); - edma_write_array(cc, EDMA_EMCR, j, mask); - - /* clear possibly pending completion interrupt */ - edma_shadow0_write_array(cc, SH_ICR, j, mask); - - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(cc, SH_EER, j)); - - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } -} -EXPORT_SYMBOL(edma_stop); - -/****************************************************************************** - * - * It cleans ParamEntry qand bring back EDMA to initial state if media has - * been removed before EDMA has finished.It is usedful for removable media. - * Arguments: - * ch_no - channel no - * - * Return: zero on success, or corresponding error no on failure - * - * FIXME this should not be needed ... edma_stop() should suffice. - * - *****************************************************************************/ - -void edma_clean_channel(struct edma *cc, unsigned channel) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < cc->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); - - pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(cc, EDMA_EMR, j)); - edma_shadow0_write_array(cc, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(cc, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(cc, SH_SECR, j, mask); - edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } -} -EXPORT_SYMBOL(edma_clean_channel); - -/* - * edma_assign_channel_eventq - move given channel to desired eventq - * Arguments: - * channel - channel number - * eventq_no - queue to move the channel - * - * Can be used to move a channel to a selected event queue. - */ -void edma_assign_channel_eventq(struct edma *cc, unsigned channel, - enum dma_event_q eventq_no) -{ - if (cc->id != EDMA_CTLR(channel)) { - dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - cc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= cc->num_channels) - return; - - /* default to low priority queue */ - if (eventq_no == EVENTQ_DEFAULT) - eventq_no = cc->default_queue; - if (eventq_no >= cc->num_tc) - return; - - map_dmach_queue(cc, channel, eventq_no); -} -EXPORT_SYMBOL(edma_assign_channel_eventq); - -struct edma *edma_get_data(struct device *edma_dev) -{ - return dev_get_drvdata(edma_dev); -} - - -static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, - struct edma *edma_cc, int cc_id) -{ - int i; - u32 value, cccfg; - s8 (*queue_priority_map)[2]; - - /* Decode the eDMA3 configuration from CCCFG register */ - cccfg = edma_read(edma_cc, EDMA_CCCFG); - - value = GET_NUM_REGN(cccfg); - edma_cc->num_region = BIT(value); - - value = GET_NUM_DMACH(cccfg); - edma_cc->num_channels = BIT(value + 1); - - value = GET_NUM_PAENTRY(cccfg); - edma_cc->num_slots = BIT(value + 4); - - value = GET_NUM_EVQUE(cccfg); - edma_cc->num_tc = value + 1; - - dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id, - cccfg); - dev_dbg(dev, "num_region: %u\n", edma_cc->num_region); - dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels); - dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots); - dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc); - - /* Nothing need to be done if queue priority is provided */ - if (pdata->queue_priority_mapping) - return 0; - - /* - * Configure TC/queue priority as follows: - * Q0 - priority 0 - * Q1 - priority 1 - * Q2 - priority 2 - * ... - * The meaning of priority numbers: 0 highest priority, 7 lowest - * priority. So Q0 is the highest priority queue and the last queue has - * the lowest priority. - */ - queue_priority_map = devm_kzalloc(dev, - (edma_cc->num_tc + 1) * sizeof(s8), - GFP_KERNEL); - if (!queue_priority_map) - return -ENOMEM; - - for (i = 0; i < edma_cc->num_tc; i++) { - queue_priority_map[i][0] = i; - queue_priority_map[i][1] = i; - } - queue_priority_map[i][0] = -1; - queue_priority_map[i][1] = -1; - - pdata->queue_priority_mapping = queue_priority_map; - /* Default queue has the lowest priority */ - pdata->default_queue = i - 1; - - return 0; -} - -#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) - -static int edma_xbar_event_map(struct device *dev, struct device_node *node, - struct edma_soc_info *pdata, size_t sz) -{ - const char pname[] = "ti,edma-xbar-event-map"; - struct resource res; - void __iomem *xbar; - s16 (*xbar_chans)[2]; - size_t nelm = sz / sizeof(s16); - u32 shift, offset, mux; - int ret, i; - - xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); - if (!xbar_chans) - return -ENOMEM; - - ret = of_address_to_resource(node, 1, &res); - if (ret) - return -ENOMEM; - - xbar = devm_ioremap(dev, res.start, resource_size(&res)); - if (!xbar) - return -ENOMEM; - - ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm); - if (ret) - return -EIO; - - /* Invalidate last entry for the other user of this mess */ - nelm >>= 1; - xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1; - - for (i = 0; i < nelm; i++) { - shift = (xbar_chans[i][1] & 0x03) << 3; - offset = xbar_chans[i][1] & 0xfffffffc; - mux = readl(xbar + offset); - mux &= ~(0xff << shift); - mux |= xbar_chans[i][0] << shift; - writel(mux, (xbar + offset)); - } - - pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; - return 0; -} - -static int edma_of_parse_dt(struct device *dev, - struct device_node *node, - struct edma_soc_info *pdata) -{ - int ret = 0; - struct property *prop; - size_t sz; - struct edma_rsv_info *rsv_info; - - rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); - if (!rsv_info) - return -ENOMEM; - pdata->rsv = rsv_info; - - prop = of_find_property(node, "ti,edma-xbar-event-map", &sz); - if (prop) - ret = edma_xbar_event_map(dev, node, pdata, sz); - - return ret; -} - -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, - struct device_node *node) -{ - struct edma_soc_info *info; - int ret; - - info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); - if (!info) - return ERR_PTR(-ENOMEM); - - ret = edma_of_parse_dt(dev, node, info); - if (ret) - return ERR_PTR(ret); - - return info; -} -#else -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, - struct device_node *node) -{ - return ERR_PTR(-ENOSYS); -} -#endif - -static int edma_probe(struct platform_device *pdev) -{ - struct edma_soc_info *info = pdev->dev.platform_data; - s8 (*queue_priority_mapping)[2]; - int i, off, ln; - const s16 (*rsv_chans)[2]; - const s16 (*rsv_slots)[2]; - const s16 (*xbar_chans)[2]; - int irq; - char *irq_name; - struct resource *mem; - struct device_node *node = pdev->dev.of_node; - struct device *dev = &pdev->dev; - int dev_id = pdev->id; - struct edma *cc; - int ret; - struct platform_device_info edma_dev_info = { - .name = "edma-dma-engine", - .dma_mask = DMA_BIT_MASK(32), - .parent = &pdev->dev, - }; - - if (node) { - info = edma_setup_info_from_dt(dev, node); - if (IS_ERR(info)) { - dev_err(dev, "failed to get DT data\n"); - return PTR_ERR(info); - } - } - - if (!info) - return -ENODEV; - - pm_runtime_enable(dev); - ret = pm_runtime_get_sync(dev); - if (ret < 0) { - dev_err(dev, "pm_runtime_get_sync() failed\n"); - return ret; - } - - mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); - if (!mem) { - dev_dbg(dev, "mem resource not found, using index 0\n"); - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - dev_err(dev, "no mem resource?\n"); - return -ENODEV; - } - } - - cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL); - if (!cc) - return -ENOMEM; - - cc->dev = dev; - cc->id = dev_id; - /* When booting with DT the pdev->id is -1 */ - if (dev_id < 0) { - cc->id = 0; - dev_id = arch_num_cc; - } - dev_set_drvdata(dev, cc); - - cc->base = devm_ioremap_resource(dev, mem); - if (IS_ERR(cc->base)) - return PTR_ERR(cc->base); - - /* Get eDMA3 configuration from IP */ - ret = edma_setup_from_hw(dev, info, cc, dev_id); - if (ret) - return ret; - - cc->default_queue = info->default_queue; - - for (i = 0; i < cc->num_slots; i++) - memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset, - PARM_SIZE); - - /* Mark all channels as unused */ - memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused)); - - if (info->rsv) { - - /* Clear the reserved channels in unused list */ - rsv_chans = info->rsv->rsv_chans; - if (rsv_chans) { - for (i = 0; rsv_chans[i][0] != -1; i++) { - off = rsv_chans[i][0]; - ln = rsv_chans[i][1]; - clear_bits(off, ln, cc->edma_unused); - } - } - - /* Set the reserved slots in inuse list */ - rsv_slots = info->rsv->rsv_slots; - if (rsv_slots) { - for (i = 0; rsv_slots[i][0] != -1; i++) { - off = rsv_slots[i][0]; - ln = rsv_slots[i][1]; - set_bits(off, ln, cc->edma_inuse); - } - } - } - - /* Clear the xbar mapped channels in unused list */ - xbar_chans = info->xbar_chans; - if (xbar_chans) { - for (i = 0; xbar_chans[i][1] != -1; i++) { - off = xbar_chans[i][1]; - clear_bits(off, 1, cc->edma_unused); - } - } - - irq = platform_get_irq_byname(pdev, "edma3_ccint"); - if (irq < 0 && node) - irq = irq_of_parse_and_map(node, 0); - - if (irq >= 0) { - irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", - dev_name(dev)); - ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, - cc); - if (ret) { - dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); - return ret; - } - } - - irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); - if (irq < 0 && node) - irq = irq_of_parse_and_map(node, 2); - - if (irq >= 0) { - irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", - dev_name(dev)); - ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, - cc); - if (ret) { - dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); - return ret; - } - } - - for (i = 0; i < cc->num_channels; i++) - map_dmach_queue(cc, i, info->default_queue); - - queue_priority_mapping = info->queue_priority_mapping; - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(cc, queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - /* Map the channel to param entry if channel mapping logic exist */ - if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(cc); - - for (i = 0; i < cc->num_region; i++) { - edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0); - edma_write_array(cc, EDMA_QRAE, i, 0x0); - } - cc->info = info; - arch_num_cc++; - - edma_dev_info.id = dev_id; - - platform_device_register_full(&edma_dev_info); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int edma_pm_resume(struct device *dev) -{ - struct edma *cc = dev_get_drvdata(dev); - int i; - s8 (*queue_priority_mapping)[2]; - - queue_priority_mapping = cc->info->queue_priority_mapping; - - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(cc, queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); - - /* Map the channel to param entry if channel mapping logic */ - if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(cc); - - for (i = 0; i < cc->num_channels; i++) { - if (test_bit(i, cc->edma_inuse)) { - /* ensure access through shadow region 0 */ - edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); - - setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i), - cc->intr_data[i].callback, - cc->intr_data[i].data); - } - } - - return 0; -} -#endif - -static const struct dev_pm_ops edma_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) -}; - -static struct platform_driver edma_driver = { - .driver = { - .name = "edma", - .pm = &edma_pm_ops, - .of_match_table = edma_of_ids, - }, - .probe = edma_probe, -}; - -static int __init edma_init(void) -{ - return platform_driver_probe(&edma_driver, edma_probe); -} -arch_initcall(edma_init); - diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 07d2e100caab..e0b6736db984 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -90,7 +90,6 @@ config ARCH_OMAP2PLUS select OMAP_GPMC select PINCTRL select SOC_BUS - select TI_PRIV_EDMA select OMAP_IRQCHIP help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index b4584757dae0..992efc8e465e 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -486,7 +486,6 @@ config TI_EDMA depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE select DMA_ENGINE select DMA_VIRTUAL_CHANNELS - select TI_PRIV_EDMA default n help Enable support for the TI EDMA controller. This DMA diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index fc91ab9dd1bb..aeb67e0cc523 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -26,12 +26,92 @@ #include #include #include +#include +#include +#include +#include #include #include "dmaengine.h" #include "virt-dma.h" +/* Offsets matching "struct edmacc_param" */ +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c + +#define PARM_SIZE 0x20 + +/* Offsets for EDMA CC global channel registers and their shadows */ +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 + +/* Offsets for EDMA CC global registers */ +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 + +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 shadow regions */ +#define EDMA_PARM 0x4000 /* PaRAM entries */ + +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) + +#define EDMA_DCHMAP 0x0100 /* 64 registers */ + +/* CCCFG register */ +#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ +#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ +#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ +#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ +#define CHMAP_EXIST BIT(24) + /* * This will go away when the private EDMA API is folded * into this driver and the platform device(s) are @@ -60,6 +140,47 @@ #define EDMA_MAX_SLOTS MAX_NR_SG #define EDMA_DESCRIPTORS 16 +#define EDMA_MAX_PARAMENTRY 512 + +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 + +#define EDMA_MAX_CC 2 + +/* PaRAM slots are laid out like this */ +struct edmacc_param { + u32 opt; + u32 src; + u32 a_b_cnt; + u32 dst; + u32 src_dst_bidx; + u32 link_bcntrld; + u32 src_dst_cidx; + u32 ccnt; +} __packed; + +/* fields in edmacc_param.opt */ +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) + +/*ch_status parameter of callback function possible values*/ +#define EDMA_DMA_COMPLETE 1 +#define EDMA_DMA_CC_ERROR 2 +#define EDMA_DMA_TC1_ERROR 3 +#define EDMA_DMA_TC2_ERROR 4 + struct edma_pset { u32 len; dma_addr_t addr; @@ -119,14 +240,929 @@ struct edma_chan { }; struct edma_cc { - struct edma *cc; - int ctlr; + struct device *dev; + struct edma_soc_info *info; + void __iomem *base; + int id; + + /* eDMA3 resource information */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + enum dma_event_q default_queue; + + bool unused_chan_list_done; + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + + /* The edma_unused bit for each channel is clear unless + * it is not being used on this platform. It uses a bit + * of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_unused, EDMA_CHANS); + + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_CHANS]; + struct dma_device dma_slave; struct edma_chan slave_chans[EDMA_CHANS]; - int num_slave_chans; int dummy_slot; }; +/* dummy param set used to (re)initialize parameter RAM slots */ +static const struct edmacc_param dummy_paramset = { + .link_bcntrld = 0xffff, + .ccnt = 1, +}; + +static const struct of_device_id edma_of_ids[] = { + { .compatible = "ti,edma3", }, + {} +}; + +static inline unsigned int edma_read(struct edma_cc *ecc, int offset) +{ + return (unsigned int)__raw_readl(ecc->base + offset); +} + +static inline void edma_write(struct edma_cc *ecc, int offset, int val) +{ + __raw_writel(val, ecc->base + offset); +} + +static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, + unsigned or) +{ + unsigned val = edma_read(ecc, offset); + + val &= and; + val |= or; + edma_write(ecc, offset, val); +} + +static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) +{ + unsigned val = edma_read(ecc, offset); + + val &= and; + edma_write(ecc, offset, val); +} + +static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) +{ + unsigned val = edma_read(ecc, offset); + + val |= or; + edma_write(ecc, offset, val); +} + +static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, + int i) +{ + return edma_read(ecc, offset + (i << 2)); +} + +static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, + unsigned val) +{ + edma_write(ecc, offset + (i << 2), val); +} + +static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, + unsigned and, unsigned or) +{ + edma_modify(ecc, offset + (i << 2), and, or); +} + +static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, + unsigned or) +{ + edma_or(ecc, offset + (i << 2), or); +} + +static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, + unsigned or) +{ + edma_or(ecc, offset + ((i * 2 + j) << 2), or); +} + +static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, + int j, unsigned val) +{ + edma_write(ecc, offset + ((i * 2 + j) << 2), val); +} + +static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) +{ + return edma_read(ecc, EDMA_SHADOW0 + offset); +} + +static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, + int offset, int i) +{ + return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); +} + +static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, + unsigned val) +{ + edma_write(ecc, EDMA_SHADOW0 + offset, val); +} + +static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, + int i, unsigned val) +{ + edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); +} + +static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset, + int param_no) +{ + return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); +} + +static inline void edma_parm_write(struct edma_cc *ecc, int offset, + int param_no, unsigned val) +{ + edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); +} + +static inline void edma_parm_modify(struct edma_cc *ecc, int offset, + int param_no, unsigned and, unsigned or) +{ + edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); +} + +static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no, + unsigned and) +{ + edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); +} + +static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no, + unsigned or) +{ + edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); +} + +static inline void set_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + set_bit(offset + (len - 1), p); +} + +static inline void clear_bits(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); +} + +static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no, + enum dma_event_q queue_no) +{ + int bit = (ch_no & 0x7) * 4; + + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = ecc->default_queue; + + queue_no &= 7; + edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), + queue_no << bit); +} + +static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, + int priority) +{ + int bit = queue_no * 4; + + edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); +} + +static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc) +{ + int i; + + for (i = 0; i < ecc->num_channels; i++) + edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5)); +} + +static int prepare_unused_channel_list(struct device *dev, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct edma_cc *ecc = data; + int i, count; + struct of_phandle_args dma_spec; + + if (dev->of_node) { + struct platform_device *dma_pdev; + + count = of_property_count_strings(dev->of_node, "dma-names"); + if (count < 0) + return 0; + for (i = 0; i < count; i++) { + if (of_parse_phandle_with_args(dev->of_node, "dmas", + "#dma-cells", i, + &dma_spec)) + continue; + + if (!of_match_node(edma_of_ids, dma_spec.np)) { + of_node_put(dma_spec.np); + continue; + } + + dma_pdev = of_find_device_by_node(dma_spec.np); + if (&dma_pdev->dev != ecc->dev) + continue; + + clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), + ecc->edma_unused); + of_node_put(dma_spec.np); + } + return 0; + } + + /* For non-OF case */ + for (i = 0; i < pdev->num_resources; i++) { + struct resource *res = &pdev->resource[i]; + + if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { + clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), + ecc->edma_unused); + } + } + + return 0; +} + +static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data) +{ + lch = EDMA_CHAN_SLOT(lch); + + if (!callback) + edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); + + ecc->intr_data[lch].callback = callback; + ecc->intr_data[lch].data = data; + + if (callback) { + edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, + BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); + } +} + +/* + * paRAM management functions + */ + +/** + * edma_write_slot - write parameter RAM data for slot + * @ecc: pointer to edma_cc struct + * @slot: number of parameter RAM slot being modified + * @param: data to be written into parameter RAM slot + * + * Use this to assign all parameters of a transfer at once. This + * allows more efficient setup of transfers than issuing multiple + * calls to set up those parameters in small pieces, and provides + * complete control over all transfer options. + */ +static void edma_write_slot(struct edma_cc *ecc, unsigned slot, + const struct edmacc_param *param) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot >= ecc->num_slots) + return; + memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); +} + +/** + * edma_read_slot - read parameter RAM data from slot + * @ecc: pointer to edma_cc struct + * @slot: number of parameter RAM slot being copied + * @param: where to store copy of parameter RAM data + * + * Use this to read data from a parameter RAM slot, perhaps to + * save them as a template for later reuse. + */ +static void edma_read_slot(struct edma_cc *ecc, unsigned slot, + struct edmacc_param *param) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot >= ecc->num_slots) + return; + memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); +} + +/** + * edma_alloc_slot - allocate DMA parameter RAM + * @ecc: pointer to edma_cc struct + * @slot: specific slot to allocate; negative for "any unused slot" + * + * This allocates a parameter RAM slot, initializing it to hold a + * dummy transfer. Slots allocated using this routine have not been + * mapped to a hardware DMA channel, and will normally be used by + * linking to them from a slot associated with a DMA channel. + * + * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific + * slots may be allocated on behalf of DSP firmware. + * + * Returns the number of the slot, else negative errno. + */ +static int edma_alloc_slot(struct edma_cc *ecc, int slot) +{ + if (slot > 0) + slot = EDMA_CHAN_SLOT(slot); + if (slot < 0) { + slot = ecc->num_channels; + for (;;) { + slot = find_next_zero_bit(ecc->edma_inuse, + ecc->num_slots, + slot); + if (slot == ecc->num_slots) + return -ENOMEM; + if (!test_and_set_bit(slot, ecc->edma_inuse)) + break; + } + } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { + return -EINVAL; + } else if (test_and_set_bit(slot, ecc->edma_inuse)) { + return -EBUSY; + } + + edma_write_slot(ecc, slot, &dummy_paramset); + + return EDMA_CTLR_CHAN(ecc->id, slot); +} + +/** + * edma_free_slot - deallocate DMA parameter RAM + * @ecc: pointer to edma_cc struct + * @slot: parameter RAM slot returned from edma_alloc_slot() + * + * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). + * Callers are responsible for ensuring the slot is inactive, and will + * not be activated. + */ +static void edma_free_slot(struct edma_cc *ecc, unsigned slot) +{ + slot = EDMA_CHAN_SLOT(slot); + if (slot < ecc->num_channels || slot >= ecc->num_slots) + return; + + edma_write_slot(ecc, slot, &dummy_paramset); + clear_bit(slot, ecc->edma_inuse); +} + +/** + * edma_link - link one parameter RAM slot to another + * @ecc: pointer to edma_cc struct + * @from: parameter RAM slot originating the link + * @to: parameter RAM slot which is the link target + * + * The originating slot should not be part of any active DMA transfer. + */ +static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) +{ + from = EDMA_CHAN_SLOT(from); + to = EDMA_CHAN_SLOT(to); + if (from >= ecc->num_slots || to >= ecc->num_slots) + return; + + edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); +} + +/** + * edma_get_position - returns the current transfer point + * @ecc: pointer to edma_cc struct + * @slot: parameter RAM slot being examined + * @dst: true selects the dest position, false the source + * + * Returns the position of the current active slot + */ +static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, + bool dst) +{ + u32 offs; + + slot = EDMA_CHAN_SLOT(slot); + offs = PARM_OFFSET(slot); + offs += dst ? PARM_DST : PARM_SRC; + + return edma_read(ecc, offs); +} + +/*-----------------------------------------------------------------------*/ +/** + * edma_start - start dma on a channel + * @ecc: pointer to edma_cc struct + * @channel: channel being activated + * + * Channels with event associations will be triggered by their hardware + * events, and channels without such associations will be triggered by + * software. (At this writing there is no interface for using software + * triggers except with channels that don't support hardware triggers.) + * + * Returns zero on success, else negative errno. + */ +static int edma_start(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); + + /* EDMA channels without event association */ + if (test_bit(channel, ecc->edma_unused)) { + pr_debug("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); + edma_shadow0_write_array(ecc, SH_ESR, j, mask); + return 0; + } + + /* EDMA channel with event association */ + pr_debug("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ER, j)); + /* Clear any pending event or error */ + edma_write_array(ecc, EDMA_ECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_shadow0_write_array(ecc, SH_EESR, j, mask); + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); + return 0; + } + + return -EINVAL; +} + +/** + * edma_stop - stops dma on the channel passed + * @ecc: pointer to edma_cc struct + * @channel: channel being deactivated + * + * When @lch is a channel, any active transfer is paused and + * all pending hardware events are cleared. The current transfer + * may not be resumed, and the channel's Parameter RAM should be + * reinitialized before being reused. + */ +static void edma_stop(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EECR, j, mask); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); + + /* clear possibly pending completion interrupt */ + edma_shadow0_write_array(ecc, SH_ICR, j, mask); + + pr_debug("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); + + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } +} + +/** + * edma_pause - pause dma on a channel + * @ecc: pointer to edma_cc struct + * @channel: on which edma_start() has been called + * + * This temporarily disables EDMA hardware events on the specified channel, + * preventing them from triggering new transfers on its behalf + */ +static void edma_pause(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask); + } +} + +/** + * edma_resume - resumes dma on a paused channel + * @ecc: pointer to edma_cc struct + * @channel: on which edma_pause() has been called + * + * This re-enables EDMA hardware events on the specified channel. + */ +static void edma_resume(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + unsigned int mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask); + } +} + +static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) +{ + unsigned int mask; + + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + mask = BIT(channel & 0x1f); + + edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); + + pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + return 0; +} + +/****************************************************************************** + * + * It cleans ParamEntry qand bring back EDMA to initial state if media has + * been removed before EDMA has finished.It is usedful for removable media. + * Arguments: + * ch_no - channel no + * + * Return: zero on success, or corresponding error no on failure + * + * FIXME this should not be needed ... edma_stop() should suffice. + * + *****************************************************************************/ + +static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel < ecc->num_channels) { + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); + + pr_debug("EDMA: EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + } +} + +/** + * edma_alloc_channel - allocate DMA channel and paired parameter RAM + * @ecc: pointer to edma_cc struct + * @channel: specific channel to allocate; negative for "any unmapped channel" + * @callback: optional; to be issued on DMA completion or errors + * @data: passed to callback + * @eventq_no: an EVENTQ_* constant, used to choose which Transfer + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. + * + * This allocates a DMA channel and its associated parameter RAM slot. + * The parameter RAM is initialized to hold a dummy transfer. + * + * Normal use is to pass a specific channel number as @channel, to make + * use of hardware events mapped to that channel. When the channel will + * be used only for software triggering or event chaining, channels not + * mapped to hardware events (or mapped to unused events) are preferable. + * + * DMA transfers start from a channel using edma_start(), or by + * chaining. When the transfer described in that channel's parameter RAM + * slot completes, that slot's data may be reloaded through a link. + * + * DMA errors are only reported to the @callback associated with the + * channel driving that transfer, but transfer completion callbacks can + * be sent to another channel under control of the TCC field in + * the option word of the transfer's parameter RAM set. Drivers must not + * use DMA transfer completion callbacks for channels they did not allocate. + * (The same applies to TCC codes used in transfer chaining.) + * + * Returns the number of the channel, else negative errno. + */ +static int edma_alloc_channel(struct edma_cc *ecc, int channel, + void (*callback)(unsigned channel, u16 ch_status, void *data), + void *data, + enum dma_event_q eventq_no) +{ + unsigned done = 0; + int ret = 0; + + if (!ecc->unused_chan_list_done) { + /* + * Scan all the platform devices to find out the EDMA channels + * used and clear them in the unused list, making the rest + * available for ARM usage. + */ + ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, + prepare_unused_channel_list); + if (ret < 0) + return ret; + + ecc->unused_chan_list_done = true; + } + + if (channel >= 0) { + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", + __func__, ecc->id, EDMA_CTLR(channel)); + return -EINVAL; + } + channel = EDMA_CHAN_SLOT(channel); + } + + if (channel < 0) { + channel = 0; + for (;;) { + channel = find_next_bit(ecc->edma_unused, + ecc->num_channels, channel); + if (channel == ecc->num_channels) + break; + if (!test_and_set_bit(channel, ecc->edma_inuse)) { + done = 1; + break; + } + channel++; + } + if (!done) + return -ENOMEM; + } else if (channel >= ecc->num_channels) { + return -EINVAL; + } else if (test_and_set_bit(channel, ecc->edma_inuse)) { + return -EBUSY; + } + + /* ensure access through shadow region 0 */ + edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + + /* ensure no events are pending */ + edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); + edma_write_slot(ecc, channel, &dummy_paramset); + + if (callback) + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), + callback, data); + + edma_map_dmach_to_queue(ecc, channel, eventq_no); + + return EDMA_CTLR_CHAN(ecc->id, channel); +} + +/** + * edma_free_channel - deallocate DMA channel + * @ecc: pointer to edma_cc struct + * @channel: dma channel returned from edma_alloc_channel() + * + * This deallocates the DMA channel and associated parameter RAM slot + * allocated by edma_alloc_channel(). + * + * Callers are responsible for ensuring the channel is inactive, and + * will not be reactivated by linking, chaining, or software calls to + * edma_start(). + */ +static void edma_free_channel(struct edma_cc *ecc, unsigned channel) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= ecc->num_channels) + return; + + edma_setup_interrupt(ecc, channel, NULL, NULL); + /* REVISIT should probably take out of shadow region 0 */ + + memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset, + PARM_SIZE); + clear_bit(channel, ecc->edma_inuse); +} + +/* + * edma_assign_channel_eventq - move given channel to desired eventq + * Arguments: + * channel - channel number + * eventq_no - queue to move the channel + * + * Can be used to move a channel to a selected event queue. + */ +static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, + enum dma_event_q eventq_no) +{ + if (ecc->id != EDMA_CTLR(channel)) { + dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, + ecc->id, EDMA_CTLR(channel)); + return; + } + channel = EDMA_CHAN_SLOT(channel); + + if (channel >= ecc->num_channels) + return; + + /* default to low priority queue */ + if (eventq_no == EVENTQ_DEFAULT) + eventq_no = ecc->default_queue; + if (eventq_no >= ecc->num_tc) + return; + + edma_map_dmach_to_queue(ecc, channel, eventq_no); +} + +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int ctlr; + u32 sh_ier; + u32 sh_ipr; + u32 bank; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_dbg(ecc->dev, "dma_irq_handler\n"); + + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); + if (!sh_ipr) { + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); + if (!sh_ipr) + return IRQ_NONE; + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); + bank = 1; + } else { + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); + bank = 0; + } + + do { + u32 slot; + u32 channel; + + dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr); + + slot = __ffs(sh_ipr); + sh_ipr &= ~(BIT(slot)); + + if (sh_ier & BIT(slot)) { + channel = (bank << 5) | slot; + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); + if (ecc->intr_data[channel].callback) + ecc->intr_data[channel].callback( + EDMA_CTLR_CHAN(ctlr, channel), + EDMA_DMA_COMPLETE, + ecc->intr_data[channel].data); + } + } while (sh_ipr); + + edma_shadow0_write(ecc, SH_IEVAL, 1); + return IRQ_HANDLED; +} + +/****************************************************************************** + * + * DMA error interrupt handler + * + *****************************************************************************/ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_dbg(ecc->dev, "dma_ccerr_handler\n"); + + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + + if (edma_read_array(ecc, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ecc, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + + if (edma_read_array(ecc, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, + j, BIT(i)); + if (ecc->intr_data[k].callback) { + ecc->intr_data[k].callback( + EDMA_CTLR_CHAN(ctlr, k), + EDMA_DMA_CC_ERROR, + ecc->intr_data[k].data); + } + } + } + } else if (edma_read(ecc, EDMA_QEMR)) { + dev_dbg(ecc->dev, "QEMR %02x\n", + edma_read(ecc, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ecc, SH_QSECR, + BIT(i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ecc, EDMA_CCERR)) { + dev_dbg(ecc->dev, "CCERR %08x\n", + edma_read(ecc, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_CCERRCLR, BIT(i)); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ecc, EDMA_EEVAL, 1); + return IRQ_HANDLED; +} + static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -137,8 +1173,7 @@ static inline struct edma_chan *to_edma_chan(struct dma_chan *c) return container_of(c, struct edma_chan, vchan.chan); } -static inline struct edma_desc -*to_edma_desc(struct dma_async_tx_descriptor *tx) +static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) { return container_of(tx, struct edma_desc, vdesc.tx); } @@ -151,7 +1186,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc) /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { - struct edma *cc = echan->ecc->cc; + struct edma_cc *ecc = echan->ecc; struct virt_dma_desc *vdesc; struct edma_desc *edesc; struct device *dev = echan->vchan.chan.device->dev; @@ -176,7 +1211,7 @@ static void edma_execute(struct edma_chan *echan) /* Write descriptor PaRAM set(s) */ for (i = 0; i < nslots; i++) { j = i + edesc->processed; - edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param); + edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; dev_vdbg(echan->vchan.chan.device->dev, "\n pset[%d]:\n" @@ -201,7 +1236,7 @@ static void edma_execute(struct edma_chan *echan) edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) - edma_link(cc, echan->slot[i], echan->slot[i+1]); + edma_link(ecc, echan->slot[i], echan->slot[i + 1]); } edesc->processed += nslots; @@ -213,9 +1248,9 @@ static void edma_execute(struct edma_chan *echan) */ if (edesc->processed == edesc->pset_nr) { if (edesc->cyclic) - edma_link(cc, echan->slot[nslots-1], echan->slot[1]); + edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); else - edma_link(cc, echan->slot[nslots-1], + edma_link(ecc, echan->slot[nslots - 1], echan->ecc->dummy_slot); } @@ -226,19 +1261,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(cc, echan->ch_num); - edma_stop(cc, echan->ch_num); - edma_start(cc, echan->ch_num); - edma_trigger_channel(cc, echan->ch_num); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(cc, echan->ch_num); + edma_start(ecc, echan->ch_num); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(cc, echan->ch_num); + edma_resume(ecc, echan->ch_num); } } @@ -256,11 +1291,10 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ecc->cc, echan->ch_num); + edma_stop(echan->ecc, echan->ch_num); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ecc->cc, - echan->ch_num, + edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -298,7 +1332,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ecc->cc, echan->ch_num); + edma_pause(echan->ecc, echan->ch_num); return 0; } @@ -306,7 +1340,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ecc->cc, echan->ch_num); + edma_resume(echan->ecc, echan->ch_num); return 0; } @@ -322,9 +1356,10 @@ static int edma_dma_resume(struct dma_chan *chan) * @direction: Direction of the transfer */ static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, - dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, - enum dma_slave_buswidth dev_width, unsigned int dma_length, - enum dma_transfer_direction direction) + dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, + enum dma_slave_buswidth dev_width, + unsigned int dma_length, + enum dma_transfer_direction direction) { struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; @@ -470,8 +1505,8 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( return NULL; } - edesc = kzalloc(sizeof(*edesc) + sg_len * - sizeof(edesc->pset[0]), GFP_ATOMIC); + edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); return NULL; @@ -488,7 +1523,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg( for (i = 0; i < nslots; i++) { if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -623,8 +1658,8 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( if (nslots > MAX_NR_SG) return NULL; - edesc = kzalloc(sizeof(*edesc) + nslots * - sizeof(edesc->pset[0]), GFP_ATOMIC); + edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); return NULL; @@ -643,7 +1678,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( /* Allocate a PaRAM slot, if needed */ if (echan->slot[i] < 0) { echan->slot[i] = - edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY); + edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); if (echan->slot[i] < 0) { kfree(edesc); dev_err(dev, "%s: Failed to allocate slot\n", @@ -704,7 +1739,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -712,7 +1747,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( static void edma_callback(unsigned ch_num, u16 ch_status, void *data) { struct edma_chan *echan = data; - struct edma *cc = echan->ecc->cc; + struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc; struct edmacc_param p; @@ -727,15 +1762,19 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) vchan_cyclic_callback(&edesc->vdesc); goto out; } else if (edesc->processed == edesc->pset_nr) { - dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); + dev_dbg(dev, + "Transfer completed on channel %d\n", + ch_num); edesc->residue = 0; - edma_stop(cc, echan->ch_num); + edma_stop(ecc, echan->ch_num); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; } else { - dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); + dev_dbg(dev, + "Sub transfer completed on channel %d\n", + ch_num); - edma_pause(cc, echan->ch_num); + edma_pause(ecc, echan->ch_num); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -746,7 +1785,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) } break; case EDMA_DMA_CC_ERROR: - edma_read_slot(cc, echan->slot[0], &p); + edma_read_slot(ecc, echan->slot[0], &p); /* * Issue later based on missed flag which will be sure @@ -761,18 +1800,18 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data) * slot. So we avoid doing so and set the missed flag. */ if (p.a_b_cnt == 0 && p.ccnt == 0) { - dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); + dev_dbg(dev, "Error on null slot, setting miss\n"); echan->missed = 1; } else { /* * The slot is already programmed but the event got * missed, so its safe to issue it here. */ - dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); - edma_clean_channel(cc, echan->ch_num); - edma_stop(cc, echan->ch_num); - edma_start(cc, echan->ch_num); - edma_trigger_channel(cc, echan->ch_num); + dev_dbg(dev, "Missed event, TRIGGERING\n"); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); } break; default: @@ -791,7 +1830,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num, + a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, edma_callback, echan, EVENTQ_DEFAULT); if (a_ch_num < 0) { @@ -816,7 +1855,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) return 0; err_wrong_chan: - edma_free_channel(echan->ecc->cc, a_ch_num); + edma_free_channel(echan->ecc, a_ch_num); err_no_chan: return ret; } @@ -829,21 +1868,21 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ecc->cc, echan->ch_num); + edma_stop(echan->ecc, echan->ch_num); vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ for (i = 1; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { - edma_free_slot(echan->ecc->cc, echan->slot[i]); + edma_free_slot(echan->ecc, echan->slot[i]); echan->slot[i] = -1; } } /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ecc->cc, echan->ch_num); + edma_free_channel(echan->ecc, echan->ch_num); echan->alloced = false; } @@ -873,8 +1912,7 @@ static u32 edma_residue(struct edma_desc *edesc) * We always read the dst/src position from the first RamPar * pset. That's the one which is active now. */ - pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0], - dst); + pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); /* * Cyclic is simple. Just subtract pset[0].addr from pos. @@ -935,15 +1973,14 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } -static void __init edma_chan_init(struct edma_cc *ecc, - struct dma_device *dma, +static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, struct edma_chan *echans) { int i, j; for (i = 0; i < EDMA_CHANS; i++) { struct edma_chan *echan = &echans[i]; - echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); + echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; @@ -991,14 +2028,189 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, INIT_LIST_HEAD(&dma->channels); } +static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, + struct edma_cc *ecc) +{ + int i; + u32 value, cccfg; + s8 (*queue_priority_map)[2]; + + /* Decode the eDMA3 configuration from CCCFG register */ + cccfg = edma_read(ecc, EDMA_CCCFG); + + value = GET_NUM_REGN(cccfg); + ecc->num_region = BIT(value); + + value = GET_NUM_DMACH(cccfg); + ecc->num_channels = BIT(value + 1); + + value = GET_NUM_PAENTRY(cccfg); + ecc->num_slots = BIT(value + 4); + + value = GET_NUM_EVQUE(cccfg); + ecc->num_tc = value + 1; + + dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); + dev_dbg(dev, "num_region: %u\n", ecc->num_region); + dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); + dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); + dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); + + /* Nothing need to be done if queue priority is provided */ + if (pdata->queue_priority_mapping) + return 0; + + /* + * Configure TC/queue priority as follows: + * Q0 - priority 0 + * Q1 - priority 1 + * Q2 - priority 2 + * ... + * The meaning of priority numbers: 0 highest priority, 7 lowest + * priority. So Q0 is the highest priority queue and the last queue has + * the lowest priority. + */ + queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8), + GFP_KERNEL); + if (!queue_priority_map) + return -ENOMEM; + + for (i = 0; i < ecc->num_tc; i++) { + queue_priority_map[i][0] = i; + queue_priority_map[i][1] = i; + } + queue_priority_map[i][0] = -1; + queue_priority_map[i][1] = -1; + + pdata->queue_priority_mapping = queue_priority_map; + /* Default queue has the lowest priority */ + pdata->default_queue = i - 1; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF) +static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, + size_t sz) +{ + const char pname[] = "ti,edma-xbar-event-map"; + struct resource res; + void __iomem *xbar; + s16 (*xbar_chans)[2]; + size_t nelm = sz / sizeof(s16); + u32 shift, offset, mux; + int ret, i; + + xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); + if (!xbar_chans) + return -ENOMEM; + + ret = of_address_to_resource(dev->of_node, 1, &res); + if (ret) + return -ENOMEM; + + xbar = devm_ioremap(dev, res.start, resource_size(&res)); + if (!xbar) + return -ENOMEM; + + ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, + nelm); + if (ret) + return -EIO; + + /* Invalidate last entry for the other user of this mess */ + nelm >>= 1; + xbar_chans[nelm][0] = -1; + xbar_chans[nelm][1] = -1; + + for (i = 0; i < nelm; i++) { + shift = (xbar_chans[i][1] & 0x03) << 3; + offset = xbar_chans[i][1] & 0xfffffffc; + mux = readl(xbar + offset); + mux &= ~(0xff << shift); + mux |= xbar_chans[i][0] << shift; + writel(mux, (xbar + offset)); + } + + pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; + return 0; +} + +static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) +{ + int ret = 0; + struct property *prop; + size_t sz; + struct edma_rsv_info *rsv_info; + + rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); + if (!rsv_info) + return -ENOMEM; + pdata->rsv = rsv_info; + + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (prop) + ret = edma_xbar_event_map(dev, pdata, sz); + + return ret; +} + +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +{ + struct edma_soc_info *info; + int ret; + + info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + ret = edma_of_parse_dt(dev, info); + if (ret) + return ERR_PTR(ret); + + return info; +} +#else +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +{ + return ERR_PTR(-EINVAL); +} +#endif + static int edma_probe(struct platform_device *pdev) { - struct edma_cc *ecc; - struct device_node *parent_node = pdev->dev.parent->of_node; - struct platform_device *parent_pdev = - to_platform_device(pdev->dev.parent); + struct edma_soc_info *info = pdev->dev.platform_data; + s8 (*queue_priority_mapping)[2]; + int i, off, ln; + const s16 (*rsv_chans)[2]; + const s16 (*rsv_slots)[2]; + const s16 (*xbar_chans)[2]; + int irq; + char *irq_name; + struct resource *mem; + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct edma_cc *ecc; int ret; + if (node) { + info = edma_setup_info_from_dt(dev); + if (IS_ERR(info)) { + dev_err(dev, "failed to get DT data\n"); + return PTR_ERR(info); + } + } + + if (!info) + return -ENODEV; + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + return ret; + } + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (ret) return ret; @@ -1009,15 +2221,123 @@ static int edma_probe(struct platform_device *pdev) return -ENOMEM; } - ecc->cc = edma_get_data(pdev->dev.parent); - if (!ecc->cc) - return -ENODEV; + ecc->dev = dev; + ecc->id = pdev->id; + /* When booting with DT the pdev->id is -1 */ + if (ecc->id < 0) + ecc->id = 0; - ecc->ctlr = parent_pdev->id; - if (ecc->ctlr < 0) - ecc->ctlr = 0; + mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc"); + if (!mem) { + dev_dbg(dev, "mem resource not found, using index 0\n"); + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(dev, "no mem resource?\n"); + return -ENODEV; + } + } + ecc->base = devm_ioremap_resource(dev, mem); + if (IS_ERR(ecc->base)) + return PTR_ERR(ecc->base); - ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY); + platform_set_drvdata(pdev, ecc); + + /* Get eDMA3 configuration from IP */ + ret = edma_setup_from_hw(dev, info, ecc); + if (ret) + return ret; + + ecc->default_queue = info->default_queue; + + for (i = 0; i < ecc->num_slots; i++) + edma_write_slot(ecc, i, &dummy_paramset); + + /* Mark all channels as unused */ + memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused)); + + if (info->rsv) { + /* Clear the reserved channels in unused list */ + rsv_chans = info->rsv->rsv_chans; + if (rsv_chans) { + for (i = 0; rsv_chans[i][0] != -1; i++) { + off = rsv_chans[i][0]; + ln = rsv_chans[i][1]; + clear_bits(off, ln, ecc->edma_unused); + } + } + + /* Set the reserved slots in inuse list */ + rsv_slots = info->rsv->rsv_slots; + if (rsv_slots) { + for (i = 0; rsv_slots[i][0] != -1; i++) { + off = rsv_slots[i][0]; + ln = rsv_slots[i][1]; + set_bits(off, ln, ecc->edma_inuse); + } + } + } + + /* Clear the xbar mapped channels in unused list */ + xbar_chans = info->xbar_chans; + if (xbar_chans) { + for (i = 0; xbar_chans[i][1] != -1; i++) { + off = xbar_chans[i][1]; + clear_bits(off, 1, ecc->edma_unused); + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 0); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, + ecc); + if (ret) { + dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + irq = platform_get_irq_byname(pdev, "edma3_ccerrint"); + if (irq < 0 && node) + irq = irq_of_parse_and_map(node, 2); + + if (irq >= 0) { + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", + dev_name(dev)); + ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, + ecc); + if (ret) { + dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); + return ret; + } + } + + for (i = 0; i < ecc->num_channels; i++) + edma_map_dmach_to_queue(ecc, i, info->default_queue); + + queue_priority_mapping = info->queue_priority_mapping; + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic exist */ + if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + edma_direct_dmach_to_param_mapping(ecc); + + for (i = 0; i < ecc->num_region; i++) { + edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); + edma_write_array(ecc, EDMA_QRAE, i, 0x0); + } + ecc->info = info; + + ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; @@ -1036,19 +2356,16 @@ static int edma_probe(struct platform_device *pdev) if (ret) goto err_reg1; - platform_set_drvdata(pdev, ecc); - - if (parent_node) { - of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id, + if (node) + of_dma_controller_register(node, of_dma_xlate_by_chan_id, &ecc->dma_slave); - } dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); return 0; err_reg1: - edma_free_slot(ecc->cc, ecc->dummy_slot); + edma_free_slot(ecc, ecc->dummy_slot); return ret; } @@ -1056,21 +2373,60 @@ static int edma_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); - struct device_node *parent_node = pdev->dev.parent->of_node; - if (parent_node) - of_dma_controller_free(parent_node); + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&ecc->dma_slave); - edma_free_slot(ecc->cc, ecc->dummy_slot); + edma_free_slot(ecc, ecc->dummy_slot); return 0; } +#ifdef CONFIG_PM_SLEEP +static int edma_pm_resume(struct device *dev) +{ + struct edma_cc *ecc = dev_get_drvdata(dev); + int i; + s8 (*queue_priority_mapping)[2]; + + queue_priority_mapping = ecc->info->queue_priority_mapping; + + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); + + /* Map the channel to param entry if channel mapping logic */ + if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + edma_direct_dmach_to_param_mapping(ecc); + + for (i = 0; i < ecc->num_channels; i++) { + if (test_bit(i, ecc->edma_inuse)) { + /* ensure access through shadow region 0 */ + edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, + BIT(i & 0x1f)); + + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), + ecc->intr_data[i].callback, + ecc->intr_data[i].data); + } + } + + return 0; +} +#endif + +static const struct dev_pm_ops edma_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) +}; + static struct platform_driver edma_driver = { .probe = edma_probe, .remove = edma_remove, .driver = { - .name = "edma-dma-engine", + .name = "edma", + .pm = &edma_pm_ops, + .of_match_table = edma_of_ids, }, }; diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index 466021c03169..6b9d500956e4 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h @@ -41,37 +41,6 @@ #ifndef EDMA_H_ #define EDMA_H_ -/* PaRAM slots are laid out like this */ -struct edmacc_param { - u32 opt; - u32 src; - u32 a_b_cnt; - u32 dst; - u32 src_dst_bidx; - u32 link_bcntrld; - u32 src_dst_cidx; - u32 ccnt; -} __packed; - -/* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) - -/*ch_status paramater of callback function possible values*/ -#define EDMA_DMA_COMPLETE 1 -#define EDMA_DMA_CC_ERROR 2 -#define EDMA_DMA_TC1_ERROR 3 -#define EDMA_DMA_TC2_ERROR 4 - enum dma_event_q { EVENTQ_0 = 0, EVENTQ_1 = 1, @@ -84,49 +53,6 @@ enum dma_event_q { #define EDMA_CTLR(i) ((i) >> 16) #define EDMA_CHAN_SLOT(i) ((i) & 0xffff) -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 -#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 - -#define EDMA_MAX_CC 2 - -struct edma; - -struct edma *edma_get_data(struct device *edma_dev); - -/* alloc/free DMA channels and their dedicated parameter RAM slots */ -int edma_alloc_channel(struct edma *cc, int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, enum dma_event_q); -void edma_free_channel(struct edma *cc, unsigned channel); - -/* alloc/free parameter RAM slots */ -int edma_alloc_slot(struct edma *cc, int slot); -void edma_free_slot(struct edma *cc, unsigned slot); - -/* calls that operate on part of a parameter RAM slot */ -dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst); -void edma_link(struct edma *cc, unsigned from, unsigned to); - -/* calls that operate on an entire parameter RAM slot */ -void edma_write_slot(struct edma *cc, unsigned slot, - const struct edmacc_param *params); -void edma_read_slot(struct edma *cc, unsigned slot, - struct edmacc_param *params); - -/* channel control operations */ -int edma_start(struct edma *cc, unsigned channel); -void edma_stop(struct edma *cc, unsigned channel); -void edma_clean_channel(struct edma *cc, unsigned channel); -void edma_pause(struct edma *cc, unsigned channel); -void edma_resume(struct edma *cc, unsigned channel); -int edma_trigger_channel(struct edma *cc, unsigned channel); - -void edma_assign_channel_eventq(struct edma *cc, unsigned channel, - enum dma_event_q eventq_no); - struct edma_rsv_info { const s16 (*rsv_chans)[2]; From cb78205955d4a2c26c18984896b81cc63b416f63 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:54 +0300 Subject: [PATCH 40/77] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Instead of using defines to specify the size of different arrays and bitmaps, allocate the memory for them based on the information we get from the HW itself. Since these defines are set based on the worst case, there are devices where they are not valid. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 62 +++++++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index aeb67e0cc523..d5a76c67f83f 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -112,23 +112,6 @@ #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ #define CHMAP_EXIST BIT(24) -/* - * This will go away when the private EDMA API is folded - * into this driver and the platform device(s) are - * instantiated in the arch code. We can only get away - * with this simplification because DA8XX may not be built - * in the same kernel image with other DaVinci parts. This - * avoids having to sprinkle dmaengine driver platform devices - * and data throughout all the existing board files. - */ -#ifdef CONFIG_ARCH_DAVINCI_DA8XX -#define EDMA_CTLRS 2 -#define EDMA_CHANS 32 -#else -#define EDMA_CTLRS 1 -#define EDMA_CHANS 64 -#endif /* CONFIG_ARCH_DAVINCI_DA8XX */ - /* * Max of 20 segments per channel to conserve PaRAM slots * Also note that MAX_NR_SG should be atleast the no.of periods @@ -140,16 +123,12 @@ #define EDMA_MAX_SLOTS MAX_NR_SG #define EDMA_DESCRIPTORS 16 -#define EDMA_MAX_PARAMENTRY 512 - #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ #define EDMA_CONT_PARAMS_ANY 1001 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 -#define EDMA_MAX_CC 2 - /* PaRAM slots are laid out like this */ struct edmacc_param { u32 opt; @@ -256,22 +235,22 @@ struct edma_cc { /* The edma_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + unsigned long *edma_inuse; /* The edma_unused bit for each channel is clear unless * it is not being used on this platform. It uses a bit * of SOC-specific initialization code. */ - DECLARE_BITMAP(edma_unused, EDMA_CHANS); + unsigned long *edma_unused; struct dma_interrupt_data { void (*callback)(unsigned channel, unsigned short ch_status, void *data); void *data; - } intr_data[EDMA_CHANS]; + } *intr_data; struct dma_device dma_slave; - struct edma_chan slave_chans[EDMA_CHANS]; + struct edma_chan *slave_chans; int dummy_slot; }; @@ -457,6 +436,8 @@ static int prepare_unused_channel_list(struct device *dev, void *data) { struct platform_device *pdev = to_platform_device(dev); struct edma_cc *ecc = data; + int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0); + int dma_req_max = dma_req_min + ecc->num_channels; int i, count; struct of_phandle_args dma_spec; @@ -491,11 +472,15 @@ static int prepare_unused_channel_list(struct device *dev, void *data) /* For non-OF case */ for (i = 0; i < pdev->num_resources; i++) { struct resource *res = &pdev->resource[i]; + int dma_req; - if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) { + if (!(res->flags & IORESOURCE_DMA)) + continue; + + dma_req = (int)res->start; + if (dma_req >= dma_req_min && dma_req < dma_req_max) clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), ecc->edma_unused); - } } return 0; @@ -1978,7 +1963,7 @@ static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, { int i, j; - for (i = 0; i < EDMA_CHANS; i++) { + for (i = 0; i < ecc->num_channels; i++) { struct edma_chan *echan = &echans[i]; echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); echan->ecc = ecc; @@ -2247,6 +2232,27 @@ static int edma_probe(struct platform_device *pdev) if (ret) return ret; + /* Allocate memory based on the information we got from the IP */ + ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, + sizeof(*ecc->slave_chans), GFP_KERNEL); + if (!ecc->slave_chans) + return -ENOMEM; + + ecc->intr_data = devm_kcalloc(dev, ecc->num_channels, + sizeof(*ecc->intr_data), GFP_KERNEL); + if (!ecc->intr_data) + return -ENOMEM; + + ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->edma_unused) + return -ENOMEM; + + ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->edma_inuse) + return -ENOMEM; + ecc->default_queue = info->default_queue; for (i = 0; i < ecc->num_slots; i++) From 547c6e27113b7d0d03db6df0d60f91b8eb232793 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:55 +0300 Subject: [PATCH 41/77] dmaengine: edma: Use devm_kcalloc when possible When allocating a memory for number of items it is better (looks better) to use devm_kcalloc. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d5a76c67f83f..95c10373168d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -2055,7 +2055,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, * priority. So Q0 is the highest priority queue and the last queue has * the lowest priority. */ - queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8), + queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), GFP_KERNEL); if (!queue_priority_map) return -ENOMEM; @@ -2086,7 +2086,7 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, u32 shift, offset, mux; int ret, i; - xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); + xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); if (!xbar_chans) return -ENOMEM; From 907f74a0b46890da59c4f2caf7e17a89695e8132 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:56 +0300 Subject: [PATCH 42/77] dmaengine: edma: Cleanup regarding the use of dev around the code Be consistent and do not mix the use of dev, &pdev->dev, etc in the functions. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 61 +++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 95c10373168d..a9fe5c92451d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1198,27 +1198,27 @@ static void edma_execute(struct edma_chan *echan) j = i + edesc->processed; edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; - dev_vdbg(echan->vchan.chan.device->dev, - "\n pset[%d]:\n" - " chnum\t%d\n" - " slot\t%d\n" - " opt\t%08x\n" - " src\t%08x\n" - " dst\t%08x\n" - " abcnt\t%08x\n" - " ccnt\t%08x\n" - " bidx\t%08x\n" - " cidx\t%08x\n" - " lkrld\t%08x\n", - j, echan->ch_num, echan->slot[i], - edesc->pset[j].param.opt, - edesc->pset[j].param.src, - edesc->pset[j].param.dst, - edesc->pset[j].param.a_b_cnt, - edesc->pset[j].param.ccnt, - edesc->pset[j].param.src_dst_bidx, - edesc->pset[j].param.src_dst_cidx, - edesc->pset[j].param.link_bcntrld); + dev_vdbg(dev, + "\n pset[%d]:\n" + " chnum\t%d\n" + " slot\t%d\n" + " opt\t%08x\n" + " src\t%08x\n" + " dst\t%08x\n" + " abcnt\t%08x\n" + " ccnt\t%08x\n" + " bidx\t%08x\n" + " cidx\t%08x\n" + " lkrld\t%08x\n", + j, echan->ch_num, echan->slot[i], + edesc->pset[j].param.opt, + edesc->pset[j].param.src, + edesc->pset[j].param.dst, + edesc->pset[j].param.a_b_cnt, + edesc->pset[j].param.ccnt, + edesc->pset[j].param.src_dst_bidx, + edesc->pset[j].param.src_dst_cidx, + edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) edma_link(ecc, echan->slot[i], echan->slot[i + 1]); @@ -1849,7 +1849,6 @@ err_no_chan: static void edma_free_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - struct device *dev = chan->device->dev; int i; /* Terminate transfers */ @@ -1871,7 +1870,7 @@ static void edma_free_chan_resources(struct dma_chan *chan) echan->alloced = false; } - dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); + dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num); } /* Send pending descriptor to hardware */ @@ -2196,13 +2195,13 @@ static int edma_probe(struct platform_device *pdev) return ret; } - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) return ret; - ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); if (!ecc) { - dev_err(&pdev->dev, "Can't allocate controller\n"); + dev_err(dev, "Can't allocate controller\n"); return -ENOMEM; } @@ -2345,7 +2344,7 @@ static int edma_probe(struct platform_device *pdev) ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); if (ecc->dummy_slot < 0) { - dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); + dev_err(dev, "Can't allocate PaRAM dummy slot\n"); return ecc->dummy_slot; } @@ -2354,7 +2353,7 @@ static int edma_probe(struct platform_device *pdev) dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); - edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); + edma_dma_init(ecc, &ecc->dma_slave, dev); edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); @@ -2366,7 +2365,7 @@ static int edma_probe(struct platform_device *pdev) of_dma_controller_register(node, of_dma_xlate_by_chan_id, &ecc->dma_slave); - dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); + dev_info(dev, "TI EDMA DMA engine driver\n"); return 0; @@ -2380,8 +2379,8 @@ static int edma_remove(struct platform_device *pdev) struct device *dev = &pdev->dev; struct edma_cc *ecc = dev_get_drvdata(dev); - if (pdev->dev.of_node) - of_dma_controller_free(pdev->dev.of_node); + if (dev->of_node) + of_dma_controller_free(dev->of_node); dma_async_device_unregister(&ecc->dma_slave); edma_free_slot(ecc, ecc->dummy_slot); From 3287fb4d23fc906edcd5fa8c1632f30946e9c779 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:57 +0300 Subject: [PATCH 43/77] dmaengine: edma: Use dev_dbg instead pr_debug We have access to dev, so it is better to use the dev_dbg for debug prints. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index a9fe5c92451d..08f9bd0aa0b3 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -676,23 +676,23 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) /* EDMA channels without event association */ if (test_bit(channel, ecc->edma_unused)) { - pr_debug("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); return 0; } /* EDMA channel with event association */ - pr_debug("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ER, j)); + dev_dbg(ecc->dev, "ER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ER, j)); /* Clear any pending event or error */ edma_write_array(ecc, EDMA_ECR, j, mask); edma_write_array(ecc, EDMA_EMCR, j, mask); /* Clear any SER */ edma_shadow0_write_array(ecc, SH_SECR, j, mask); edma_shadow0_write_array(ecc, SH_EESR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); return 0; } @@ -730,8 +730,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) /* clear possibly pending completion interrupt */ edma_shadow0_write_array(ecc, SH_ICR, j, mask); - pr_debug("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); /* REVISIT: consider guarding against inappropriate event * chaining by overwriting with dummy_paramset. @@ -800,8 +800,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); - pr_debug("EDMA: ESR%d %08x\n", (channel >> 5), - edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); + dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), + edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); return 0; } @@ -831,8 +831,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - pr_debug("EDMA: EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); edma_shadow0_write_array(ecc, SH_ECR, j, mask); /* Clear the corresponding EMR bits */ edma_write_array(ecc, EDMA_EMCR, j, mask); From 96f5ff0e108a497372d86a286e6c264b39c09370 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:58 +0300 Subject: [PATCH 44/77] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio edma_write_slot() is for writing an entire paRAM slot. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 08f9bd0aa0b3..f6653da0ee16 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -968,8 +968,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) edma_setup_interrupt(ecc, channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset, - PARM_SIZE); + edma_write_slot(ecc, channel, &dummy_paramset); clear_bit(channel, ecc->edma_inuse); } From fc014095da23575297288bb3ab215db7c50af381 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:42:59 +0300 Subject: [PATCH 45/77] dmaengine: edma: Print warning when linking slots from different eDMA Warning message in case of linking between paRAM slots in different eDMA controllers. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index f6653da0ee16..d33ae0b43925 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -619,6 +619,9 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) */ static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) { + if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to))) + dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); + from = EDMA_CHAN_SLOT(from); to = EDMA_CHAN_SLOT(to); if (from >= ecc->num_slots || to >= ecc->num_slots) From 11c157337a3fb0a8bed5272b3a43f2bf482032ee Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:00 +0300 Subject: [PATCH 46/77] dmaengine: edma: Consolidate the comments for functions Remove or rewrite the comments for the internal functions. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 86 ++++++---------------------------------------- 1 file changed, 11 insertions(+), 75 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d33ae0b43925..6bcbdceb3dc2 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -508,19 +508,7 @@ static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, } /* - * paRAM management functions - */ - -/** - * edma_write_slot - write parameter RAM data for slot - * @ecc: pointer to edma_cc struct - * @slot: number of parameter RAM slot being modified - * @param: data to be written into parameter RAM slot - * - * Use this to assign all parameters of a transfer at once. This - * allows more efficient setup of transfers than issuing multiple - * calls to set up those parameters in small pieces, and provides - * complete control over all transfer options. + * paRAM slot management functions */ static void edma_write_slot(struct edma_cc *ecc, unsigned slot, const struct edmacc_param *param) @@ -531,15 +519,6 @@ static void edma_write_slot(struct edma_cc *ecc, unsigned slot, memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); } -/** - * edma_read_slot - read parameter RAM data from slot - * @ecc: pointer to edma_cc struct - * @slot: number of parameter RAM slot being copied - * @param: where to store copy of parameter RAM data - * - * Use this to read data from a parameter RAM slot, perhaps to - * save them as a template for later reuse. - */ static void edma_read_slot(struct edma_cc *ecc, unsigned slot, struct edmacc_param *param) { @@ -590,15 +569,6 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) return EDMA_CTLR_CHAN(ecc->id, slot); } -/** - * edma_free_slot - deallocate DMA parameter RAM - * @ecc: pointer to edma_cc struct - * @slot: parameter RAM slot returned from edma_alloc_slot() - * - * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). - * Callers are responsible for ensuring the slot is inactive, and will - * not be activated. - */ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) { slot = EDMA_CHAN_SLOT(slot); @@ -707,10 +677,9 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) * @ecc: pointer to edma_cc struct * @channel: channel being deactivated * - * When @lch is a channel, any active transfer is paused and - * all pending hardware events are cleared. The current transfer - * may not be resumed, and the channel's Parameter RAM should be - * reinitialized before being reused. + * Any active transfer is paused and all pending hardware events are cleared. + * The current transfer may not be resumed, and the channel's Parameter RAM + * should be reinitialized before being reused. */ static void edma_stop(struct edma_cc *ecc, unsigned channel) { @@ -742,13 +711,9 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel) } } -/** - * edma_pause - pause dma on a channel - * @ecc: pointer to edma_cc struct - * @channel: on which edma_start() has been called - * - * This temporarily disables EDMA hardware events on the specified channel, - * preventing them from triggering new transfers on its behalf +/* + * Temporarily disable EDMA hardware events on the specified channel, + * preventing them from triggering new transfers */ static void edma_pause(struct edma_cc *ecc, unsigned channel) { @@ -766,13 +731,7 @@ static void edma_pause(struct edma_cc *ecc, unsigned channel) } } -/** - * edma_resume - resumes dma on a paused channel - * @ecc: pointer to edma_cc struct - * @channel: on which edma_pause() has been called - * - * This re-enables EDMA hardware events on the specified channel. - */ +/* Re-enable EDMA hardware events on the specified channel. */ static void edma_resume(struct edma_cc *ecc, unsigned channel) { if (ecc->id != EDMA_CTLR(channel)) { @@ -808,19 +767,6 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) return 0; } -/****************************************************************************** - * - * It cleans ParamEntry qand bring back EDMA to initial state if media has - * been removed before EDMA has finished.It is usedful for removable media. - * Arguments: - * ch_no - channel no - * - * Return: zero on success, or corresponding error no on failure - * - * FIXME this should not be needed ... edma_stop() should suffice. - * - *****************************************************************************/ - static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) { if (ecc->id != EDMA_CTLR(channel)) { @@ -975,14 +921,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) clear_bit(channel, ecc->edma_inuse); } -/* - * edma_assign_channel_eventq - move given channel to desired eventq - * Arguments: - * channel - channel number - * eventq_no - queue to move the channel - * - * Can be used to move a channel to a selected event queue. - */ +/* Move channel to a specific event queue */ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, enum dma_event_q eventq_no) { @@ -1005,6 +944,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, edma_map_dmach_to_queue(ecc, channel, eventq_no); } +/* eDMA interrupt handler */ static irqreturn_t dma_irq_handler(int irq, void *data) { struct edma_cc *ecc = data; @@ -1056,11 +996,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) return IRQ_HANDLED; } -/****************************************************************************** - * - * DMA error interrupt handler - * - *****************************************************************************/ +/* eDMA error interrupt handler */ static irqreturn_t dma_ccerr_handler(int irq, void *data) { struct edma_cc *ecc = data; From 79ad2e383d01d03188d9e51e2058545203288bc4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:01 +0300 Subject: [PATCH 47/77] dmaengine: edma: Simplify the interrupt handling With the merger of the arch/arm/common/edma.c code into the dmaengine driver, there is no longer need to have per channel callback/data storage for interrupt events. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 454 +++++++++++++++++++++------------------------ 1 file changed, 207 insertions(+), 247 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 6bcbdceb3dc2..daa94a4bbe11 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -154,12 +154,6 @@ struct edmacc_param { #define TCCHEN BIT(22) #define ITCCHEN BIT(23) -/*ch_status parameter of callback function possible values*/ -#define EDMA_DMA_COMPLETE 1 -#define EDMA_DMA_CC_ERROR 2 -#define EDMA_DMA_TC1_ERROR 3 -#define EDMA_DMA_TC2_ERROR 4 - struct edma_pset { u32 len; dma_addr_t addr; @@ -243,12 +237,6 @@ struct edma_cc { */ unsigned long *edma_unused; - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } *intr_data; - struct dma_device dma_slave; struct edma_chan *slave_chans; int dummy_slot; @@ -486,24 +474,18 @@ static int prepare_unused_channel_list(struct device *dev, void *data) return 0; } -static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data) +static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable) { lch = EDMA_CHAN_SLOT(lch); - if (!callback) - edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); - - ecc->intr_data[lch].callback = callback; - ecc->intr_data[lch].data = data; - - if (callback) { + if (enable) { edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, BIT(lch & 0x1f)); edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, BIT(lch & 0x1f)); + } else { + edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); } } @@ -795,8 +777,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) * edma_alloc_channel - allocate DMA channel and paired parameter RAM * @ecc: pointer to edma_cc struct * @channel: specific channel to allocate; negative for "any unmapped channel" - * @callback: optional; to be issued on DMA completion or errors - * @data: passed to callback * @eventq_no: an EVENTQ_* constant, used to choose which Transfer * Controller (TC) executes requests using this channel. Use * EVENTQ_DEFAULT unless you really need a high priority queue. @@ -823,9 +803,7 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) * Returns the number of the channel, else negative errno. */ static int edma_alloc_channel(struct edma_cc *ecc, int channel, - void (*callback)(unsigned channel, u16 ch_status, void *data), - void *data, - enum dma_event_q eventq_no) + enum dma_event_q eventq_no) { unsigned done = 0; int ret = 0; @@ -881,9 +859,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); edma_write_slot(ecc, channel, &dummy_paramset); - if (callback) - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), - callback, data); + edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); edma_map_dmach_to_queue(ecc, channel, eventq_no); @@ -914,7 +890,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) if (channel >= ecc->num_channels) return; - edma_setup_interrupt(ecc, channel, NULL, NULL); + edma_setup_interrupt(ecc, channel, false); /* REVISIT should probably take out of shadow region 0 */ edma_write_slot(ecc, channel, &dummy_paramset); @@ -944,148 +920,6 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, edma_map_dmach_to_queue(ecc, channel, eventq_no); } -/* eDMA interrupt handler */ -static irqreturn_t dma_irq_handler(int irq, void *data) -{ - struct edma_cc *ecc = data; - int ctlr; - u32 sh_ier; - u32 sh_ipr; - u32 bank; - - ctlr = ecc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(ecc->dev, "dma_irq_handler\n"); - - sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); - if (!sh_ipr) { - sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); - if (!sh_ipr) - return IRQ_NONE; - sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); - bank = 1; - } else { - sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); - bank = 0; - } - - do { - u32 slot; - u32 channel; - - dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr); - - slot = __ffs(sh_ipr); - sh_ipr &= ~(BIT(slot)); - - if (sh_ier & BIT(slot)) { - channel = (bank << 5) | slot; - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); - if (ecc->intr_data[channel].callback) - ecc->intr_data[channel].callback( - EDMA_CTLR_CHAN(ctlr, channel), - EDMA_DMA_COMPLETE, - ecc->intr_data[channel].data); - } - } while (sh_ipr); - - edma_shadow0_write(ecc, SH_IEVAL, 1); - return IRQ_HANDLED; -} - -/* eDMA error interrupt handler */ -static irqreturn_t dma_ccerr_handler(int irq, void *data) -{ - struct edma_cc *ecc = data; - int i; - int ctlr; - unsigned int cnt = 0; - - ctlr = ecc->id; - if (ctlr < 0) - return IRQ_NONE; - - dev_dbg(ecc->dev, "dma_ccerr_handler\n"); - - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) - return IRQ_NONE; - - while (1) { - int j = -1; - - if (edma_read_array(ecc, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ecc, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - - if (edma_read_array(ecc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, - j, BIT(i)); - if (ecc->intr_data[k].callback) { - ecc->intr_data[k].callback( - EDMA_CTLR_CHAN(ctlr, k), - EDMA_DMA_CC_ERROR, - ecc->intr_data[k].data); - } - } - } - } else if (edma_read(ecc, EDMA_QEMR)) { - dev_dbg(ecc->dev, "QEMR %02x\n", - edma_read(ecc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ecc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ecc, EDMA_CCERR)) { - dev_dbg(ecc->dev, "CCERR %08x\n", - edma_read(ecc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(ecc, EDMA_EEVAL, 1); - return IRQ_HANDLED; -} - static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -1667,83 +1501,216 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } -static void edma_callback(unsigned ch_num, u16 ch_status, void *data) +static void edma_completion_handler(struct edma_chan *echan) { - struct edma_chan *echan = data; struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; - struct edma_desc *edesc; - struct edmacc_param p; + struct edma_desc *edesc = echan->edesc; - edesc = echan->edesc; + if (!edesc) + return; spin_lock(&echan->vchan.lock); - switch (ch_status) { - case EDMA_DMA_COMPLETE: - if (edesc) { - if (edesc->cyclic) { - vchan_cyclic_callback(&edesc->vdesc); - goto out; - } else if (edesc->processed == edesc->pset_nr) { - dev_dbg(dev, - "Transfer completed on channel %d\n", - ch_num); - edesc->residue = 0; - edma_stop(ecc, echan->ch_num); - vchan_cookie_complete(&edesc->vdesc); - echan->edesc = NULL; - } else { - dev_dbg(dev, - "Sub transfer completed on channel %d\n", - ch_num); + if (edesc->cyclic) { + vchan_cyclic_callback(&edesc->vdesc); + spin_unlock(&echan->vchan.lock); + return; + } else if (edesc->processed == edesc->pset_nr) { + edesc->residue = 0; + edma_stop(ecc, echan->ch_num); + vchan_cookie_complete(&edesc->vdesc); + echan->edesc = NULL; - edma_pause(ecc, echan->ch_num); + dev_dbg(dev, "Transfer completed on channel %d\n", + echan->ch_num); + } else { + dev_dbg(dev, "Sub transfer completed on channel %d\n", + echan->ch_num); - /* Update statistics for tx_status */ - edesc->residue -= edesc->sg_len; - edesc->residue_stat = edesc->residue; - edesc->processed_stat = edesc->processed; - } - edma_execute(echan); - } - break; - case EDMA_DMA_CC_ERROR: - edma_read_slot(ecc, echan->slot[0], &p); + edma_pause(ecc, echan->ch_num); - /* - * Issue later based on missed flag which will be sure - * to happen as: - * (1) we finished transmitting an intermediate slot and - * edma_execute is coming up. - * (2) or we finished current transfer and issue will - * call edma_execute. - * - * Important note: issuing can be dangerous here and - * lead to some nasty recursion when we are in a NULL - * slot. So we avoid doing so and set the missed flag. - */ - if (p.a_b_cnt == 0 && p.ccnt == 0) { - dev_dbg(dev, "Error on null slot, setting miss\n"); - echan->missed = 1; - } else { - /* - * The slot is already programmed but the event got - * missed, so its safe to issue it here. - */ - dev_dbg(dev, "Missed event, TRIGGERING\n"); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); - } - break; - default: - break; + /* Update statistics for tx_status */ + edesc->residue -= edesc->sg_len; + edesc->residue_stat = edesc->residue; + edesc->processed_stat = edesc->processed; } -out: + edma_execute(echan); + spin_unlock(&echan->vchan.lock); } +/* eDMA interrupt handler */ +static irqreturn_t dma_irq_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int ctlr; + u32 sh_ier; + u32 sh_ipr; + u32 bank; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_vdbg(ecc->dev, "dma_irq_handler\n"); + + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); + if (!sh_ipr) { + sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); + if (!sh_ipr) + return IRQ_NONE; + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); + bank = 1; + } else { + sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); + bank = 0; + } + + do { + u32 slot; + u32 channel; + + slot = __ffs(sh_ipr); + sh_ipr &= ~(BIT(slot)); + + if (sh_ier & BIT(slot)) { + channel = (bank << 5) | slot; + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); + edma_completion_handler(&ecc->slave_chans[channel]); + } + } while (sh_ipr); + + edma_shadow0_write(ecc, SH_IEVAL, 1); + return IRQ_HANDLED; +} + +static void edma_error_handler(struct edma_chan *echan) +{ + struct edma_cc *ecc = echan->ecc; + struct device *dev = echan->vchan.chan.device->dev; + struct edmacc_param p; + + if (!echan->edesc) + return; + + spin_lock(&echan->vchan.lock); + + edma_read_slot(ecc, echan->slot[0], &p); + /* + * Issue later based on missed flag which will be sure + * to happen as: + * (1) we finished transmitting an intermediate slot and + * edma_execute is coming up. + * (2) or we finished current transfer and issue will + * call edma_execute. + * + * Important note: issuing can be dangerous here and + * lead to some nasty recursion when we are in a NULL + * slot. So we avoid doing so and set the missed flag. + */ + if (p.a_b_cnt == 0 && p.ccnt == 0) { + dev_dbg(dev, "Error on null slot, setting miss\n"); + echan->missed = 1; + } else { + /* + * The slot is already programmed but the event got + * missed, so its safe to issue it here. + */ + dev_dbg(dev, "Missed event, TRIGGERING\n"); + edma_clean_channel(ecc, echan->ch_num); + edma_stop(ecc, echan->ch_num); + edma_start(ecc, echan->ch_num); + edma_trigger_channel(ecc, echan->ch_num); + } + spin_unlock(&echan->vchan.lock); +} + +/* eDMA error interrupt handler */ +static irqreturn_t dma_ccerr_handler(int irq, void *data) +{ + struct edma_cc *ecc = data; + int i; + int ctlr; + unsigned int cnt = 0; + + ctlr = ecc->id; + if (ctlr < 0) + return IRQ_NONE; + + dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); + + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + return IRQ_NONE; + + while (1) { + int j = -1; + + if (edma_read_array(ecc, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ecc, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + dev_dbg(ecc->dev, "EMR%d %08x\n", j, + edma_read_array(ecc, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + + if (edma_read_array(ecc, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, + j, BIT(i)); + edma_error_handler(&ecc->slave_chans[k]); + } + } + } else if (edma_read(ecc, EDMA_QEMR)) { + dev_dbg(ecc->dev, "QEMR %02x\n", + edma_read(ecc, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ecc, SH_QSECR, + BIT(i)); + + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ecc, EDMA_CCERR)) { + dev_dbg(ecc->dev, "CCERR %08x\n", + edma_read(ecc, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ecc, EDMA_CCERRCLR, BIT(i)); + + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && + (edma_read_array(ecc, EDMA_EMR, 1) == 0) && + (edma_read(ecc, EDMA_QEMR) == 0) && + (edma_read(ecc, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ecc, EDMA_EEVAL, 1); + return IRQ_HANDLED; +} + /* Alloc channel resources */ static int edma_alloc_chan_resources(struct dma_chan *chan) { @@ -1753,8 +1720,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) int a_ch_num; LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, - edma_callback, echan, EVENTQ_DEFAULT); + a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); if (a_ch_num < 0) { ret = -ENODEV; @@ -2175,11 +2141,6 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->intr_data = devm_kcalloc(dev, ecc->num_channels, - sizeof(*ecc->intr_data), GFP_KERNEL); - if (!ecc->intr_data) - return -ENOMEM; - ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), sizeof(unsigned long), GFP_KERNEL); if (!ecc->edma_unused) @@ -2350,8 +2311,7 @@ static int edma_pm_resume(struct device *dev) BIT(i & 0x1f)); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), - ecc->intr_data[i].callback, - ecc->intr_data[i].data); + true); } } From 7c3b8b3d2608bb4b1a97749c607440785b60ef7f Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:02 +0300 Subject: [PATCH 48/77] dmaengine: edma: Move the pending error check into helper function In the ccerr interrupt handler the code checks for pending errors in the error status registers in two different places. Move the check out to a helper function. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index daa94a4bbe11..84b98a01993a 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1626,6 +1626,16 @@ static void edma_error_handler(struct edma_chan *echan) spin_unlock(&echan->vchan.lock); } +static inline bool edma_error_pending(struct edma_cc *ecc) +{ + if (edma_read_array(ecc, EDMA_EMR, 0) || + edma_read_array(ecc, EDMA_EMR, 1) || + edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) + return true; + + return false; +} + /* eDMA error interrupt handler */ static irqreturn_t dma_ccerr_handler(int irq, void *data) { @@ -1640,10 +1650,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) + if (!edma_error_pending(ecc)) return IRQ_NONE; while (1) { @@ -1698,10 +1705,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) } } } - if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) && - (edma_read_array(ecc, EDMA_EMR, 1) == 0) && - (edma_read(ecc, EDMA_QEMR) == 0) && - (edma_read(ecc, EDMA_CCERR) == 0)) + if (!edma_error_pending(ecc)) break; cnt++; if (cnt > 10) From e4402a129faca71ddd160d89ef7750da0ce2d6c4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:03 +0300 Subject: [PATCH 49/77] dmaengine: edma: Simplify and optimize ccerr interrupt handler No need to run through the bits in QEMR and CCERR events since they will not trigger any action, so just clearing the errors there is fine. In case of the missed event the loop can be optimized so we spend less time to handle the event. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 80 ++++++++++++++++++++-------------------------- 1 file changed, 34 insertions(+), 46 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 84b98a01993a..d105d1ae0f13 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1640,9 +1640,10 @@ static inline bool edma_error_pending(struct edma_cc *ecc) static irqreturn_t dma_ccerr_handler(int irq, void *data) { struct edma_cc *ecc = data; - int i; + int i, j; int ctlr; unsigned int cnt = 0; + unsigned int val; ctlr = ecc->id; if (ctlr < 0) @@ -1654,57 +1655,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_NONE; while (1) { - int j = -1; + /* Event missed register(s) */ + for (j = 0; j < 2; j++) { + unsigned long emr; - if (edma_read_array(ecc, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ecc, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { + val = edma_read_array(ecc, EDMA_EMR, j); + if (!val) + continue; + + dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); + emr = val; + for (i = find_next_bit(&emr, 32, 0); i < 32; + i = find_next_bit(&emr, 32, i + 1)) { int k = (j << 5) + i; - if (edma_read_array(ecc, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, - j, BIT(i)); - edma_error_handler(&ecc->slave_chans[k]); - } - } - } else if (edma_read(ecc, EDMA_QEMR)) { - dev_dbg(ecc->dev, "QEMR %02x\n", - edma_read(ecc, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ecc, SH_QSECR, - BIT(i)); - - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ecc, EDMA_CCERR)) { - dev_dbg(ecc->dev, "CCERR %08x\n", - edma_read(ecc, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ecc, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ecc, EDMA_CCERRCLR, BIT(i)); - - /* NOTE: not reported!! */ - } + edma_error_handler(&ecc->slave_chans[k]); } } + + val = edma_read(ecc, EDMA_QEMR); + if (val) { + dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_QEMCR, val); + edma_shadow0_write(ecc, SH_QSECR, val); + } + + val = edma_read(ecc, EDMA_CCERR); + if (val) { + dev_warn(ecc->dev, "CCERR 0x%08x\n", val); + /* Not reported, just clear the interrupt reason. */ + edma_write(ecc, EDMA_CCERRCLR, val); + } + if (!edma_error_pending(ecc)) break; cnt++; From 4ab54f696dc5299d7db9d924f28f408dc0404f1b Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:04 +0300 Subject: [PATCH 50/77] dmaengine: edma: Read channel mapping support only once from HW Instead of directly reading it from CCCFG register take the information out once when we set up the configuration from the HW. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d105d1ae0f13..4b2ccc9de0ad 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -223,6 +223,7 @@ struct edma_cc { unsigned num_region; unsigned num_slots; unsigned num_tc; + bool chmap_exist; enum dma_event_q default_queue; bool unused_chan_list_done; @@ -1930,11 +1931,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, value = GET_NUM_EVQUE(cccfg); ecc->num_tc = value + 1; + ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; + dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); dev_dbg(dev, "num_region: %u\n", ecc->num_region); dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); + dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); /* Nothing need to be done if queue priority is provided */ if (pdata->queue_priority_mapping) @@ -2223,7 +2227,7 @@ static int edma_probe(struct platform_device *pdev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic exist */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_region; i++) { @@ -2293,7 +2297,7 @@ static int edma_pm_resume(struct device *dev) queue_priority_mapping[i][1]); /* Map the channel to param entry if channel mapping logic */ - if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST) + if (ecc->chmap_exist) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_channels; i++) { From 7a73b135cdb33f78acab118dd72782416d5281b2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:05 +0300 Subject: [PATCH 51/77] dmaengine: edma: Rename bitfields for slot and channel usage tracking The names chosen for the bitfields were quite confusing and given no real information on what they are used for... edma_inuse -> slot_inuse: tracks the slot usage/availability edma_unused -> channel_unused: tracks the channel usage/availability Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 51 +++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 4b2ccc9de0ad..8d9169b7f208 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -227,16 +227,16 @@ struct edma_cc { enum dma_event_q default_queue; bool unused_chan_list_done; - /* The edma_inuse bit for each PaRAM slot is clear unless the + /* The slot_inuse bit for each PaRAM slot is clear unless the * channel is in use ... by ARM or DSP, for QDMA, or whatever. */ - unsigned long *edma_inuse; + unsigned long *slot_inuse; - /* The edma_unused bit for each channel is clear unless + /* The channel_unused bit for each channel is clear unless * it is not being used on this platform. It uses a bit * of SOC-specific initialization code. */ - unsigned long *edma_unused; + unsigned long *channel_unused; struct dma_device dma_slave; struct edma_chan *slave_chans; @@ -452,7 +452,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) continue; clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - ecc->edma_unused); + ecc->channel_unused); of_node_put(dma_spec.np); } return 0; @@ -469,7 +469,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data) dma_req = (int)res->start; if (dma_req >= dma_req_min && dma_req < dma_req_max) clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - ecc->edma_unused); + ecc->channel_unused); } return 0; @@ -533,17 +533,17 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) if (slot < 0) { slot = ecc->num_channels; for (;;) { - slot = find_next_zero_bit(ecc->edma_inuse, + slot = find_next_zero_bit(ecc->slot_inuse, ecc->num_slots, slot); if (slot == ecc->num_slots) return -ENOMEM; - if (!test_and_set_bit(slot, ecc->edma_inuse)) + if (!test_and_set_bit(slot, ecc->slot_inuse)) break; } } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { return -EINVAL; - } else if (test_and_set_bit(slot, ecc->edma_inuse)) { + } else if (test_and_set_bit(slot, ecc->slot_inuse)) { return -EBUSY; } @@ -559,7 +559,7 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot) return; edma_write_slot(ecc, slot, &dummy_paramset); - clear_bit(slot, ecc->edma_inuse); + clear_bit(slot, ecc->slot_inuse); } /** @@ -631,7 +631,7 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) unsigned int mask = BIT(channel & 0x1f); /* EDMA channels without event association */ - if (test_bit(channel, ecc->edma_unused)) { + if (test_bit(channel, ecc->channel_unused)) { dev_dbg(ecc->dev, "ESR%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ESR, j)); edma_shadow0_write_array(ecc, SH_ESR, j, mask); @@ -835,11 +835,11 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, if (channel < 0) { channel = 0; for (;;) { - channel = find_next_bit(ecc->edma_unused, + channel = find_next_bit(ecc->channel_unused, ecc->num_channels, channel); if (channel == ecc->num_channels) break; - if (!test_and_set_bit(channel, ecc->edma_inuse)) { + if (!test_and_set_bit(channel, ecc->slot_inuse)) { done = 1; break; } @@ -849,7 +849,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, return -ENOMEM; } else if (channel >= ecc->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, ecc->edma_inuse)) { + } else if (test_and_set_bit(channel, ecc->slot_inuse)) { return -EBUSY; } @@ -895,7 +895,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) /* REVISIT should probably take out of shadow region 0 */ edma_write_slot(ecc, channel, &dummy_paramset); - clear_bit(channel, ecc->edma_inuse); + clear_bit(channel, ecc->slot_inuse); } /* Move channel to a specific event queue */ @@ -2137,14 +2137,15 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels), - sizeof(unsigned long), GFP_KERNEL); - if (!ecc->edma_unused) + ecc->channel_unused = devm_kcalloc(dev, + BITS_TO_LONGS(ecc->num_channels), + sizeof(unsigned long), GFP_KERNEL); + if (!ecc->channel_unused) return -ENOMEM; - ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), + ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), sizeof(unsigned long), GFP_KERNEL); - if (!ecc->edma_inuse) + if (!ecc->slot_inuse) return -ENOMEM; ecc->default_queue = info->default_queue; @@ -2153,7 +2154,7 @@ static int edma_probe(struct platform_device *pdev) edma_write_slot(ecc, i, &dummy_paramset); /* Mark all channels as unused */ - memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused)); + memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused)); if (info->rsv) { /* Clear the reserved channels in unused list */ @@ -2162,7 +2163,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; rsv_chans[i][0] != -1; i++) { off = rsv_chans[i][0]; ln = rsv_chans[i][1]; - clear_bits(off, ln, ecc->edma_unused); + clear_bits(off, ln, ecc->channel_unused); } } @@ -2172,7 +2173,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; rsv_slots[i][0] != -1; i++) { off = rsv_slots[i][0]; ln = rsv_slots[i][1]; - set_bits(off, ln, ecc->edma_inuse); + set_bits(off, ln, ecc->slot_inuse); } } } @@ -2182,7 +2183,7 @@ static int edma_probe(struct platform_device *pdev) if (xbar_chans) { for (i = 0; xbar_chans[i][1] != -1; i++) { off = xbar_chans[i][1]; - clear_bits(off, 1, ecc->edma_unused); + clear_bits(off, 1, ecc->channel_unused); } } @@ -2301,7 +2302,7 @@ static int edma_pm_resume(struct device *dev) edma_direct_dmach_to_param_mapping(ecc); for (i = 0; i < ecc->num_channels; i++) { - if (test_bit(i, ecc->edma_inuse)) { + if (test_bit(i, ecc->slot_inuse)) { /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); From e4e886c6b1e2a1ef9654d26dad1c3baca8139b3c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Wed, 14 Oct 2015 14:43:06 +0300 Subject: [PATCH 52/77] dmaengine: edma: Dynamic paRAM slot handling if HW supports it If the eDMA3 has support for channel paRAM slot mapping we can utilize it to allocate slots on demand and save precious slots for real transfers. On am335x the eDMA has 64 channels which means we can unlock 64 paRAM slots out from the available 256. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 101 +++++++++++++++++++++++---------------------- 1 file changed, 52 insertions(+), 49 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 8d9169b7f208..7eefbf1e1c94 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -413,12 +413,13 @@ static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } -static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc) +static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot) { - int i; - - for (i = 0; i < ecc->num_channels; i++) - edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5)); + if (ecc->chmap_exist) { + channel = EDMA_CHAN_SLOT(channel); + slot = EDMA_CHAN_SLOT(slot); + edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); + } } static int prepare_unused_channel_list(struct device *dev, void *data) @@ -528,10 +529,18 @@ static void edma_read_slot(struct edma_cc *ecc, unsigned slot, */ static int edma_alloc_slot(struct edma_cc *ecc, int slot) { - if (slot > 0) + if (slot > 0) { slot = EDMA_CHAN_SLOT(slot); + /* Requesting entry paRAM slot for a HW triggered channel. */ + if (ecc->chmap_exist && slot < ecc->num_channels) + slot = EDMA_SLOT_ANY; + } + if (slot < 0) { - slot = ecc->num_channels; + if (ecc->chmap_exist) + slot = 0; + else + slot = ecc->num_channels; for (;;) { slot = find_next_zero_bit(ecc->slot_inuse, ecc->num_slots, @@ -541,7 +550,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) if (!test_and_set_bit(slot, ecc->slot_inuse)) break; } - } else if (slot < ecc->num_channels || slot >= ecc->num_slots) { + } else if (slot >= ecc->num_slots) { return -EINVAL; } else if (test_and_set_bit(slot, ecc->slot_inuse)) { return -EBUSY; @@ -555,7 +564,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot) static void edma_free_slot(struct edma_cc *ecc, unsigned slot) { slot = EDMA_CHAN_SLOT(slot); - if (slot < ecc->num_channels || slot >= ecc->num_slots) + if (slot >= ecc->num_slots) return; edma_write_slot(ecc, slot, &dummy_paramset); @@ -806,7 +815,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) static int edma_alloc_channel(struct edma_cc *ecc, int channel, enum dma_event_q eventq_no) { - unsigned done = 0; int ret = 0; if (!ecc->unused_chan_list_done) { @@ -833,24 +841,12 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, } if (channel < 0) { - channel = 0; - for (;;) { - channel = find_next_bit(ecc->channel_unused, - ecc->num_channels, channel); - if (channel == ecc->num_channels) - break; - if (!test_and_set_bit(channel, ecc->slot_inuse)) { - done = 1; - break; - } - channel++; - } - if (!done) - return -ENOMEM; + channel = find_next_bit(ecc->channel_unused, ecc->num_channels, + 0); + if (channel == ecc->num_channels) + return -EBUSY; } else if (channel >= ecc->num_channels) { return -EINVAL; - } else if (test_and_set_bit(channel, ecc->slot_inuse)) { - return -EBUSY; } /* ensure access through shadow region 0 */ @@ -858,7 +854,6 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, /* ensure no events are pending */ edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); - edma_write_slot(ecc, channel, &dummy_paramset); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); @@ -891,11 +886,8 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) if (channel >= ecc->num_channels) return; - edma_setup_interrupt(ecc, channel, false); /* REVISIT should probably take out of shadow region 0 */ - - edma_write_slot(ecc, channel, &dummy_paramset); - clear_bit(channel, ecc->slot_inuse); + edma_setup_interrupt(ecc, channel, false); } /* Move channel to a specific event queue */ @@ -1729,7 +1721,15 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) } echan->alloced = true; - echan->slot[0] = echan->ch_num; + echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); + if (echan->slot[0] < 0) { + dev_err(dev, "Entry slot allocation failed for channel %u\n", + EDMA_CHAN_SLOT(echan->ch_num)); + goto err_wrong_chan; + } + + /* Set up channel -> slot mapping for the entry slot */ + edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]); dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); @@ -1754,13 +1754,16 @@ static void edma_free_chan_resources(struct dma_chan *chan) vchan_free_chan_resources(&echan->vchan); /* Free EDMA PaRAM slots */ - for (i = 1; i < EDMA_MAX_SLOTS; i++) { + for (i = 0; i < EDMA_MAX_SLOTS; i++) { if (echan->slot[i] >= 0) { edma_free_slot(echan->ecc, echan->slot[i]); echan->slot[i] = -1; } } + /* Set entry slot to the dummy slot */ + edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot); + /* Free EDMA channel */ if (echan->alloced) { edma_free_channel(echan->ecc, echan->ch_num); @@ -2217,8 +2220,18 @@ static int edma_probe(struct platform_device *pdev) } } - for (i = 0; i < ecc->num_channels; i++) + ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); + if (ecc->dummy_slot < 0) { + dev_err(dev, "Can't allocate PaRAM dummy slot\n"); + return ecc->dummy_slot; + } + + for (i = 0; i < ecc->num_channels; i++) { + /* Assign all channels to the default queue */ edma_map_dmach_to_queue(ecc, i, info->default_queue); + /* Set entry slot to the dummy slot */ + edma_set_chmap(ecc, i, ecc->dummy_slot); + } queue_priority_mapping = info->queue_priority_mapping; @@ -2227,10 +2240,6 @@ static int edma_probe(struct platform_device *pdev) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic exist */ - if (ecc->chmap_exist) - edma_direct_dmach_to_param_mapping(ecc); - for (i = 0; i < ecc->num_region; i++) { edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); @@ -2238,12 +2247,6 @@ static int edma_probe(struct platform_device *pdev) } ecc->info = info; - ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); - if (ecc->dummy_slot < 0) { - dev_err(dev, "Can't allocate PaRAM dummy slot\n"); - return ecc->dummy_slot; - } - dma_cap_zero(ecc->dma_slave.cap_mask); dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); @@ -2287,6 +2290,7 @@ static int edma_remove(struct platform_device *pdev) static int edma_pm_resume(struct device *dev) { struct edma_cc *ecc = dev_get_drvdata(dev); + struct edma_chan *echan = ecc->slave_chans; int i; s8 (*queue_priority_mapping)[2]; @@ -2297,18 +2301,17 @@ static int edma_pm_resume(struct device *dev) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic */ - if (ecc->chmap_exist) - edma_direct_dmach_to_param_mapping(ecc); - for (i = 0; i < ecc->num_channels; i++) { - if (test_bit(i, ecc->slot_inuse)) { + if (echan[i].alloced) { /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), true); + + /* Set up channel -> slot mapping for the entry slot */ + edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]); } } From e6d5bf6a8f23d0557ac685b7e81ce148f3a7744c Mon Sep 17 00:00:00 2001 From: Rameshwar Prasad Sahu Date: Wed, 14 Oct 2015 19:25:07 +0530 Subject: [PATCH 53/77] dmaengine: xgene-dma: Remove memcpy offload support due to performance drop The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other computations. But the bandwidth of the entire DMA engine is shared among all channels. This patch re-configures operations availability such that one can achieve maximum performance for XOR and PQ computation by removing the memory offload operations. Signed-off-by: Rameshwar Prasad Sahu Signed-off-by: Vinod Koul --- drivers/dma/xgene-dma.c | 59 +---------------------------------------- 1 file changed, 1 insertion(+), 58 deletions(-) diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c index dc84ed1f7541..ecc9e9025688 100644 --- a/drivers/dma/xgene-dma.c +++ b/drivers/dma/xgene-dma.c @@ -907,60 +907,6 @@ static void xgene_dma_free_chan_resources(struct dma_chan *dchan) chan->desc_pool = NULL; } -static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy( - struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src, - size_t len, unsigned long flags) -{ - struct xgene_dma_desc_sw *first = NULL, *new; - struct xgene_dma_chan *chan; - size_t copy; - - if (unlikely(!dchan || !len)) - return NULL; - - chan = to_dma_chan(dchan); - - do { - /* Allocate the link descriptor from DMA pool */ - new = xgene_dma_alloc_descriptor(chan); - if (!new) - goto fail; - - /* Create the largest transaction possible */ - copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT); - - /* Prepare DMA descriptor */ - xgene_dma_prep_cpy_desc(chan, new, dst, src, copy); - - if (!first) - first = new; - - new->tx.cookie = 0; - async_tx_ack(&new->tx); - - /* Update metadata */ - len -= copy; - dst += copy; - src += copy; - - /* Insert the link descriptor to the LD ring */ - list_add_tail(&new->node, &first->tx_list); - } while (len); - - new->tx.flags = flags; /* client is in control of this ack */ - new->tx.cookie = -EBUSY; - list_splice(&first->tx_list, &new->tx_list); - - return &new->tx; - -fail: - if (!first) - return NULL; - - xgene_dma_free_desc_list(chan, &first->tx_list); - return NULL; -} - static struct dma_async_tx_descriptor *xgene_dma_prep_sg( struct dma_chan *dchan, struct scatterlist *dst_sg, u32 dst_nents, struct scatterlist *src_sg, @@ -1717,7 +1663,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan, dma_cap_zero(dma_dev->cap_mask); /* Set DMA device capability */ - dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); dma_cap_set(DMA_SG, dma_dev->cap_mask); /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR @@ -1744,7 +1689,6 @@ static void xgene_dma_set_caps(struct xgene_dma_chan *chan, dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources; dma_dev->device_issue_pending = xgene_dma_issue_pending; dma_dev->device_tx_status = xgene_dma_tx_status; - dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy; dma_dev->device_prep_dma_sg = xgene_dma_prep_sg; if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { @@ -1797,8 +1741,7 @@ static int xgene_dma_async_register(struct xgene_dma *pdma, int id) /* DMA capability info */ dev_info(pdma->dev, - "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan), - dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "", + "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan), dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "", dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "", dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : ""); From 52984aab3369869d43efdf15743cc23795413f68 Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Sun, 18 Oct 2015 23:31:10 +0800 Subject: [PATCH 54/77] dmaengine: ste_dma40: fix a trivial typo s/regsiter/register/ Signed-off-by: Geliang Tang Acked-by: Linus Walleij Signed-off-by: Vinod Koul --- drivers/dma/ste_dma40.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 750d1b313684..dd3e7ba273ad 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -2907,7 +2907,7 @@ static int __init d40_dmaengine_init(struct d40_base *base, if (err) { d40_err(base->dev, - "Failed to regsiter memcpy only channels\n"); + "Failed to register memcpy only channels\n"); goto failure2; } From 21a31846a7736a88709fe6fe2e73857d884de89c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:17:59 +0300 Subject: [PATCH 55/77] dmaengine: edma: Remove alignment constraint for memcpy Despite the claim by the original commit adding the memcpy support, eDMA does not have constraint on the alignment of src, dst or length in increment mode. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 7eefbf1e1c94..b36dfa5458cb 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1324,6 +1324,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( struct edma_desc *edesc; struct device *dev = chan->device->dev; struct edma_chan *echan = to_edma_chan(chan); + unsigned int width; if (unlikely(!echan || !len)) return NULL; @@ -1336,8 +1337,12 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( edesc->pset_nr = 1; + width = 1 << __ffs((src | dest | len)); + if (width > DMA_SLAVE_BUSWIDTH_64_BYTES) + width = DMA_SLAVE_BUSWIDTH_64_BYTES; + ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, - DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM); + width, len, DMA_MEM_TO_MEM); if (ret < 0) return NULL; @@ -1903,12 +1908,6 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, dma->dev = dev; - /* - * code using dma memcpy must make sure alignment of - * length is at dma->copy_align boundary. - */ - dma->copy_align = DMAENGINE_ALIGN_4_BYTES; - INIT_LIST_HEAD(&dma->channels); } From df6694f80365a72700d4c68fcf61ef068f5b3c25 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:00 +0300 Subject: [PATCH 56/77] dmaengine: edma: Optimize memcpy operation If the transfer is shorted then 64K we can complete it with one ACNT burst by configuring ACNT to the length of the copy, this require one paRAM slot. Otherwise we use two paRAM slots for the copy: slot1: will copy (length / 32767) number of 32767 byte long blocks slot2: will be configured to copy the remaining data. According to tests this patch increases the throughput of memcpy from ~3MB/s to 15MB/s Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 96 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 75 insertions(+), 21 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index b36dfa5458cb..c0165e3d3396 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1107,19 +1107,16 @@ static int edma_dma_resume(struct dma_chan *chan) */ static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset, dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, - enum dma_slave_buswidth dev_width, - unsigned int dma_length, + unsigned int acnt, unsigned int dma_length, enum dma_transfer_direction direction) { struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; struct edmacc_param *param = &epset->param; - int acnt, bcnt, ccnt, cidx; + int bcnt, ccnt, cidx; int src_bidx, dst_bidx, src_cidx, dst_cidx; int absync; - acnt = dev_width; - /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ if (!burst) burst = 1; @@ -1320,41 +1317,98 @@ static struct dma_async_tx_descriptor *edma_prep_dma_memcpy( struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long tx_flags) { - int ret; + int ret, nslots; struct edma_desc *edesc; struct device *dev = chan->device->dev; struct edma_chan *echan = to_edma_chan(chan); - unsigned int width; + unsigned int width, pset_len; if (unlikely(!echan || !len)) return NULL; - edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC); + if (len < SZ_64K) { + /* + * Transfer size less than 64K can be handled with one paRAM + * slot and with one burst. + * ACNT = length + */ + width = len; + pset_len = len; + nslots = 1; + } else { + /* + * Transfer size bigger than 64K will be handled with maximum of + * two paRAM slots. + * slot1: (full_length / 32767) times 32767 bytes bursts. + * ACNT = 32767, length1: (full_length / 32767) * 32767 + * slot2: the remaining amount of data after slot1. + * ACNT = full_length - length1, length2 = ACNT + * + * When the full_length is multibple of 32767 one slot can be + * used to complete the transfer. + */ + width = SZ_32K - 1; + pset_len = rounddown(len, width); + /* One slot is enough for lengths multiple of (SZ_32K -1) */ + if (unlikely(pset_len == len)) + nslots = 1; + else + nslots = 2; + } + + edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), + GFP_ATOMIC); if (!edesc) { dev_dbg(dev, "Failed to allocate a descriptor\n"); return NULL; } - edesc->pset_nr = 1; - - width = 1 << __ffs((src | dest | len)); - if (width > DMA_SLAVE_BUSWIDTH_64_BYTES) - width = DMA_SLAVE_BUSWIDTH_64_BYTES; + edesc->pset_nr = nslots; + edesc->residue = edesc->residue_stat = len; + edesc->direction = DMA_MEM_TO_MEM; + edesc->echan = echan; ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, - width, len, DMA_MEM_TO_MEM); - if (ret < 0) + width, pset_len, DMA_MEM_TO_MEM); + if (ret < 0) { + kfree(edesc); return NULL; + } edesc->absync = ret; - /* - * Enable intermediate transfer chaining to re-trigger channel - * on completion of every TR, and enable transfer-completion - * interrupt on completion of the whole transfer. - */ edesc->pset[0].param.opt |= ITCCHEN; - edesc->pset[0].param.opt |= TCINTEN; + if (nslots == 1) { + /* Enable transfer complete interrupt */ + edesc->pset[0].param.opt |= TCINTEN; + } else { + /* Enable transfer complete chaining for the first slot */ + edesc->pset[0].param.opt |= TCCHEN; + + if (echan->slot[1] < 0) { + echan->slot[1] = edma_alloc_slot(echan->ecc, + EDMA_SLOT_ANY); + if (echan->slot[1] < 0) { + kfree(edesc); + dev_err(dev, "%s: Failed to allocate slot\n", + __func__); + return NULL; + } + } + dest += pset_len; + src += pset_len; + pset_len = width = len % (SZ_32K - 1); + + ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, + width, pset_len, DMA_MEM_TO_MEM); + if (ret < 0) { + kfree(edesc); + return NULL; + } + + edesc->pset[1].param.opt |= ITCCHEN; + edesc->pset[1].param.opt |= TCINTEN; + } return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } From 34cf30111cfccd18e1ccf2456f72dff6d42bd853 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:01 +0300 Subject: [PATCH 57/77] dmaengine: edma: Simplify function parameter list for channel operations Instead of passing a pointer to struct edma_cc and the channel number, pass only the pointer to the edma_chan structure for the given channel. This struct contains all the information needed by the functions and the use of this makes it obvious that most of the sanity checks can be removed from the driver. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 396 ++++++++++++++------------------------------- 1 file changed, 123 insertions(+), 273 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index c0165e3d3396..a64befecf477 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -391,17 +391,19 @@ static inline void clear_bits(int offset, int len, unsigned long *p) clear_bit(offset + (len - 1), p); } -static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no, +static void edma_map_dmach_to_queue(struct edma_chan *echan, enum dma_event_q queue_no) { - int bit = (ch_no & 0x7) * 4; + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int bit = (channel & 0x7) * 4; /* default to low priority queue */ if (queue_no == EVENTQ_DEFAULT) queue_no = ecc->default_queue; queue_no &= 7; - edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit), + edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), queue_no << bit); } @@ -413,10 +415,12 @@ static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); } -static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot) +static void edma_set_chmap(struct edma_chan *echan, int slot) { + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + if (ecc->chmap_exist) { - channel = EDMA_CHAN_SLOT(channel); slot = EDMA_CHAN_SLOT(slot); edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); } @@ -476,18 +480,19 @@ static int prepare_unused_channel_list(struct device *dev, void *data) return 0; } -static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable) +static void edma_setup_interrupt(struct edma_chan *echan, bool enable) { - lch = EDMA_CHAN_SLOT(lch); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); if (enable) { - edma_shadow0_write_array(ecc, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ecc, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, + BIT(channel & 0x1f)); + edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, + BIT(channel & 0x1f)); } else { - edma_shadow0_write_array(ecc, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, + BIT(channel & 0x1f)); } } @@ -613,40 +618,25 @@ static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, return edma_read(ecc, offs); } -/*-----------------------------------------------------------------------*/ -/** - * edma_start - start dma on a channel - * @ecc: pointer to edma_cc struct - * @channel: channel being activated - * +/* * Channels with event associations will be triggered by their hardware * events, and channels without such associations will be triggered by * software. (At this writing there is no interface for using software * triggers except with channels that don't support hardware triggers.) - * - * Returns zero on success, else negative errno. */ -static int edma_start(struct edma_cc *ecc, unsigned channel) +static void edma_start(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel < ecc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); + if (test_bit(channel, ecc->channel_unused)) { /* EDMA channels without event association */ - if (test_bit(channel, ecc->channel_unused)) { - dev_dbg(ecc->dev, "ESR%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_ESR, j)); - edma_shadow0_write_array(ecc, SH_ESR, j, mask); - return 0; - } - + dev_dbg(ecc->dev, "ESR%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_ESR, j)); + edma_shadow0_write_array(ecc, SH_ESR, j, mask); + } else { /* EDMA channel with event association */ dev_dbg(ecc->dev, "ER%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ER, j)); @@ -658,164 +648,86 @@ static int edma_start(struct edma_cc *ecc, unsigned channel) edma_shadow0_write_array(ecc, SH_EESR, j, mask); dev_dbg(ecc->dev, "EER%d %08x\n", j, edma_shadow0_read_array(ecc, SH_EER, j)); - return 0; } - - return -EINVAL; } -/** - * edma_stop - stops dma on the channel passed - * @ecc: pointer to edma_cc struct - * @channel: channel being deactivated - * - * Any active transfer is paused and all pending hardware events are cleared. - * The current transfer may not be resumed, and the channel's Parameter RAM - * should be reinitialized before being reused. - */ -static void edma_stop(struct edma_cc *ecc, unsigned channel) +static void edma_stop(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - if (channel < ecc->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + edma_shadow0_write_array(ecc, SH_EECR, j, mask); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write_array(ecc, EDMA_EMCR, j, mask); - edma_shadow0_write_array(ecc, SH_EECR, j, mask); - edma_shadow0_write_array(ecc, SH_ECR, j, mask); - edma_shadow0_write_array(ecc, SH_SECR, j, mask); - edma_write_array(ecc, EDMA_EMCR, j, mask); + /* clear possibly pending completion interrupt */ + edma_shadow0_write_array(ecc, SH_ICR, j, mask); - /* clear possibly pending completion interrupt */ - edma_shadow0_write_array(ecc, SH_ICR, j, mask); + dev_dbg(ecc->dev, "EER%d %08x\n", j, + edma_shadow0_read_array(ecc, SH_EER, j)); - dev_dbg(ecc->dev, "EER%d %08x\n", j, - edma_shadow0_read_array(ecc, SH_EER, j)); - - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ } /* * Temporarily disable EDMA hardware events on the specified channel, * preventing them from triggering new transfers */ -static void edma_pause(struct edma_cc *ecc, unsigned channel) +static void edma_pause(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); - if (channel < ecc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask); - } + edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); } /* Re-enable EDMA hardware events on the specified channel. */ -static void edma_resume(struct edma_cc *ecc, unsigned channel) +static void edma_resume(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); - if (channel < ecc->num_channels) { - unsigned int mask = BIT(channel & 0x1f); - - edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask); - } + edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); } -static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel) +static void edma_trigger_channel(struct edma_chan *echan) { - unsigned int mask; - - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - mask = BIT(channel & 0x1f); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + unsigned int mask = BIT(channel & 0x1f); edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); - return 0; } -static void edma_clean_channel(struct edma_cc *ecc, unsigned channel) +static void edma_clean_channel(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - if (channel < ecc->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); - - dev_dbg(ecc->dev, "EMR%d %08x\n", j, - edma_read_array(ecc, EDMA_EMR, j)); - edma_shadow0_write_array(ecc, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(ecc, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ecc, SH_SECR, j, mask); - edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } + dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); + edma_shadow0_write_array(ecc, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ecc, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ecc, SH_SECR, j, mask); + edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } -/** - * edma_alloc_channel - allocate DMA channel and paired parameter RAM - * @ecc: pointer to edma_cc struct - * @channel: specific channel to allocate; negative for "any unmapped channel" - * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. - * - * This allocates a DMA channel and its associated parameter RAM slot. - * The parameter RAM is initialized to hold a dummy transfer. - * - * Normal use is to pass a specific channel number as @channel, to make - * use of hardware events mapped to that channel. When the channel will - * be used only for software triggering or event chaining, channels not - * mapped to hardware events (or mapped to unused events) are preferable. - * - * DMA transfers start from a channel using edma_start(), or by - * chaining. When the transfer described in that channel's parameter RAM - * slot completes, that slot's data may be reloaded through a link. - * - * DMA errors are only reported to the @callback associated with the - * channel driving that transfer, but transfer completion callbacks can - * be sent to another channel under control of the TCC field in - * the option word of the transfer's parameter RAM set. Drivers must not - * use DMA transfer completion callbacks for channels they did not allocate. - * (The same applies to TCC codes used in transfer chaining.) - * - * Returns the number of the channel, else negative errno. - */ -static int edma_alloc_channel(struct edma_cc *ecc, int channel, +static int edma_alloc_channel(struct edma_chan *echan, enum dma_event_q eventq_no) { - int ret = 0; + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); if (!ecc->unused_chan_list_done) { /* @@ -823,86 +735,40 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel, * used and clear them in the unused list, making the rest * available for ARM usage. */ - ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, - prepare_unused_channel_list); + int ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, + prepare_unused_channel_list); if (ret < 0) return ret; ecc->unused_chan_list_done = true; } - if (channel >= 0) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", - __func__, ecc->id, EDMA_CTLR(channel)); - return -EINVAL; - } - channel = EDMA_CHAN_SLOT(channel); - } - - if (channel < 0) { - channel = find_next_bit(ecc->channel_unused, ecc->num_channels, - 0); - if (channel == ecc->num_channels) - return -EBUSY; - } else if (channel >= ecc->num_channels) { - return -EINVAL; - } - /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); /* ensure no events are pending */ - edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel)); + edma_stop(echan); - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true); + edma_setup_interrupt(echan, true); - edma_map_dmach_to_queue(ecc, channel, eventq_no); + edma_map_dmach_to_queue(echan, eventq_no); - return EDMA_CTLR_CHAN(ecc->id, channel); + return 0; } -/** - * edma_free_channel - deallocate DMA channel - * @ecc: pointer to edma_cc struct - * @channel: dma channel returned from edma_alloc_channel() - * - * This deallocates the DMA channel and associated parameter RAM slot - * allocated by edma_alloc_channel(). - * - * Callers are responsible for ensuring the channel is inactive, and - * will not be reactivated by linking, chaining, or software calls to - * edma_start(). - */ -static void edma_free_channel(struct edma_cc *ecc, unsigned channel) +static void edma_free_channel(struct edma_chan *echan) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= ecc->num_channels) - return; - + /* ensure no events are pending */ + edma_stop(echan); /* REVISIT should probably take out of shadow region 0 */ - edma_setup_interrupt(ecc, channel, false); + edma_setup_interrupt(echan, false); } /* Move channel to a specific event queue */ -static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, +static void edma_assign_channel_eventq(struct edma_chan *echan, enum dma_event_q eventq_no) { - if (ecc->id != EDMA_CTLR(channel)) { - dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__, - ecc->id, EDMA_CTLR(channel)); - return; - } - channel = EDMA_CHAN_SLOT(channel); - - if (channel >= ecc->num_channels) - return; + struct edma_cc *ecc = echan->ecc; /* default to low priority queue */ if (eventq_no == EVENTQ_DEFAULT) @@ -910,7 +776,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel, if (eventq_no >= ecc->num_tc) return; - edma_map_dmach_to_queue(ecc, channel, eventq_no); + edma_map_dmach_to_queue(echan, eventq_no); } static inline struct edma_cc *to_edma_cc(struct dma_device *d) @@ -1011,19 +877,19 @@ static void edma_execute(struct edma_chan *echan) * transfers of MAX_NR_SG */ dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); + edma_clean_channel(echan); + edma_stop(echan); + edma_start(echan); + edma_trigger_channel(echan); echan->missed = 0; } else if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); - edma_start(ecc, echan->ch_num); + edma_start(echan); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); - edma_resume(ecc, echan->ch_num); + edma_resume(echan); } } @@ -1041,11 +907,10 @@ static int edma_terminate_all(struct dma_chan *chan) * echan->edesc is NULL and exit.) */ if (echan->edesc) { - edma_stop(echan->ecc, echan->ch_num); + edma_stop(echan); /* Move the cyclic channel back to default queue */ if (echan->edesc->cyclic) - edma_assign_channel_eventq(echan->ecc, echan->ch_num, - EVENTQ_DEFAULT); + edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); /* * free the running request descriptor * since it is not in any of the vdesc lists @@ -1082,7 +947,7 @@ static int edma_dma_pause(struct dma_chan *chan) if (!echan->edesc) return -EINVAL; - edma_pause(echan->ecc, echan->ch_num); + edma_pause(echan); return 0; } @@ -1090,7 +955,7 @@ static int edma_dma_resume(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - edma_resume(echan->ecc, echan->ch_num); + edma_resume(echan); return 0; } @@ -1548,14 +1413,13 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0); + edma_assign_channel_eventq(echan, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } static void edma_completion_handler(struct edma_chan *echan) { - struct edma_cc *ecc = echan->ecc; struct device *dev = echan->vchan.chan.device->dev; struct edma_desc *edesc = echan->edesc; @@ -1569,7 +1433,7 @@ static void edma_completion_handler(struct edma_chan *echan) return; } else if (edesc->processed == edesc->pset_nr) { edesc->residue = 0; - edma_stop(ecc, echan->ch_num); + edma_stop(echan); vchan_cookie_complete(&edesc->vdesc); echan->edesc = NULL; @@ -1579,7 +1443,7 @@ static void edma_completion_handler(struct edma_chan *echan) dev_dbg(dev, "Sub transfer completed on channel %d\n", echan->ch_num); - edma_pause(ecc, echan->ch_num); + edma_pause(echan); /* Update statistics for tx_status */ edesc->residue -= edesc->sg_len; @@ -1670,10 +1534,10 @@ static void edma_error_handler(struct edma_chan *echan) * missed, so its safe to issue it here. */ dev_dbg(dev, "Missed event, TRIGGERING\n"); - edma_clean_channel(ecc, echan->ch_num); - edma_stop(ecc, echan->ch_num); - edma_start(ecc, echan->ch_num); - edma_trigger_channel(ecc, echan->ch_num); + edma_clean_channel(echan); + edma_stop(echan); + edma_start(echan); + edma_trigger_channel(echan); } spin_unlock(&echan->vchan.lock); } @@ -1761,43 +1625,29 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) struct edma_chan *echan = to_edma_chan(chan); struct device *dev = chan->device->dev; int ret; - int a_ch_num; - LIST_HEAD(descs); - a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT); + ret = edma_alloc_channel(echan, EVENTQ_DEFAULT); + if (ret) + return ret; - if (a_ch_num < 0) { - ret = -ENODEV; - goto err_no_chan; - } - - if (a_ch_num != echan->ch_num) { - dev_err(dev, "failed to allocate requested channel %u:%u\n", - EDMA_CTLR(echan->ch_num), - EDMA_CHAN_SLOT(echan->ch_num)); - ret = -ENODEV; - goto err_wrong_chan; - } - - echan->alloced = true; echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); if (echan->slot[0] < 0) { dev_err(dev, "Entry slot allocation failed for channel %u\n", EDMA_CHAN_SLOT(echan->ch_num)); - goto err_wrong_chan; + goto err_slot; } /* Set up channel -> slot mapping for the entry slot */ - edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]); + edma_set_chmap(echan, echan->slot[0]); + echan->alloced = true; dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); return 0; -err_wrong_chan: - edma_free_channel(echan->ecc, a_ch_num); -err_no_chan: +err_slot: + edma_free_channel(echan); return ret; } @@ -1808,7 +1658,7 @@ static void edma_free_chan_resources(struct dma_chan *chan) int i; /* Terminate transfers */ - edma_stop(echan->ecc, echan->ch_num); + edma_stop(echan); vchan_free_chan_resources(&echan->vchan); @@ -1821,11 +1671,11 @@ static void edma_free_chan_resources(struct dma_chan *chan) } /* Set entry slot to the dummy slot */ - edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot); + edma_set_chmap(echan, echan->ecc->dummy_slot); /* Free EDMA channel */ if (echan->alloced) { - edma_free_channel(echan->ecc, echan->ch_num); + edma_free_channel(echan); echan->alloced = false; } @@ -2279,13 +2129,6 @@ static int edma_probe(struct platform_device *pdev) return ecc->dummy_slot; } - for (i = 0; i < ecc->num_channels; i++) { - /* Assign all channels to the default queue */ - edma_map_dmach_to_queue(ecc, i, info->default_queue); - /* Set entry slot to the dummy slot */ - edma_set_chmap(ecc, i, ecc->dummy_slot); - } - queue_priority_mapping = info->queue_priority_mapping; /* Event queue priority mapping */ @@ -2309,6 +2152,14 @@ static int edma_probe(struct platform_device *pdev) edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); + for (i = 0; i < ecc->num_channels; i++) { + /* Assign all channels to the default queue */ + edma_map_dmach_to_queue(&ecc->slave_chans[i], + info->default_queue); + /* Set entry slot to the dummy slot */ + edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); + } + ret = dma_async_device_register(&ecc->dma_slave); if (ret) goto err_reg1; @@ -2360,11 +2211,10 @@ static int edma_pm_resume(struct device *dev) edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f)); - edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i), - true); + edma_setup_interrupt(&echan[i], true); /* Set up channel -> slot mapping for the entry slot */ - edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]); + edma_set_chmap(&echan[i], echan[i].slot[0]); } } From d9c345d18a8df5a5427cca80d2b9d981468ef270 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:02 +0300 Subject: [PATCH 58/77] dmaengine: edma: Correct PaRAM access function names (_parm_ to _param_) These inline functions are designed to modify parts of the PaRAM in eDMA. Change the names accordingly. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index a64befecf477..051a7c4593d4 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -349,32 +349,32 @@ static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); } -static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset, - int param_no) +static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, + int param_no) { return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); } -static inline void edma_parm_write(struct edma_cc *ecc, int offset, - int param_no, unsigned val) +static inline void edma_param_write(struct edma_cc *ecc, int offset, + int param_no, unsigned val) { edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); } -static inline void edma_parm_modify(struct edma_cc *ecc, int offset, - int param_no, unsigned and, unsigned or) +static inline void edma_param_modify(struct edma_cc *ecc, int offset, + int param_no, unsigned and, unsigned or) { edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); } -static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no, - unsigned and) +static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, + unsigned and) { edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); } -static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no, - unsigned or) +static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, + unsigned or) { edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); } @@ -594,8 +594,8 @@ static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) if (from >= ecc->num_slots || to >= ecc->num_slots) return; - edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } /** From f9425deb662ac07099ec151ffb4791eef48e9d83 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:03 +0300 Subject: [PATCH 59/77] dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue() We can merge the content of the later so we will have only one function to be used for mapping channels to given eventq Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 56 ++++++++++++++++++---------------------------- 1 file changed, 22 insertions(+), 34 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 051a7c4593d4..eaf1f9e4bde0 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -391,22 +391,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p) clear_bit(offset + (len - 1), p); } -static void edma_map_dmach_to_queue(struct edma_chan *echan, - enum dma_event_q queue_no) -{ - struct edma_cc *ecc = echan->ecc; - int channel = EDMA_CHAN_SLOT(echan->ch_num); - int bit = (channel & 0x7) * 4; - - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = ecc->default_queue; - - queue_no &= 7; - edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), - queue_no << bit); -} - static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, int priority) { @@ -723,6 +707,25 @@ static void edma_clean_channel(struct edma_chan *echan) edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); } +/* Move channel to a specific event queue */ +static void edma_assign_channel_eventq(struct edma_chan *echan, + enum dma_event_q eventq_no) +{ + struct edma_cc *ecc = echan->ecc; + int channel = EDMA_CHAN_SLOT(echan->ch_num); + int bit = (channel & 0x7) * 4; + + /* default to low priority queue */ + if (eventq_no == EVENTQ_DEFAULT) + eventq_no = ecc->default_queue; + if (eventq_no >= ecc->num_tc) + return; + + eventq_no &= 7; + edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), + eventq_no << bit); +} + static int edma_alloc_channel(struct edma_chan *echan, enum dma_event_q eventq_no) { @@ -751,7 +754,7 @@ static int edma_alloc_channel(struct edma_chan *echan, edma_setup_interrupt(echan, true); - edma_map_dmach_to_queue(echan, eventq_no); + edma_assign_channel_eventq(echan, eventq_no); return 0; } @@ -764,21 +767,6 @@ static void edma_free_channel(struct edma_chan *echan) edma_setup_interrupt(echan, false); } -/* Move channel to a specific event queue */ -static void edma_assign_channel_eventq(struct edma_chan *echan, - enum dma_event_q eventq_no) -{ - struct edma_cc *ecc = echan->ecc; - - /* default to low priority queue */ - if (eventq_no == EVENTQ_DEFAULT) - eventq_no = ecc->default_queue; - if (eventq_no >= ecc->num_tc) - return; - - edma_map_dmach_to_queue(echan, eventq_no); -} - static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); @@ -2154,8 +2142,8 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ - edma_map_dmach_to_queue(&ecc->slave_chans[i], - info->default_queue); + edma_assign_channel_eventq(&ecc->slave_chans[i], + info->default_queue); /* Set entry slot to the dummy slot */ edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); } From 633e42b8c5465acf03671be7bd2866c486816596 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:04 +0300 Subject: [PATCH 60/77] dmaengine: edma: Get qDMA channel information from HW also Query the number of qDMA channels from CCCFG register. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index eaf1f9e4bde0..ea851ab05c8e 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -107,6 +107,7 @@ /* CCCFG register */ #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */ +#define GET_NUM_QDMACH(x) (x & 0x70 >> 4) /* bits 4-6 */ #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */ #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */ #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ @@ -220,6 +221,7 @@ struct edma_cc { /* eDMA3 resource information */ unsigned num_channels; + unsigned num_qchannels; unsigned num_region; unsigned num_slots; unsigned num_tc; @@ -1819,6 +1821,9 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, value = GET_NUM_DMACH(cccfg); ecc->num_channels = BIT(value + 1); + value = GET_NUM_QDMACH(cccfg); + ecc->num_qchannels = value * 2; + value = GET_NUM_PAENTRY(cccfg); ecc->num_slots = BIT(value + 4); @@ -1830,6 +1835,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg); dev_dbg(dev, "num_region: %u\n", ecc->num_region); dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); + dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); From 02f77ef1197bd0acde8c0b7ed2b4dee7da7bcbf6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:05 +0300 Subject: [PATCH 61/77] dmaengine: edma: Refactor the dma device and channel struct initialization Move all code under one function to do the dma device and eDMA channel related setup so they are not scattered around the driver. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 87 ++++++++++++++++++++++------------------------ 1 file changed, 41 insertions(+), 46 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index ea851ab05c8e..e1b0e6864f27 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1756,53 +1756,54 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } -static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma, - struct edma_chan *echans) -{ - int i, j; - - for (i = 0; i < ecc->num_channels; i++) { - struct edma_chan *echan = &echans[i]; - echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); - echan->ecc = ecc; - echan->vchan.desc_free = edma_desc_free; - - vchan_init(&echan->vchan, dma); - - INIT_LIST_HEAD(&echan->node); - for (j = 0; j < EDMA_MAX_SLOTS; j++) - echan->slot[j] = -1; - } -} - #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) -static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, - struct device *dev) +static void edma_dma_init(struct edma_cc *ecc) { - dma->device_prep_slave_sg = edma_prep_slave_sg; - dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; - dma->device_prep_dma_memcpy = edma_prep_dma_memcpy; - dma->device_alloc_chan_resources = edma_alloc_chan_resources; - dma->device_free_chan_resources = edma_free_chan_resources; - dma->device_issue_pending = edma_issue_pending; - dma->device_tx_status = edma_tx_status; - dma->device_config = edma_slave_config; - dma->device_pause = edma_dma_pause; - dma->device_resume = edma_dma_resume; - dma->device_terminate_all = edma_terminate_all; + struct dma_device *ddev = &ecc->dma_slave; + int i, j; - dma->src_addr_widths = EDMA_DMA_BUSWIDTHS; - dma->dst_addr_widths = EDMA_DMA_BUSWIDTHS; - dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); - dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + dma_cap_zero(ddev->cap_mask); + dma_cap_set(DMA_SLAVE, ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, ddev->cap_mask); + dma_cap_set(DMA_MEMCPY, ddev->cap_mask); - dma->dev = dev; + ddev->device_prep_slave_sg = edma_prep_slave_sg; + ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; + ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + ddev->device_free_chan_resources = edma_free_chan_resources; + ddev->device_issue_pending = edma_issue_pending; + ddev->device_tx_status = edma_tx_status; + ddev->device_config = edma_slave_config; + ddev->device_pause = edma_dma_pause; + ddev->device_resume = edma_dma_resume; + ddev->device_terminate_all = edma_terminate_all; - INIT_LIST_HEAD(&dma->channels); + ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + ddev->dev = ecc->dev; + + INIT_LIST_HEAD(&ddev->channels); + + for (i = 0; i < ecc->num_channels; i++) { + struct edma_chan *echan = &ecc->slave_chans[i]; + echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); + echan->ecc = ecc; + echan->vchan.desc_free = edma_desc_free; + + vchan_init(&echan->vchan, ddev); + + INIT_LIST_HEAD(&echan->node); + for (j = 0; j < EDMA_MAX_SLOTS; j++) + echan->slot[j] = -1; + } } static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, @@ -2137,14 +2138,8 @@ static int edma_probe(struct platform_device *pdev) } ecc->info = info; - dma_cap_zero(ecc->dma_slave.cap_mask); - dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); - dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); - dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask); - - edma_dma_init(ecc, &ecc->dma_slave, dev); - - edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); + /* Init the dma device and channels */ + edma_dma_init(ecc); for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ From 56c7b749965947af45efaf8a7021a1f86d4ce4d8 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:06 +0300 Subject: [PATCH 62/77] dmaengine: edma: Do not allocate memory for edma_rsv_info in case of DT boot The channel/slot reservation is not supported when booted with DT so there is not need to allocate memory. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index e1b0e6864f27..c1b8bb09c221 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1926,12 +1926,6 @@ static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) int ret = 0; struct property *prop; size_t sz; - struct edma_rsv_info *rsv_info; - - rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); - if (!rsv_info) - return -ENOMEM; - pdata->rsv = rsv_info; prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); if (prop) From 966a87b5962ed0d058e93809ae310fa542a69c8e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:07 +0300 Subject: [PATCH 63/77] dmaengine: edma: Merge the of parsing functions Instead of nesting functions just merge them since the resulting function is still small and readable. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index c1b8bb09c221..d4d71e60da1b 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -1921,31 +1921,23 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, return 0; } -static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata) -{ - int ret = 0; - struct property *prop; - size_t sz; - - prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); - if (prop) - ret = edma_xbar_event_map(dev, pdata, sz); - - return ret; -} - static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) { struct edma_soc_info *info; + struct property *prop; + size_t sz; int ret; info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); if (!info) return ERR_PTR(-ENOMEM); - ret = edma_of_parse_dt(dev, info); - if (ret) - return ERR_PTR(ret); + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (prop) { + ret = edma_xbar_event_map(dev, info, sz); + if (ret) + return ERR_PTR(ret); + } return info; } From 42dbdcc6bf965997c088caff2a8be7f9bf44f701 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:08 +0300 Subject: [PATCH 64/77] dmaengine: ti-dma-crossbar: Add support for crossbar on AM33xx/AM43xx The DMA event crossbar on AM33xx/AM43xx is different from the one found in DRA7x family. Instead of a single event crossbar it has 64 identical mux attached to each eDMA event line. When the 0 event mux is selected, the default mapped event is going to be routed to the corresponding eDMA event line. If different mux is selected, then the selected event is going to be routed to the given eDMA event. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- .../bindings/dma/ti-dma-crossbar.txt | 15 +- drivers/dma/ti-dma-crossbar.c | 251 +++++++++++++++--- 2 files changed, 234 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt index 63a48928f3a8..b152a75dceae 100644 --- a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt +++ b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt @@ -2,9 +2,10 @@ Texas Instruments DMA Crossbar (DMA request router) Required properties: - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar + "ti,am335x-edma-crossbar" for AM335x and AM437x - reg: Memory map for accessing module -- #dma-cells: Should be set to <1>. - Clients should use the crossbar request number (input) +- #dma-cells: Should be set to to match with the DMA controller's dma-cells + for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar. - dma-requests: Number of DMA requests the crossbar can receive - dma-masters: phandle pointing to the DMA controller @@ -14,6 +15,15 @@ The DMA controller node need to have the following poroperties: Optional properties: - ti,dma-safe-map: Safe routing value for unused request lines +Notes: +When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request +the DMA event number as crossbar ID (input to the DMA crossbar). + +For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients: +dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC +the event should be assigned and <1> is the mux selection for in the crossbar. +When mux 0 is used the DMA channel can be requested directly from edma node. + Example: /* DMA controller */ @@ -47,6 +57,7 @@ uart1: serial@4806a000 { ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; + /* Requesting crossbar input 49 and 50 */ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; dma-names = "tx", "rx"; }; diff --git a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c index 5cce8c9d0026..a415edbe61b1 100644 --- a/drivers/dma/ti-dma-crossbar.c +++ b/drivers/dma/ti-dma-crossbar.c @@ -17,13 +17,184 @@ #include #include -#define TI_XBAR_OUTPUTS 127 -#define TI_XBAR_INPUTS 256 +#define TI_XBAR_DRA7 0 +#define TI_XBAR_AM335X 1 + +static const struct of_device_id ti_dma_xbar_match[] = { + { + .compatible = "ti,dra7-dma-crossbar", + .data = (void *)TI_XBAR_DRA7, + }, + { + .compatible = "ti,am335x-edma-crossbar", + .data = (void *)TI_XBAR_AM335X, + }, + {}, +}; + +/* Crossbar on AM335x/AM437x family */ +#define TI_AM335X_XBAR_LINES 64 + +struct ti_am335x_xbar_data { + void __iomem *iomem; + + struct dma_router dmarouter; + + u32 xbar_events; /* maximum number of events to select in xbar */ + u32 dma_requests; /* number of DMA requests on eDMA */ +}; + +struct ti_am335x_xbar_map { + u16 dma_line; + u16 mux_val; +}; + +static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u16 val) +{ + writeb_relaxed(val & 0x1f, iomem + event); +} + +static void ti_am335x_xbar_free(struct device *dev, void *route_data) +{ + struct ti_am335x_xbar_data *xbar = dev_get_drvdata(dev); + struct ti_am335x_xbar_map *map = route_data; + + dev_dbg(dev, "Unmapping XBAR event %u on channel %u\n", + map->mux_val, map->dma_line); + + ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); + kfree(map); +} + +static void *ti_am335x_xbar_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); + struct ti_am335x_xbar_data *xbar = platform_get_drvdata(pdev); + struct ti_am335x_xbar_map *map; + + if (dma_spec->args_count != 3) + return ERR_PTR(-EINVAL); + + if (dma_spec->args[2] >= xbar->xbar_events) { + dev_err(&pdev->dev, "Invalid XBAR event number: %d\n", + dma_spec->args[2]); + return ERR_PTR(-EINVAL); + } + + if (dma_spec->args[0] >= xbar->dma_requests) { + dev_err(&pdev->dev, "Invalid DMA request line number: %d\n", + dma_spec->args[0]); + return ERR_PTR(-EINVAL); + } + + /* The of_node_put() will be done in the core for the node */ + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0); + if (!dma_spec->np) { + dev_err(&pdev->dev, "Can't get DMA master\n"); + return ERR_PTR(-EINVAL); + } + + map = kzalloc(sizeof(*map), GFP_KERNEL); + if (!map) { + of_node_put(dma_spec->np); + return ERR_PTR(-ENOMEM); + } + + map->dma_line = (u16)dma_spec->args[0]; + map->mux_val = (u16)dma_spec->args[2]; + + dma_spec->args[2] = 0; + dma_spec->args_count = 2; + + dev_dbg(&pdev->dev, "Mapping XBAR event%u to DMA%u\n", + map->mux_val, map->dma_line); + + ti_am335x_xbar_write(xbar->iomem, map->dma_line, map->mux_val); + + return map; +} + +static const struct of_device_id ti_am335x_master_match[] = { + { .compatible = "ti,edma3-tpcc", }, + {}, +}; + +static int ti_am335x_xbar_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + const struct of_device_id *match; + struct device_node *dma_node; + struct ti_am335x_xbar_data *xbar; + struct resource *res; + void __iomem *iomem; + int i, ret; + + if (!node) + return -ENODEV; + + xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL); + if (!xbar) + return -ENOMEM; + + dma_node = of_parse_phandle(node, "dma-masters", 0); + if (!dma_node) { + dev_err(&pdev->dev, "Can't get DMA master node\n"); + return -ENODEV; + } + + match = of_match_node(ti_am335x_master_match, dma_node); + if (!match) { + dev_err(&pdev->dev, "DMA master is not supported\n"); + return -EINVAL; + } + + if (of_property_read_u32(dma_node, "dma-requests", + &xbar->dma_requests)) { + dev_info(&pdev->dev, + "Missing XBAR output information, using %u.\n", + TI_AM335X_XBAR_LINES); + xbar->dma_requests = TI_AM335X_XBAR_LINES; + } + of_node_put(dma_node); + + if (of_property_read_u32(node, "dma-requests", &xbar->xbar_events)) { + dev_info(&pdev->dev, + "Missing XBAR input information, using %u.\n", + TI_AM335X_XBAR_LINES); + xbar->xbar_events = TI_AM335X_XBAR_LINES; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + iomem = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(iomem)) + return PTR_ERR(iomem); + + xbar->iomem = iomem; + + xbar->dmarouter.dev = &pdev->dev; + xbar->dmarouter.route_free = ti_am335x_xbar_free; + + platform_set_drvdata(pdev, xbar); + + /* Reset the crossbar */ + for (i = 0; i < xbar->dma_requests; i++) + ti_am335x_xbar_write(xbar->iomem, i, 0); + + ret = of_dma_router_register(node, ti_am335x_xbar_route_allocate, + &xbar->dmarouter); + + return ret; +} + +/* Crossbar on DRA7xx family */ +#define TI_DRA7_XBAR_OUTPUTS 127 +#define TI_DRA7_XBAR_INPUTS 256 #define TI_XBAR_EDMA_OFFSET 0 #define TI_XBAR_SDMA_OFFSET 1 -struct ti_dma_xbar_data { +struct ti_dra7_xbar_data { void __iomem *iomem; struct dma_router dmarouter; @@ -35,35 +206,35 @@ struct ti_dma_xbar_data { u32 dma_offset; }; -struct ti_dma_xbar_map { +struct ti_dra7_xbar_map { u16 xbar_in; int xbar_out; }; -static inline void ti_dma_xbar_write(void __iomem *iomem, int xbar, u16 val) +static inline void ti_dra7_xbar_write(void __iomem *iomem, int xbar, u16 val) { writew_relaxed(val, iomem + (xbar * 2)); } -static void ti_dma_xbar_free(struct device *dev, void *route_data) +static void ti_dra7_xbar_free(struct device *dev, void *route_data) { - struct ti_dma_xbar_data *xbar = dev_get_drvdata(dev); - struct ti_dma_xbar_map *map = route_data; + struct ti_dra7_xbar_data *xbar = dev_get_drvdata(dev); + struct ti_dra7_xbar_map *map = route_data; dev_dbg(dev, "Unmapping XBAR%u (was routed to %d)\n", map->xbar_in, map->xbar_out); - ti_dma_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val); + ti_dra7_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val); idr_remove(&xbar->map_idr, map->xbar_out); kfree(map); } -static void *ti_dma_xbar_route_allocate(struct of_phandle_args *dma_spec, - struct of_dma *ofdma) +static void *ti_dra7_xbar_route_allocate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) { struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); - struct ti_dma_xbar_data *xbar = platform_get_drvdata(pdev); - struct ti_dma_xbar_map *map; + struct ti_dra7_xbar_data *xbar = platform_get_drvdata(pdev); + struct ti_dra7_xbar_map *map; if (dma_spec->args[0] >= xbar->xbar_requests) { dev_err(&pdev->dev, "Invalid XBAR request number: %d\n", @@ -93,12 +264,12 @@ static void *ti_dma_xbar_route_allocate(struct of_phandle_args *dma_spec, dev_dbg(&pdev->dev, "Mapping XBAR%u to DMA%d\n", map->xbar_in, map->xbar_out); - ti_dma_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in); + ti_dra7_xbar_write(xbar->iomem, map->xbar_out, map->xbar_in); return map; } -static const struct of_device_id ti_dma_master_match[] = { +static const struct of_device_id ti_dra7_master_match[] = { { .compatible = "ti,omap4430-sdma", .data = (void *)TI_XBAR_SDMA_OFFSET, @@ -110,12 +281,12 @@ static const struct of_device_id ti_dma_master_match[] = { {}, }; -static int ti_dma_xbar_probe(struct platform_device *pdev) +static int ti_dra7_xbar_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; struct device_node *dma_node; - struct ti_dma_xbar_data *xbar; + struct ti_dra7_xbar_data *xbar; struct resource *res; u32 safe_val; void __iomem *iomem; @@ -136,7 +307,7 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) return -ENODEV; } - match = of_match_node(ti_dma_master_match, dma_node); + match = of_match_node(ti_dra7_master_match, dma_node); if (!match) { dev_err(&pdev->dev, "DMA master is not supported\n"); return -EINVAL; @@ -146,16 +317,16 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) &xbar->dma_requests)) { dev_info(&pdev->dev, "Missing XBAR output information, using %u.\n", - TI_XBAR_OUTPUTS); - xbar->dma_requests = TI_XBAR_OUTPUTS; + TI_DRA7_XBAR_OUTPUTS); + xbar->dma_requests = TI_DRA7_XBAR_OUTPUTS; } of_node_put(dma_node); if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) { dev_info(&pdev->dev, "Missing XBAR input information, using %u.\n", - TI_XBAR_INPUTS); - xbar->xbar_requests = TI_XBAR_INPUTS; + TI_DRA7_XBAR_INPUTS); + xbar->xbar_requests = TI_DRA7_XBAR_INPUTS; } if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val)) @@ -169,30 +340,50 @@ static int ti_dma_xbar_probe(struct platform_device *pdev) xbar->iomem = iomem; xbar->dmarouter.dev = &pdev->dev; - xbar->dmarouter.route_free = ti_dma_xbar_free; + xbar->dmarouter.route_free = ti_dra7_xbar_free; xbar->dma_offset = (u32)match->data; platform_set_drvdata(pdev, xbar); /* Reset the crossbar */ for (i = 0; i < xbar->dma_requests; i++) - ti_dma_xbar_write(xbar->iomem, i, xbar->safe_val); + ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val); - ret = of_dma_router_register(node, ti_dma_xbar_route_allocate, + ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate, &xbar->dmarouter); if (ret) { /* Restore the defaults for the crossbar */ for (i = 0; i < xbar->dma_requests; i++) - ti_dma_xbar_write(xbar->iomem, i, i); + ti_dra7_xbar_write(xbar->iomem, i, i); } return ret; } -static const struct of_device_id ti_dma_xbar_match[] = { - { .compatible = "ti,dra7-dma-crossbar" }, - {}, -}; +static int ti_dma_xbar_probe(struct platform_device *pdev) +{ + const struct of_device_id *match; + int ret; + + match = of_match_node(ti_dma_xbar_match, pdev->dev.of_node); + if (unlikely(!match)) + return -EINVAL; + + switch ((u32)match->data) { + case TI_XBAR_DRA7: + ret = ti_dra7_xbar_probe(pdev); + break; + case TI_XBAR_AM335X: + ret = ti_am335x_xbar_probe(pdev); + break; + default: + dev_err(&pdev->dev, "Unsupported crossbar\n"); + ret = -ENODEV; + break; + } + + return ret; +} static struct platform_driver ti_dma_xbar_driver = { .driver = { From f7c7cae94832fc09ccff080b4cc2358ac11e2150 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:09 +0300 Subject: [PATCH 65/77] dmaengine: Kconfig: edma: Select TI_DMA_CROSSBAR in case of ARCH_OMAP Since the crossbar is needed for eDMA when it is used on OMAP like platforms (am335x/am437x and later DRA7xx), select the crossbar to be built if ARCH_OMAP is set. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- drivers/dma/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 992efc8e465e..6a388a7c6429 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -486,6 +486,7 @@ config TI_EDMA depends on ARCH_DAVINCI || ARCH_OMAP || ARCH_KEYSTONE select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select TI_DMA_CROSSBAR if ARCH_OMAP default n help Enable support for the TI EDMA controller. This DMA From 1be5336bc7ba050ee07d352643bf4c01c513553c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:10 +0300 Subject: [PATCH 66/77] dmaengine: edma: New device tree binding With the old binding and driver architecture we had many issues: No way to assign eDMA channels to event queues, thus not able to tune the system by moving specific DMA channels to low/high priority servicing. We moved the cyclic channels to high priority within the code, but that was just a workaround to this issue. Memcopy was fundamentally broken: even if the driver scanned the DT/devices in the booted system for direct DMA users (which is not effective when the events are going through a crossbar) and created a map of 'used' channels, this information was not really usable. Since via dmaengien API the eDMA driver will be called with _some_ channel number, we would try to request this channel when any channel is requested for memcpy. By luck we got channel which is not used by any device most of the time so things worked, but if a device would have been using the given channel, but not requested it, the memcpy channel would have been waiting for HW event. The old code had the am33xx/am43xx DMA event router handling embedded. This should have been done in a separate driver since it is not part of the actual eDMA IP. There were no way to 'lock' PaRAM slots to be used by the DSP for example when booting with DT. In DT boot the edma node used more than one hwmod which is not a good practice and the kernel prints warning because of this. With the new bindings and the changes in the driver we can: - No regression with Legacy binding and non DT boot - DMA channels can be assigned to any TC (to set priority) - PaRAM slots can be reserved for other cores to use - Dynamic power management for CC and TCs, if only TC0 is used all other TC can be powered down for example Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/ti-edma.txt | 117 ++++- drivers/dma/edma.c | 482 ++++++++++++------ include/linux/platform_data/edma.h | 3 + 3 files changed, 457 insertions(+), 145 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt index 5ba525a10035..d3d0a4fb1c73 100644 --- a/Documentation/devicetree/bindings/dma/ti-edma.txt +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt @@ -1,4 +1,119 @@ -TI EDMA +Texas Instruments eDMA + +The eDMA3 consists of two components: Channel controller (CC) and Transfer +Controller(s) (TC). The CC is the main entry for DMA users since it is +responsible for the DMA channel handling, while the TCs are responsible to +execute the actual DMA tansfer. + +------------------------------------------------------------------------------ +eDMA3 Channel Controller + +Required properties: +- compatible: "ti,edma3-tpcc" for the channel controller(s) +- #dma-cells: Should be set to <2>. The first number is the DMA request + number and the second is the TC the channel is serviced on. +- reg: Memory map of eDMA CC +- reg-names: "edma3_cc" +- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. +- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint" +- ti,tptcs: List of TPTCs associated with the eDMA in the following form: + <&tptc_phandle TC_priority_number>. The highest priority is 0. + +Optional properties: +- ti,hwmods: Name of the hwmods associated to the eDMA CC +- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow + these channels will be SW triggered channels. The list must + contain 16 bits numbers, see example. +- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by + the driver, they are allocated to be used by for example the + DSP. See example. + +------------------------------------------------------------------------------ +eDMA3 Transfer Controller + +Required properties: +- compatible: "ti,edma3-tptc" for the transfer controller(s) +- reg: Memory map of eDMA TC +- interrupts: Interrupt number for TCerrint. + +Optional properties: +- ti,hwmods: Name of the hwmods associated to the given eDMA TC +- interrupt-names: "edma3_tcerrint" + +------------------------------------------------------------------------------ +Example: + +edma: edma@49000000 { + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; + interrupts = <12 13 14>; + interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; + + /* Channel 20 and 21 is allocated for memcpy */ + ti,edma-memcpy-channels = /bits/ 16 <20 21>; + /* The following PaRAM slots are reserved: 35-45 and 100-110 */ + ti,edma-reserved-slot-ranges = /bits/ 16 <35 10>, + /bits/ 16 <100 10>; +}; + +edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edm3_tcerrint"; +}; + +edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = <113>; + interrupt-names = "edm3_tcerrint"; +}; + +edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = <114>; + interrupt-names = "edm3_tcerrint"; +}; + +sham: sham@53100000 { + compatible = "ti,omap4-sham"; + ti,hwmods = "sham"; + reg = <0x53100000 0x200>; + interrupts = <109>; + /* DMA channel 36 executed on eDMA TC0 - low priority queue */ + dmas = <&edma 36 0>; + dma-names = "rx"; +}; + +mcasp0: mcasp@48038000 { + compatible = "ti,am33xx-mcasp-audio"; + ti,hwmods = "mcasp0"; + reg = <0x48038000 0x2000>, + <0x46000000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <80>, <81>; + interrupt-names = "tx", "rx"; + status = "disabled"; + /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */ + dmas = <&edma 8 2>, + <&edma 9 2>; + dma-names = "tx", "rx"; +}; + +------------------------------------------------------------------------------ +DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc +binding. Required properties: - compatible : "ti,edma3" diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d4d71e60da1b..31722d436a42 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -201,13 +201,20 @@ struct edma_desc { struct edma_cc; +struct edma_tc { + struct device_node *node; + u16 id; +}; + struct edma_chan { struct virt_dma_chan vchan; struct list_head node; struct edma_desc *edesc; struct edma_cc *ecc; + struct edma_tc *tc; int ch_num; bool alloced; + bool hw_triggered; int slot[EDMA_MAX_SLOTS]; int missed; struct dma_slave_config cfg; @@ -218,6 +225,7 @@ struct edma_cc { struct edma_soc_info *info; void __iomem *base; int id; + bool legacy_mode; /* eDMA3 resource information */ unsigned num_channels; @@ -228,20 +236,16 @@ struct edma_cc { bool chmap_exist; enum dma_event_q default_queue; - bool unused_chan_list_done; - /* The slot_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. + /* + * The slot_inuse bit for each PaRAM slot is clear unless the slot is + * in use by Linux or if it is allocated to be used by DSP. */ unsigned long *slot_inuse; - /* The channel_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - unsigned long *channel_unused; - struct dma_device dma_slave; + struct dma_device *dma_memcpy; struct edma_chan *slave_chans; + struct edma_tc *tc_list; int dummy_slot; }; @@ -251,8 +255,17 @@ static const struct edmacc_param dummy_paramset = { .ccnt = 1, }; +#define EDMA_BINDING_LEGACY 0 +#define EDMA_BINDING_TPCC 1 static const struct of_device_id edma_of_ids[] = { - { .compatible = "ti,edma3", }, + { + .compatible = "ti,edma3", + .data = (void *)EDMA_BINDING_LEGACY, + }, + { + .compatible = "ti,edma3-tpcc", + .data = (void *)EDMA_BINDING_TPCC, + }, {} }; @@ -412,60 +425,6 @@ static void edma_set_chmap(struct edma_chan *echan, int slot) } } -static int prepare_unused_channel_list(struct device *dev, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - struct edma_cc *ecc = data; - int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0); - int dma_req_max = dma_req_min + ecc->num_channels; - int i, count; - struct of_phandle_args dma_spec; - - if (dev->of_node) { - struct platform_device *dma_pdev; - - count = of_property_count_strings(dev->of_node, "dma-names"); - if (count < 0) - return 0; - for (i = 0; i < count; i++) { - if (of_parse_phandle_with_args(dev->of_node, "dmas", - "#dma-cells", i, - &dma_spec)) - continue; - - if (!of_match_node(edma_of_ids, dma_spec.np)) { - of_node_put(dma_spec.np); - continue; - } - - dma_pdev = of_find_device_by_node(dma_spec.np); - if (&dma_pdev->dev != ecc->dev) - continue; - - clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]), - ecc->channel_unused); - of_node_put(dma_spec.np); - } - return 0; - } - - /* For non-OF case */ - for (i = 0; i < pdev->num_resources; i++) { - struct resource *res = &pdev->resource[i]; - int dma_req; - - if (!(res->flags & IORESOURCE_DMA)) - continue; - - dma_req = (int)res->start; - if (dma_req >= dma_req_min && dma_req < dma_req_max) - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - ecc->channel_unused); - } - - return 0; -} - static void edma_setup_interrupt(struct edma_chan *echan, bool enable) { struct edma_cc *ecc = echan->ecc; @@ -617,7 +576,7 @@ static void edma_start(struct edma_chan *echan) int j = (channel >> 5); unsigned int mask = BIT(channel & 0x1f); - if (test_bit(channel, ecc->channel_unused)) { + if (!echan->hw_triggered) { /* EDMA channels without event association */ dev_dbg(ecc->dev, "ESR%d %08x\n", j, edma_shadow0_read_array(ecc, SH_ESR, j)); @@ -734,20 +693,6 @@ static int edma_alloc_channel(struct edma_chan *echan, struct edma_cc *ecc = echan->ecc; int channel = EDMA_CHAN_SLOT(echan->ch_num); - if (!ecc->unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - int ret = bus_for_each_dev(&platform_bus_type, NULL, ecc, - prepare_unused_channel_list); - if (ret < 0) - return ret; - - ecc->unused_chan_list_done = true; - } - /* ensure access through shadow region 0 */ edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); @@ -899,7 +844,7 @@ static int edma_terminate_all(struct dma_chan *chan) if (echan->edesc) { edma_stop(echan); /* Move the cyclic channel back to default queue */ - if (echan->edesc->cyclic) + if (!echan->tc && echan->edesc->cyclic) edma_assign_channel_eventq(echan, EVENTQ_DEFAULT); /* * free the running request descriptor @@ -1403,7 +1348,8 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( } /* Place the cyclic channel to highest priority queue */ - edma_assign_channel_eventq(echan, EVENTQ_0); + if (!echan->tc) + edma_assign_channel_eventq(echan, EVENTQ_0); return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); } @@ -1609,18 +1555,54 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) return IRQ_HANDLED; } +static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable) +{ + struct platform_device *tc_pdev; + int ret; + + if (!tc) + return; + + tc_pdev = of_find_device_by_node(tc->node); + if (!tc_pdev) { + pr_err("%s: TPTC device is not found\n", __func__); + return; + } + if (!pm_runtime_enabled(&tc_pdev->dev)) + pm_runtime_enable(&tc_pdev->dev); + + if (enable) + ret = pm_runtime_get_sync(&tc_pdev->dev); + else + ret = pm_runtime_put_sync(&tc_pdev->dev); + + if (ret < 0) + pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__, + enable ? "get" : "put", dev_name(&tc_pdev->dev)); +} + /* Alloc channel resources */ static int edma_alloc_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); - struct device *dev = chan->device->dev; + struct edma_cc *ecc = echan->ecc; + struct device *dev = ecc->dev; + enum dma_event_q eventq_no = EVENTQ_DEFAULT; int ret; - ret = edma_alloc_channel(echan, EVENTQ_DEFAULT); + if (echan->tc) { + eventq_no = echan->tc->id; + } else if (ecc->tc_list) { + /* memcpy channel */ + echan->tc = &ecc->tc_list[ecc->info->default_queue]; + eventq_no = echan->tc->id; + } + + ret = edma_alloc_channel(echan, eventq_no); if (ret) return ret; - echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num); + echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); if (echan->slot[0] < 0) { dev_err(dev, "Entry slot allocation failed for channel %u\n", EDMA_CHAN_SLOT(echan->ch_num)); @@ -1631,8 +1613,11 @@ static int edma_alloc_chan_resources(struct dma_chan *chan) edma_set_chmap(echan, echan->slot[0]); echan->alloced = true; - dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num, - EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); + dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", + EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, + echan->hw_triggered ? "HW" : "SW"); + + edma_tc_set_pm_state(echan->tc, true); return 0; @@ -1645,6 +1630,7 @@ err_slot: static void edma_free_chan_resources(struct dma_chan *chan) { struct edma_chan *echan = to_edma_chan(chan); + struct device *dev = echan->ecc->dev; int i; /* Terminate transfers */ @@ -1669,7 +1655,12 @@ static void edma_free_chan_resources(struct dma_chan *chan) echan->alloced = false; } - dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num); + edma_tc_set_pm_state(echan->tc, false); + echan->tc = NULL; + echan->hw_triggered = false; + + dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", + EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); } /* Send pending descriptor to hardware */ @@ -1756,41 +1747,90 @@ static enum dma_status edma_tx_status(struct dma_chan *chan, return ret; } +static bool edma_is_memcpy_channel(int ch_num, u16 *memcpy_channels) +{ + s16 *memcpy_ch = memcpy_channels; + + if (!memcpy_channels) + return false; + while (*memcpy_ch != -1) { + if (*memcpy_ch == ch_num) + return true; + memcpy_ch++; + } + return false; +} + #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) -static void edma_dma_init(struct edma_cc *ecc) +static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) { - struct dma_device *ddev = &ecc->dma_slave; + struct dma_device *s_ddev = &ecc->dma_slave; + struct dma_device *m_ddev = NULL; + s16 *memcpy_channels = ecc->info->memcpy_channels; int i, j; - dma_cap_zero(ddev->cap_mask); - dma_cap_set(DMA_SLAVE, ddev->cap_mask); - dma_cap_set(DMA_CYCLIC, ddev->cap_mask); - dma_cap_set(DMA_MEMCPY, ddev->cap_mask); + dma_cap_zero(s_ddev->cap_mask); + dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); + dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); + if (ecc->legacy_mode && !memcpy_channels) { + dev_warn(ecc->dev, + "Legacy memcpy is enabled, things might not work\n"); - ddev->device_prep_slave_sg = edma_prep_slave_sg; - ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; - ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; - ddev->device_alloc_chan_resources = edma_alloc_chan_resources; - ddev->device_free_chan_resources = edma_free_chan_resources; - ddev->device_issue_pending = edma_issue_pending; - ddev->device_tx_status = edma_tx_status; - ddev->device_config = edma_slave_config; - ddev->device_pause = edma_dma_pause; - ddev->device_resume = edma_dma_resume; - ddev->device_terminate_all = edma_terminate_all; + dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); + s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + s_ddev->directions = BIT(DMA_MEM_TO_MEM); + } - ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; - ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; - ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); - ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + s_ddev->device_prep_slave_sg = edma_prep_slave_sg; + s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; + s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + s_ddev->device_free_chan_resources = edma_free_chan_resources; + s_ddev->device_issue_pending = edma_issue_pending; + s_ddev->device_tx_status = edma_tx_status; + s_ddev->device_config = edma_slave_config; + s_ddev->device_pause = edma_dma_pause; + s_ddev->device_resume = edma_dma_resume; + s_ddev->device_terminate_all = edma_terminate_all; - ddev->dev = ecc->dev; + s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); + s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; - INIT_LIST_HEAD(&ddev->channels); + s_ddev->dev = ecc->dev; + INIT_LIST_HEAD(&s_ddev->channels); + + if (memcpy_channels) { + m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); + ecc->dma_memcpy = m_ddev; + + dma_cap_zero(m_ddev->cap_mask); + dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); + + m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; + m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; + m_ddev->device_free_chan_resources = edma_free_chan_resources; + m_ddev->device_issue_pending = edma_issue_pending; + m_ddev->device_tx_status = edma_tx_status; + m_ddev->device_config = edma_slave_config; + m_ddev->device_pause = edma_dma_pause; + m_ddev->device_resume = edma_dma_resume; + m_ddev->device_terminate_all = edma_terminate_all; + + m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; + m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; + m_ddev->directions = BIT(DMA_MEM_TO_MEM); + m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + + m_ddev->dev = ecc->dev; + INIT_LIST_HEAD(&m_ddev->channels); + } else if (!ecc->legacy_mode) { + dev_info(ecc->dev, "memcpy is disabled\n"); + } for (i = 0; i < ecc->num_channels; i++) { struct edma_chan *echan = &ecc->slave_chans[i]; @@ -1798,7 +1838,10 @@ static void edma_dma_init(struct edma_cc *ecc) echan->ecc = ecc; echan->vchan.desc_free = edma_desc_free; - vchan_init(&echan->vchan, ddev); + if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels)) + vchan_init(&echan->vchan, m_ddev); + else + vchan_init(&echan->vchan, s_ddev); INIT_LIST_HEAD(&echan->node); for (j = 0; j < EDMA_MAX_SLOTS; j++) @@ -1921,7 +1964,8 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, return 0; } -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + bool legacy_mode) { struct edma_soc_info *info; struct property *prop; @@ -1932,20 +1976,121 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) if (!info) return ERR_PTR(-ENOMEM); - prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz); + if (legacy_mode) { + prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", + &sz); + if (prop) { + ret = edma_xbar_event_map(dev, info, sz); + if (ret) + return ERR_PTR(ret); + } + return info; + } + + /* Get the list of channels allocated to be used for memcpy */ + prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); if (prop) { - ret = edma_xbar_event_map(dev, info, sz); + const char pname[] = "ti,edma-memcpy-channels"; + size_t nelm = sz / sizeof(s16); + s16 *memcpy_ch; + + memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s16), + GFP_KERNEL); + if (!memcpy_ch) + return ERR_PTR(-ENOMEM); + + ret = of_property_read_u16_array(dev->of_node, pname, + (u16 *)memcpy_ch, nelm); if (ret) return ERR_PTR(ret); + + memcpy_ch[nelm] = -1; + info->memcpy_channels = memcpy_ch; + } + + prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", + &sz); + if (prop) { + const char pname[] = "ti,edma-reserved-slot-ranges"; + s16 (*rsv_slots)[2]; + size_t nelm = sz / sizeof(*rsv_slots); + struct edma_rsv_info *rsv_info; + + if (!nelm) + return info; + + rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL); + if (!rsv_info) + return ERR_PTR(-ENOMEM); + + rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots), + GFP_KERNEL); + if (!rsv_slots) + return ERR_PTR(-ENOMEM); + + ret = of_property_read_u16_array(dev->of_node, pname, + (u16 *)rsv_slots, nelm * 2); + if (ret) + return ERR_PTR(ret); + + rsv_slots[nelm][0] = -1; + rsv_slots[nelm][1] = -1; + info->rsv = rsv_info; + info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; } return info; } + +static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct edma_cc *ecc = ofdma->of_dma_data; + struct dma_chan *chan = NULL; + struct edma_chan *echan; + int i; + + if (!ecc || dma_spec->args_count < 1) + return NULL; + + for (i = 0; i < ecc->num_channels; i++) { + echan = &ecc->slave_chans[i]; + if (echan->ch_num == dma_spec->args[0]) { + chan = &echan->vchan.chan; + break; + } + } + + if (!chan) + return NULL; + + if (echan->ecc->legacy_mode && dma_spec->args_count == 1) + goto out; + + if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && + dma_spec->args[1] < echan->ecc->num_tc) { + echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; + goto out; + } + + return NULL; +out: + /* The channel is going to be used as HW synchronized */ + echan->hw_triggered = true; + return dma_get_slave_channel(chan); +} #else -static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev) +static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, + bool legacy_mode) { return ERR_PTR(-EINVAL); } + +static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + return NULL; +} #endif static int edma_probe(struct platform_device *pdev) @@ -1953,7 +2098,6 @@ static int edma_probe(struct platform_device *pdev) struct edma_soc_info *info = pdev->dev.platform_data; s8 (*queue_priority_mapping)[2]; int i, off, ln; - const s16 (*rsv_chans)[2]; const s16 (*rsv_slots)[2]; const s16 (*xbar_chans)[2]; int irq; @@ -1962,10 +2106,17 @@ static int edma_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; struct device *dev = &pdev->dev; struct edma_cc *ecc; + bool legacy_mode = true; int ret; if (node) { - info = edma_setup_info_from_dt(dev); + const struct of_device_id *match; + + match = of_match_node(edma_of_ids, node); + if (match && (u32)match->data == EDMA_BINDING_TPCC) + legacy_mode = false; + + info = edma_setup_info_from_dt(dev, legacy_mode); if (IS_ERR(info)) { dev_err(dev, "failed to get DT data\n"); return PTR_ERR(info); @@ -1994,6 +2145,7 @@ static int edma_probe(struct platform_device *pdev) ecc->dev = dev; ecc->id = pdev->id; + ecc->legacy_mode = legacy_mode; /* When booting with DT the pdev->id is -1 */ if (ecc->id < 0) ecc->id = 0; @@ -2024,12 +2176,6 @@ static int edma_probe(struct platform_device *pdev) if (!ecc->slave_chans) return -ENOMEM; - ecc->channel_unused = devm_kcalloc(dev, - BITS_TO_LONGS(ecc->num_channels), - sizeof(unsigned long), GFP_KERNEL); - if (!ecc->channel_unused) - return -ENOMEM; - ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), sizeof(unsigned long), GFP_KERNEL); if (!ecc->slot_inuse) @@ -2040,20 +2186,7 @@ static int edma_probe(struct platform_device *pdev) for (i = 0; i < ecc->num_slots; i++) edma_write_slot(ecc, i, &dummy_paramset); - /* Mark all channels as unused */ - memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused)); - if (info->rsv) { - /* Clear the reserved channels in unused list */ - rsv_chans = info->rsv->rsv_chans; - if (rsv_chans) { - for (i = 0; rsv_chans[i][0] != -1; i++) { - off = rsv_chans[i][0]; - ln = rsv_chans[i][1]; - clear_bits(off, ln, ecc->channel_unused); - } - } - /* Set the reserved slots in inuse list */ rsv_slots = info->rsv->rsv_slots; if (rsv_slots) { @@ -2070,7 +2203,6 @@ static int edma_probe(struct platform_device *pdev) if (xbar_chans) { for (i = 0; xbar_chans[i][1] != -1; i++) { off = xbar_chans[i][1]; - clear_bits(off, 1, ecc->channel_unused); } } @@ -2112,6 +2244,31 @@ static int edma_probe(struct platform_device *pdev) queue_priority_mapping = info->queue_priority_mapping; + if (!ecc->legacy_mode) { + int lowest_priority = 0; + struct of_phandle_args tc_args; + + ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, + sizeof(*ecc->tc_list), GFP_KERNEL); + if (!ecc->tc_list) + return -ENOMEM; + + for (i = 0;; i++) { + ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs", + 1, i, &tc_args); + if (ret || i == ecc->num_tc) + break; + + ecc->tc_list[i].node = tc_args.np; + ecc->tc_list[i].id = i; + queue_priority_mapping[i][1] = tc_args.args[0]; + if (queue_priority_mapping[i][1] > lowest_priority) { + lowest_priority = queue_priority_mapping[i][1]; + info->default_queue = i; + } + } + } + /* Event queue priority mapping */ for (i = 0; queue_priority_mapping[i][0] != -1; i++) edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], @@ -2125,7 +2282,7 @@ static int edma_probe(struct platform_device *pdev) ecc->info = info; /* Init the dma device and channels */ - edma_dma_init(ecc); + edma_dma_init(ecc, legacy_mode); for (i = 0; i < ecc->num_channels; i++) { /* Assign all channels to the default queue */ @@ -2136,12 +2293,23 @@ static int edma_probe(struct platform_device *pdev) } ret = dma_async_device_register(&ecc->dma_slave); - if (ret) + if (ret) { + dev_err(dev, "slave ddev registration failed (%d)\n", ret); goto err_reg1; + } + + if (ecc->dma_memcpy) { + ret = dma_async_device_register(ecc->dma_memcpy); + if (ret) { + dev_err(dev, "memcpy ddev registration failed (%d)\n", + ret); + dma_async_device_unregister(&ecc->dma_slave); + goto err_reg1; + } + } if (node) - of_dma_controller_register(node, of_dma_xlate_by_chan_id, - &ecc->dma_slave); + of_dma_controller_register(node, of_edma_xlate, ecc); dev_info(dev, "TI EDMA DMA engine driver\n"); @@ -2160,12 +2328,30 @@ static int edma_remove(struct platform_device *pdev) if (dev->of_node) of_dma_controller_free(dev->of_node); dma_async_device_unregister(&ecc->dma_slave); + if (ecc->dma_memcpy) + dma_async_device_unregister(ecc->dma_memcpy); edma_free_slot(ecc, ecc->dummy_slot); return 0; } #ifdef CONFIG_PM_SLEEP +static int edma_pm_suspend(struct device *dev) +{ + struct edma_cc *ecc = dev_get_drvdata(dev); + struct edma_chan *echan = ecc->slave_chans; + int i; + + for (i = 0; i < ecc->num_channels; i++) { + if (echan[i].alloced) { + edma_setup_interrupt(&echan[i], false); + edma_tc_set_pm_state(echan[i].tc, false); + } + } + + return 0; +} + static int edma_pm_resume(struct device *dev) { struct edma_cc *ecc = dev_get_drvdata(dev); @@ -2190,6 +2376,8 @@ static int edma_pm_resume(struct device *dev) /* Set up channel -> slot mapping for the entry slot */ edma_set_chmap(&echan[i], echan[i].slot[0]); + + edma_tc_set_pm_state(echan[i].tc, true); } } @@ -2198,7 +2386,7 @@ static int edma_pm_resume(struct device *dev) #endif static const struct dev_pm_ops edma_pm_ops = { - SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume) + SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume) }; static struct platform_driver edma_driver = { @@ -2213,12 +2401,18 @@ static struct platform_driver edma_driver = { bool edma_filter_fn(struct dma_chan *chan, void *param) { + bool match = false; + if (chan->device->dev->driver == &edma_driver.driver) { struct edma_chan *echan = to_edma_chan(chan); unsigned ch_req = *(unsigned *)param; - return ch_req == echan->ch_num; + if (ch_req == echan->ch_num) { + /* The channel is going to be used as HW synchronized */ + echan->hw_triggered = true; + match = true; + } } - return false; + return match; } EXPORT_SYMBOL(edma_filter_fn); diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index 6b9d500956e4..e2878baeb90e 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h @@ -71,6 +71,9 @@ struct edma_soc_info { /* Resource reservation for other cores */ struct edma_rsv_info *rsv; + /* List of channels allocated for memcpy, terminated with -1 */ + s16 *memcpy_channels; + s8 (*queue_priority_mapping)[2]; const s16 (*xbar_chans)[2]; }; From d871cd2ec5abf8715774bcb90aa32ae5b750b587 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:11 +0300 Subject: [PATCH 67/77] ARM: DTS: am33xx: Use the new DT bindings for the eDMA3 Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and enable the DMA even crossbar with ti,am335x-edma-crossbar. With the new bindings boards can customize and tweak the DMA channel priority to match their needs. With the new binding the memcpy is safe to be used since with the old binding it was not possible for a driver to know which channel is allowed to be used as non HW triggered channel. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/boot/dts/am335x-evm.dts | 9 +-- arch/arm/boot/dts/am335x-pepper.dts | 11 +--- arch/arm/boot/dts/am33xx.dtsi | 96 +++++++++++++++++++++-------- 3 files changed, 73 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 1942a5c8132d..507980672c32 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -743,8 +743,8 @@ &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; @@ -766,11 +766,6 @@ }; }; -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 7106114c7464..39073b921664 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -339,13 +339,6 @@ ti,non-removable; }; -&edma { - /* Map eDMA MMC2 Events from Crossbar */ - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - - &mmc3 { /* Wifi & Bluetooth on MMC #3 */ status = "okay"; @@ -354,8 +347,8 @@ vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; ti,non-removable; - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d23e2524d694..6053e75c6e99 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -174,12 +174,54 @@ }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = <12 13 14>; - #dma-cells = <1>; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = /bits/ 16 <20 21>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_xbar: dma-router@44e10f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0x44e10f90 0x40>; + + #dma-cells = <3>; + dma-requests = <32>; + + dma-masters = <&edma>; }; gpio0: gpio@44e07000 { @@ -233,7 +275,7 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; - dmas = <&edma 26>, <&edma 27>; + dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; @@ -244,7 +286,7 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; - dmas = <&edma 28>, <&edma 29>; + dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; @@ -255,7 +297,7 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; - dmas = <&edma 30>, <&edma 31>; + dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; @@ -322,8 +364,8 @@ ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma_xbar 24 0 0 + &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; interrupt-parent = <&intc>; @@ -335,8 +377,8 @@ compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0 + &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; interrupt-parent = <&intc>; @@ -474,10 +516,10 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 - &edma 17 - &edma 18 - &edma 19>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -490,10 +532,10 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -831,7 +873,7 @@ ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; }; @@ -840,8 +882,8 @@ ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; - dmas = <&edma 6>, - <&edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -854,8 +896,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; @@ -868,8 +910,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; From e3faf2b8826b8ac58cdaad7f801e59e389320f0e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 16 Oct 2015 10:18:12 +0300 Subject: [PATCH 68/77] ARM: DTS: am437x: Use the new DT bindings for the eDMA3 Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and enable the DMA even crossbar with ti,am335x-edma-crossbar. With the new bindings boards can customize and tweak the DMA channel priority to match their needs. With the new binding the memcpy is safe to be used since with the old binding it was not possible for a driver to know which channel is allowed to be used as non HW triggered channel. Signed-off-by: Peter Ujfalusi Signed-off-by: Vinod Koul --- arch/arm/boot/dts/am4372.dtsi | 82 ++++++++++++++++++++++------- arch/arm/boot/dts/am437x-gp-evm.dts | 9 +--- 2 files changed, 64 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0447c04a40cc..461548ed69fd 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -183,14 +183,56 @@ }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x10>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = , - , - ; - #dma-cells = <1>; + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = /bits/ 16 <32 33>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_xbar: dma-router@44e10f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0x44e10f90 0x40>; + + #dma-cells = <3>; + dma-requests = <64>; + + dma-masters = <&edma>; }; uart0: serial@44e09000 { @@ -495,8 +537,8 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma 24 0>, + <&edma 25 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -507,8 +549,8 @@ reg = <0x481d8000 0x1000>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0>, + <&edma 3 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -775,7 +817,7 @@ compatible = "ti,omap5-sham"; ti,hwmods = "sham"; reg = <0x53100000 0x300>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; interrupts = ; }; @@ -785,8 +827,8 @@ ti,hwmods = "aes"; reg = <0x53501000 0xa0>; interrupts = ; - dmas = <&edma 6 - &edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -795,8 +837,8 @@ ti,hwmods = "des"; reg = <0x53701000 0xa0>; interrupts = ; - dmas = <&edma 34 - &edma 33>; + dmas = <&edma 34 0>, + <&edma 33 0>; dma-names = "tx", "rx"; }; @@ -809,8 +851,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; @@ -823,8 +865,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 22038f21f228..28e3b252c08c 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -711,8 +711,8 @@ status = "okay"; /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 30 - &edma 31>; + dmas = <&edma_xbar 30 0 1>, + <&edma_xbar 31 0 2>; dma-names = "tx", "rx"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; @@ -733,11 +733,6 @@ }; }; -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 30 - 2 31>; -}; - &uart3 { status = "okay"; pinctrl-names = "default"; From 28ca3e8556e3ecda74adf1c4c3453ed9d5b9e5e6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 20 Oct 2015 13:14:45 +0200 Subject: [PATCH 69/77] dmaengine: virt-dma: Fix kernel-doc annotations In kernel-doc annotations parameters need to start with a @ for them to be properly recognized. Add those where missing for virt-dma. Signed-off-by: Lars-Peter Clausen Signed-off-by: Vinod Koul --- drivers/dma/virt-dma.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h index 181b95267866..2fa47745a41f 100644 --- a/drivers/dma/virt-dma.h +++ b/drivers/dma/virt-dma.h @@ -47,9 +47,9 @@ struct virt_dma_desc *vchan_find_desc(struct virt_dma_chan *, dma_cookie_t); /** * vchan_tx_prep - prepare a descriptor - * vc: virtual channel allocating this descriptor - * vd: virtual descriptor to prepare - * tx_flags: flags argument passed in to prepare function + * @vc: virtual channel allocating this descriptor + * @vd: virtual descriptor to prepare + * @tx_flags: flags argument passed in to prepare function */ static inline struct dma_async_tx_descriptor *vchan_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd, unsigned long tx_flags) @@ -65,7 +65,7 @@ static inline struct dma_async_tx_descriptor *vchan_tx_prep(struct virt_dma_chan /** * vchan_issue_pending - move submitted descriptors to issued list - * vc: virtual channel to update + * @vc: virtual channel to update * * vc.lock must be held by caller */ @@ -77,7 +77,7 @@ static inline bool vchan_issue_pending(struct virt_dma_chan *vc) /** * vchan_cookie_complete - report completion of a descriptor - * vd: virtual descriptor to update + * @vd: virtual descriptor to update * * vc.lock must be held by caller */ @@ -97,7 +97,7 @@ static inline void vchan_cookie_complete(struct virt_dma_desc *vd) /** * vchan_cyclic_callback - report the completion of a period - * vd: virtual descriptor + * @vd: virtual descriptor */ static inline void vchan_cyclic_callback(struct virt_dma_desc *vd) { @@ -109,7 +109,7 @@ static inline void vchan_cyclic_callback(struct virt_dma_desc *vd) /** * vchan_next_desc - peek at the next descriptor to be processed - * vc: virtual channel to obtain descriptor from + * @vc: virtual channel to obtain descriptor from * * vc.lock must be held by caller */ @@ -123,8 +123,8 @@ static inline struct virt_dma_desc *vchan_next_desc(struct virt_dma_chan *vc) /** * vchan_get_all_descriptors - obtain all submitted and issued descriptors - * vc: virtual channel to get descriptors from - * head: list of descriptors found + * @vc: virtual channel to get descriptors from + * @head: list of descriptors found * * vc.lock must be held by caller * From ce2a673d66b2cab4b459981be1a28bbb6c071555 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 22 Oct 2015 11:40:59 +0200 Subject: [PATCH 70/77] dmaengine: hdmac: factorise memset descriptor allocation The memset and scatter gathered memset are going to use some common logic to create their descriptors. Move that logic into a function of its own so that we can share it with the future memset_sg callback. Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 105 +++++++++++++++++++++--------------- drivers/dma/at_hdmac_regs.h | 2 +- 2 files changed, 62 insertions(+), 45 deletions(-) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index 58d406230d89..cad18f3660ae 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -458,10 +458,10 @@ atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) dma_cookie_complete(txd); /* If the transfer was a memset, free our temporary buffer */ - if (desc->memset) { + if (desc->memset_buffer) { dma_pool_free(atdma->memset_pool, desc->memset_vaddr, desc->memset_paddr); - desc->memset = false; + desc->memset_buffer = false; } /* move children to free_list */ @@ -881,6 +881,46 @@ err_desc_get: return NULL; } +static struct at_desc *atc_create_memset_desc(struct dma_chan *chan, + dma_addr_t psrc, + dma_addr_t pdst, + size_t len) +{ + struct at_dma_chan *atchan = to_at_dma_chan(chan); + struct at_desc *desc; + size_t xfer_count; + + u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2); + u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN | + ATC_SRC_ADDR_MODE_FIXED | + ATC_DST_ADDR_MODE_INCR | + ATC_FC_MEM2MEM; + + xfer_count = len >> 2; + if (xfer_count > ATC_BTSIZE_MAX) { + dev_err(chan2dev(chan), "%s: buffer is too big\n", + __func__); + return NULL; + } + + desc = atc_desc_get(atchan); + if (!desc) { + dev_err(chan2dev(chan), "%s: can't get a descriptor\n", + __func__); + return NULL; + } + + desc->lli.saddr = psrc; + desc->lli.daddr = pdst; + desc->lli.ctrla = ctrla | xfer_count; + desc->lli.ctrlb = ctrlb; + + desc->txd.cookie = 0; + desc->len = len; + + return desc; +} + /** * atc_prep_dma_memset - prepare a memcpy operation * @chan: the channel to prepare operation on @@ -893,12 +933,10 @@ static struct dma_async_tx_descriptor * atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, size_t len, unsigned long flags) { - struct at_dma_chan *atchan = to_at_dma_chan(chan); struct at_dma *atdma = to_at_dma(chan->device); - struct at_desc *desc = NULL; - size_t xfer_count; - u32 ctrla; - u32 ctrlb; + struct at_desc *desc; + void __iomem *vaddr; + dma_addr_t paddr; dev_vdbg(chan2dev(chan), "%s: d0x%x v0x%x l0x%zx f0x%lx\n", __func__, dest, value, len, flags); @@ -914,46 +952,26 @@ atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, return NULL; } - xfer_count = len >> 2; - if (xfer_count > ATC_BTSIZE_MAX) { - dev_err(chan2dev(chan), "%s: buffer is too big\n", - __func__); - return NULL; - } - - ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN - | ATC_SRC_ADDR_MODE_FIXED - | ATC_DST_ADDR_MODE_INCR - | ATC_FC_MEM2MEM; - - ctrla = ATC_SRC_WIDTH(2) | - ATC_DST_WIDTH(2); - - desc = atc_desc_get(atchan); - if (!desc) { - dev_err(chan2dev(chan), "%s: can't get a descriptor\n", - __func__); - return NULL; - } - - desc->memset_vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, - &desc->memset_paddr); - if (!desc->memset_vaddr) { + vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr); + if (!vaddr) { dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", __func__); - goto err_put_desc; + return NULL; + } + *(u32*)vaddr = value; + + desc = atc_create_memset_desc(chan, paddr, dest, len); + if (!desc) { + dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n", + __func__); + goto err_free_buffer; } - *desc->memset_vaddr = value; - desc->memset = true; - - desc->lli.saddr = desc->memset_paddr; - desc->lli.daddr = dest; - desc->lli.ctrla = ctrla | xfer_count; - desc->lli.ctrlb = ctrlb; + desc->memset_paddr = paddr; + desc->memset_vaddr = vaddr; + desc->memset_buffer = true; desc->txd.cookie = -EBUSY; - desc->len = len; desc->total_len = len; /* set end-of-link on the descriptor */ @@ -963,12 +981,11 @@ atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, return &desc->txd; -err_put_desc: - atc_desc_put(atchan, desc); +err_free_buffer: + dma_pool_free(atdma->memset_pool, vaddr, paddr); return NULL; } - /** * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction * @chan: DMA channel diff --git a/drivers/dma/at_hdmac_regs.h b/drivers/dma/at_hdmac_regs.h index c3bebbe899ac..d1cfc8c876f9 100644 --- a/drivers/dma/at_hdmac_regs.h +++ b/drivers/dma/at_hdmac_regs.h @@ -202,7 +202,7 @@ struct at_desc { size_t src_hole; /* Memset temporary buffer */ - bool memset; + bool memset_buffer; dma_addr_t memset_paddr; int *memset_vaddr; }; From 67d25f0d4e24775418aae403610cae99e27cdc3c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 22 Oct 2015 11:41:00 +0200 Subject: [PATCH 71/77] dmaengine: hdmac: Add scatter-gathered memset support Just like memset support, the HDMAC might be used to do a memset over a discontiguous memory area. In such a case, we'll just build up a chain of memset descriptors over the contiguous chunks of memory to set, in order to allow such a support. Signed-off-by: Maxime Ripard Acked-by: Nicolas Ferre Signed-off-by: Vinod Koul --- drivers/dma/at_hdmac.c | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c index cad18f3660ae..4e55239c7a30 100644 --- a/drivers/dma/at_hdmac.c +++ b/drivers/dma/at_hdmac.c @@ -986,6 +986,83 @@ err_free_buffer: return NULL; } +static struct dma_async_tx_descriptor * +atc_prep_dma_memset_sg(struct dma_chan *chan, + struct scatterlist *sgl, + unsigned int sg_len, int value, + unsigned long flags) +{ + struct at_dma_chan *atchan = to_at_dma_chan(chan); + struct at_dma *atdma = to_at_dma(chan->device); + struct at_desc *desc = NULL, *first = NULL, *prev = NULL; + struct scatterlist *sg; + void __iomem *vaddr; + dma_addr_t paddr; + size_t total_len = 0; + int i; + + dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__, + value, sg_len, flags); + + if (unlikely(!sgl || !sg_len)) { + dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n", + __func__); + return NULL; + } + + vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr); + if (!vaddr) { + dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n", + __func__); + return NULL; + } + *(u32*)vaddr = value; + + for_each_sg(sgl, sg, sg_len, i) { + dma_addr_t dest = sg_dma_address(sg); + size_t len = sg_dma_len(sg); + + dev_vdbg(chan2dev(chan), "%s: d0x%08x, l0x%zx\n", + __func__, dest, len); + + if (!is_dma_fill_aligned(chan->device, dest, 0, len)) { + dev_err(chan2dev(chan), "%s: buffer is not aligned\n", + __func__); + goto err_put_desc; + } + + desc = atc_create_memset_desc(chan, paddr, dest, len); + if (!desc) + goto err_put_desc; + + atc_desc_chain(&first, &prev, desc); + + total_len += len; + } + + /* + * Only set the buffer pointers on the last descriptor to + * avoid free'ing while we have our transfer still going + */ + desc->memset_paddr = paddr; + desc->memset_vaddr = vaddr; + desc->memset_buffer = true; + + first->txd.cookie = -EBUSY; + first->total_len = total_len; + + /* set end-of-link on the descriptor */ + set_desc_eol(desc); + + first->txd.flags = flags; + + return &first->txd; + +err_put_desc: + atc_desc_put(atchan, first); + return NULL; +} + /** * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction * @chan: DMA channel @@ -1868,6 +1945,7 @@ static int __init at_dma_probe(struct platform_device *pdev) dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask); dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask); + dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask); dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask); dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask); @@ -1989,6 +2067,7 @@ static int __init at_dma_probe(struct platform_device *pdev) if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) { atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset; + atdma->dma_common.device_prep_dma_memset_sg = atc_prep_dma_memset_sg; atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES; } From 30cb2639aa5253cf5bc4bd7dc5ea7e61b6887379 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 13 Oct 2015 20:09:17 +0300 Subject: [PATCH 72/77] dmaengine: dw: don't override platform data with autocfg Let probe driver decide either it wants to auto configure the driver or have explicitly defined properties. Signed-off-by: Andy Shevchenko Acked-by: Viresh Kumar Signed-off-by: Vinod Koul --- drivers/dma/dw/core.c | 57 ++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index 46859f738fcf..f16d1ed99ba9 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1499,9 +1499,8 @@ EXPORT_SYMBOL(dw_dma_cyclic_free); int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) { struct dw_dma *dw; - bool autocfg; + bool autocfg = false; unsigned int dw_params; - unsigned int nr_channels; unsigned int max_blk_size = 0; int err; int i; @@ -1515,33 +1514,41 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) pm_runtime_get_sync(chip->dev); - dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); - autocfg = dw_params >> DW_PARAMS_EN & 0x1; + if (!pdata) { + dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); + dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); - dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); + autocfg = dw_params >> DW_PARAMS_EN & 1; + if (!autocfg) { + err = -EINVAL; + goto err_pdata; + } - if (!pdata && autocfg) { pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) { err = -ENOMEM; goto err_pdata; } + /* Get hardware configuration parameters */ + pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; + pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; + for (i = 0; i < pdata->nr_masters; i++) { + pdata->data_width[i] = + (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; + } + max_blk_size = dma_readl(dw, MAX_BLK_SIZE); + /* Fill platform data with the default values */ pdata->is_private = true; pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; pdata->chan_priority = CHAN_PRIORITY_ASCENDING; - } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { + } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { err = -EINVAL; goto err_pdata; } - if (autocfg) - nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1; - else - nr_channels = pdata->nr_channels; - - dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan), + dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), GFP_KERNEL); if (!dw->chan) { err = -ENOMEM; @@ -1549,22 +1556,12 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) } /* Get hardware configuration parameters */ - if (autocfg) { - max_blk_size = dma_readl(dw, MAX_BLK_SIZE); - - dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; - for (i = 0; i < dw->nr_masters; i++) { - dw->data_width[i] = - (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2; - } - } else { - dw->nr_masters = pdata->nr_masters; - for (i = 0; i < dw->nr_masters; i++) - dw->data_width[i] = pdata->data_width[i]; - } + dw->nr_masters = pdata->nr_masters; + for (i = 0; i < dw->nr_masters; i++) + dw->data_width[i] = pdata->data_width[i]; /* Calculate all channel mask before DMA setup */ - dw->all_chan_mask = (1 << nr_channels) - 1; + dw->all_chan_mask = (1 << pdata->nr_channels) - 1; /* Force dma off, just in case */ dw_dma_off(dw); @@ -1589,7 +1586,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) goto err_pdata; INIT_LIST_HEAD(&dw->dma.channels); - for (i = 0; i < nr_channels; i++) { + for (i = 0; i < pdata->nr_channels; i++) { struct dw_dma_chan *dwc = &dw->chan[i]; int r = nr_channels - i - 1; @@ -1603,7 +1600,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* 7 is highest priority & 0 is lowest. */ if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) - dwc->priority = r; + dwc->priority = pdata->nr_channels - i - 1; else dwc->priority = i; @@ -1687,7 +1684,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) goto err_dma_register; dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", - nr_channels); + pdata->nr_channels); pm_runtime_put_sync_suspend(chip->dev); From 175267b389f781748e2bbb6c737e76b5c9bc4c88 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 13 Oct 2015 20:09:18 +0300 Subject: [PATCH 73/77] dmaengine: dw: platform: provide platform data for Intel Provide platform data explicitly for Intel SoCs where dw_dmac is enumerated by ACPI. Signed-off-by: Andy Shevchenko Acked-by: Viresh Kumar Signed-off-by: Vinod Koul --- drivers/dma/dw/platform.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c index b2c3ae071429..68a4815750b5 100644 --- a/drivers/dma/dw/platform.c +++ b/drivers/dma/dw/platform.c @@ -155,6 +155,7 @@ static int dw_probe(struct platform_device *pdev) struct dw_dma_chip *chip; struct device *dev = &pdev->dev; struct resource *mem; + const struct acpi_device_id *id; struct dw_dma_platform_data *pdata; int err; @@ -178,6 +179,11 @@ static int dw_probe(struct platform_device *pdev) pdata = dev_get_platdata(dev); if (!pdata) pdata = dw_dma_parse_dt(pdev); + if (!pdata && has_acpi_companion(dev)) { + id = acpi_match_device(dev->driver->acpi_match_table, dev); + if (id) + pdata = (struct dw_dma_platform_data *)id->driver_data; + } chip->dev = dev; @@ -246,8 +252,17 @@ MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); #endif #ifdef CONFIG_ACPI +static struct dw_dma_platform_data dw_dma_acpi_pdata = { + .nr_channels = 8, + .is_private = true, + .chan_allocation_order = CHAN_ALLOCATION_ASCENDING, + .chan_priority = CHAN_PRIORITY_ASCENDING, + .block_size = 4095, + .nr_masters = 2, +}; + static const struct acpi_device_id dw_dma_acpi_id_table[] = { - { "INTL9C60", 0 }, + { "INTL9C60", (kernel_ulong_t)&dw_dma_acpi_pdata }, { } }; MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table); From df5c7386f62d2db95ca48005087195e9a15e2b1f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 13 Oct 2015 20:09:19 +0300 Subject: [PATCH 74/77] dmaengine: dw: some Intel devices has no memcpy support Provide a flag to choose if the device does support memory-to-memory transfers. At least this is not true for iDMA32 controller that might be supported in the future. Besides that Intel BayTrail and Braswell users should not try this feature due to HW specific behaviour. Signed-off-by: Andy Shevchenko Acked-by: Viresh Kumar Signed-off-by: Vinod Koul --- drivers/dma/dw/core.c | 6 +++++- include/linux/platform_data/dma-dw.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index f16d1ed99ba9..41e9554b884d 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -1541,6 +1541,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) /* Fill platform data with the default values */ pdata->is_private = true; + pdata->is_memcpy = true; pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; pdata->chan_priority = CHAN_PRIORITY_ASCENDING; } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { @@ -1653,10 +1654,13 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); - dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); + /* Set capabilities */ dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); if (pdata->is_private) dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); + if (pdata->is_memcpy) + dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); + dw->dma.dev = chip->dev; dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; dw->dma.device_free_chan_resources = dwc_free_chan_resources; diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index 87ac14c584f2..03b6095d3b18 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -37,6 +37,7 @@ struct dw_dma_slave { * @nr_channels: Number of channels supported by hardware (max 8) * @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. + * @is_memcpy: The device channels do support memory-to-memory transfers. * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller @@ -47,6 +48,7 @@ struct dw_dma_slave { struct dw_dma_platform_data { unsigned int nr_channels; bool is_private; + bool is_memcpy; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order; From b1c4e98296d2f08e3fcc9aab0c1103e0bc05d9f3 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 2 Nov 2015 21:05:29 +0530 Subject: [PATCH 75/77] Revert "ARM: DTS: am437x: Use the new DT bindings for the eDMA3" This reverts commit e3faf2b8826b8ac58cdaad7f801e59e389320f0e as it causes regression in BBB Reported-by: Olof Johansson Signed-off-by: Vinod Koul --- arch/arm/boot/dts/am4372.dtsi | 82 +++++++---------------------- arch/arm/boot/dts/am437x-gp-evm.dts | 9 +++- 2 files changed, 27 insertions(+), 64 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 461548ed69fd..0447c04a40cc 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -183,56 +183,14 @@ }; edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x10>; interrupts = , - , - ; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = /bits/ 16 <32 33>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = ; - interrupt-names = "edma3_tcerrint"; - }; - - edma_xbar: dma-router@44e10f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0x44e10f90 0x40>; - - #dma-cells = <3>; - dma-requests = <64>; - - dma-masters = <&edma>; + , + ; + #dma-cells = <1>; }; uart0: serial@44e09000 { @@ -537,8 +495,8 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&edma 24 0>, - <&edma 25 0>; + dmas = <&edma 24 + &edma 25>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -549,8 +507,8 @@ reg = <0x481d8000 0x1000>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 0>, - <&edma 3 0>; + dmas = <&edma 2 + &edma 3>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -817,7 +775,7 @@ compatible = "ti,omap5-sham"; ti,hwmods = "sham"; reg = <0x53100000 0x300>; - dmas = <&edma 36 0>; + dmas = <&edma 36>; dma-names = "rx"; interrupts = ; }; @@ -827,8 +785,8 @@ ti,hwmods = "aes"; reg = <0x53501000 0xa0>; interrupts = ; - dmas = <&edma 6 0>, - <&edma 5 0>; + dmas = <&edma 6 + &edma 5>; dma-names = "tx", "rx"; }; @@ -837,8 +795,8 @@ ti,hwmods = "des"; reg = <0x53701000 0xa0>; interrupts = ; - dmas = <&edma 34 0>, - <&edma 33 0>; + dmas = <&edma 34 + &edma 33>; dma-names = "tx", "rx"; }; @@ -851,8 +809,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; + dmas = <&edma 8>, + <&edma 9>; dma-names = "tx", "rx"; }; @@ -865,8 +823,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; + dmas = <&edma 10>, + <&edma 11>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 28e3b252c08c..22038f21f228 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -711,8 +711,8 @@ status = "okay"; /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma_xbar 30 0 1>, - <&edma_xbar 31 0 2>; + dmas = <&edma 30 + &edma 31>; dma-names = "tx", "rx"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; @@ -733,6 +733,11 @@ }; }; +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 30 + 2 31>; +}; + &uart3 { status = "okay"; pinctrl-names = "default"; From 829a2fac71b83c1689213337e8cfc58a9ea12211 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Mon, 2 Nov 2015 21:06:46 +0530 Subject: [PATCH 76/77] Revert "ARM: DTS: am33xx: Use the new DT bindings for the eDMA3" This reverts commit d871cd2ec5abf8715774bcb90aa32ae5b750b587 as it causes regression in BBB Reported-by: Olof Johansson Signed-off-by: Vinod Koul --- arch/arm/boot/dts/am335x-evm.dts | 9 ++- arch/arm/boot/dts/am335x-pepper.dts | 11 +++- arch/arm/boot/dts/am33xx.dtsi | 96 ++++++++--------------------- 3 files changed, 43 insertions(+), 73 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 507980672c32..1942a5c8132d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -743,8 +743,8 @@ &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; + dmas = <&edma 12 + &edma 13>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; @@ -766,6 +766,11 @@ }; }; +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 12 + 2 13>; +}; + &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 39073b921664..7106114c7464 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -339,6 +339,13 @@ ti,non-removable; }; +&edma { + /* Map eDMA MMC2 Events from Crossbar */ + ti,edma-xbar-event-map = /bits/ 16 <1 12 + 2 13>; +}; + + &mmc3 { /* Wifi & Bluetooth on MMC #3 */ status = "okay"; @@ -347,8 +354,8 @@ vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; ti,non-removable; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; + dmas = <&edma 12 + &edma 13>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 6053e75c6e99..d23e2524d694 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -174,54 +174,12 @@ }; edma: edma@49000000 { - compatible = "ti,edma3-tpcc"; - ti,hwmods = "tpcc"; - reg = <0x49000000 0x10000>; - reg-names = "edma3_cc"; + compatible = "ti,edma3"; + ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; + reg = <0x49000000 0x10000>, + <0x44e10f90 0x40>; interrupts = <12 13 14>; - interrupt-names = "edma3_ccint", "emda3_mperr", - "edma3_ccerrint"; - dma-requests = <64>; - #dma-cells = <2>; - - ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, - <&edma_tptc2 0>; - - ti,edma-memcpy-channels = /bits/ 16 <20 21>; - }; - - edma_tptc0: tptc@49800000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc0"; - reg = <0x49800000 0x100000>; - interrupts = <112>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_tptc2: tptc@49a00000 { - compatible = "ti,edma3-tptc"; - ti,hwmods = "tptc2"; - reg = <0x49a00000 0x100000>; - interrupts = <114>; - interrupt-names = "edma3_tcerrint"; - }; - - edma_xbar: dma-router@44e10f90 { - compatible = "ti,am335x-edma-crossbar"; - reg = <0x44e10f90 0x40>; - - #dma-cells = <3>; - dma-requests = <32>; - - dma-masters = <&edma>; + #dma-cells = <1>; }; gpio0: gpio@44e07000 { @@ -275,7 +233,7 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; - dmas = <&edma 26 0>, <&edma 27 0>; + dmas = <&edma 26>, <&edma 27>; dma-names = "tx", "rx"; }; @@ -286,7 +244,7 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; - dmas = <&edma 28 0>, <&edma 29 0>; + dmas = <&edma 28>, <&edma 29>; dma-names = "tx", "rx"; }; @@ -297,7 +255,7 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; - dmas = <&edma 30 0>, <&edma 31 0>; + dmas = <&edma 30>, <&edma 31>; dma-names = "tx", "rx"; }; @@ -364,8 +322,8 @@ ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; - dmas = <&edma_xbar 24 0 0 - &edma_xbar 25 0 0>; + dmas = <&edma 24 + &edma 25>; dma-names = "tx", "rx"; interrupts = <64>; interrupt-parent = <&intc>; @@ -377,8 +335,8 @@ compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 0 - &edma 3 0>; + dmas = <&edma 2 + &edma 3>; dma-names = "tx", "rx"; interrupts = <28>; interrupt-parent = <&intc>; @@ -516,10 +474,10 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 0 - &edma 17 0 - &edma 18 0 - &edma 19 0>; + dmas = <&edma 16 + &edma 17 + &edma 18 + &edma 19>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -532,10 +490,10 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 0 - &edma 43 0 - &edma 44 0 - &edma 45 0>; + dmas = <&edma 42 + &edma 43 + &edma 44 + &edma 45>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -873,7 +831,7 @@ ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; - dmas = <&edma 36 0>; + dmas = <&edma 36>; dma-names = "rx"; }; @@ -882,8 +840,8 @@ ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; - dmas = <&edma 6 0>, - <&edma 5 0>; + dmas = <&edma 6>, + <&edma 5>; dma-names = "tx", "rx"; }; @@ -896,8 +854,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8 2>, - <&edma 9 2>; + dmas = <&edma 8>, + <&edma 9>; dma-names = "tx", "rx"; }; @@ -910,8 +868,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10 2>, - <&edma 11 2>; + dmas = <&edma 10>, + <&edma 11>; dma-names = "tx", "rx"; }; From 34635b1accb99b3c3ad3b35a210be198701aac7e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 2 Nov 2015 15:21:40 +0200 Subject: [PATCH 77/77] dmaengine: edma: Add dummy driver skeleton for edma3-tptc The eDMA3 TPTC does not need any software configuration, but it is a separate IP block in the SoC. In order the omap hwmod core to be able to handle the TPTC resources correctly in regards of PM we need to have a driver loaded for it. This patch will add a dummy driver skeleton without probe or remove callbacks provided. Signed-off-by: Peter Ujfalusi Reported-by: Olof Johansson Tested-by: Felipe Balbi Signed-off-by: Vinod Koul --- drivers/dma/edma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 31722d436a42..6b03e4e84e6b 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -269,6 +269,11 @@ static const struct of_device_id edma_of_ids[] = { {} }; +static const struct of_device_id edma_tptc_of_ids[] = { + { .compatible = "ti,edma3-tptc", }, + {} +}; + static inline unsigned int edma_read(struct edma_cc *ecc, int offset) { return (unsigned int)__raw_readl(ecc->base + offset); @@ -2399,6 +2404,13 @@ static struct platform_driver edma_driver = { }, }; +static struct platform_driver edma_tptc_driver = { + .driver = { + .name = "edma3-tptc", + .of_match_table = edma_tptc_of_ids, + }, +}; + bool edma_filter_fn(struct dma_chan *chan, void *param) { bool match = false; @@ -2418,6 +2430,12 @@ EXPORT_SYMBOL(edma_filter_fn); static int edma_init(void) { + int ret; + + ret = platform_driver_register(&edma_tptc_driver); + if (ret) + return ret; + return platform_driver_register(&edma_driver); } subsys_initcall(edma_init); @@ -2425,6 +2443,7 @@ subsys_initcall(edma_init); static void __exit edma_exit(void) { platform_driver_unregister(&edma_driver); + platform_driver_unregister(&edma_tptc_driver); } module_exit(edma_exit);