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powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes 

According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is
connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the
device tree to reflect the correct PHY order and port association.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
Camelia Groza 2018-09-20 14:47:01 +03:00 committed by Scott Wood
parent a0e102914a
commit 0400d65501
1 changed files with 2 additions and 2 deletions
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4
arch/powerpc/boot/dts/fsl/t2080rdb.dts
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@ -77,12 +77,12 @@
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy1>;
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy2>;
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};