clk: meson: remove obsolete cpu_clk
meson8b cpu_clk has been replaced by a set of divider and mux clocks. meson_cpu_clk is no longer used and can be removed Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
Neil Armstrong
parent
251b6fd38b
commit
03a6519e9c
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@ -2,7 +2,7 @@
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# Makefile for Meson specific clk
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#
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
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@ -1,178 +0,0 @@
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* CPU clock path:
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*
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* +-[/N]-----|3|
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* MUX2 +--[/3]-+----------|2| MUX1
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* [sys_pll]---|1| |--[/2]------------|1|-|1|
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* | |---+------------------|0| | |----- [a5_clk]
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* +--|0| | |
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* [xtal]---+-------------------------------|0|
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*
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*
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#define MESON_CPU_CLK_CNTL1 0x00
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#define MESON_CPU_CLK_CNTL 0x40
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#define MESON_CPU_CLK_MUX1 BIT(7)
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#define MESON_CPU_CLK_MUX2 BIT(0)
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#define MESON_N_WIDTH 9
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#define MESON_N_SHIFT 20
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#define MESON_SEL_WIDTH 2
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#define MESON_SEL_SHIFT 2
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#include "clkc.h"
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#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw)
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#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb)
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static long meson_clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
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return divider_round_rate(hw, rate, prate, clk_cpu->div_table,
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MESON_N_WIDTH, CLK_DIVIDER_ROUND_CLOSEST);
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}
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static int meson_clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
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unsigned int div, sel, N = 0;
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u32 reg;
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div = DIV_ROUND_UP(parent_rate, rate);
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if (div <= 3) {
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sel = div - 1;
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} else {
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sel = 3;
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N = div / 2;
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}
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reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
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reg = PARM_SET(MESON_N_WIDTH, MESON_N_SHIFT, reg, N);
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writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
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reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
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reg = PARM_SET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg, sel);
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writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
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return 0;
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}
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static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
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unsigned int N, sel;
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unsigned int div = 1;
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u32 reg;
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reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
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N = PARM_GET(MESON_N_WIDTH, MESON_N_SHIFT, reg);
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reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
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sel = PARM_GET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg);
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if (sel < 3)
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div = sel + 1;
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else
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div = 2 * N;
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return parent_rate / div;
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}
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/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
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static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
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struct clk_notifier_data *ndata)
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{
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u32 cpu_clk_cntl;
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/* switch MUX1 to xtal */
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cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off
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+ MESON_CPU_CLK_CNTL);
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cpu_clk_cntl &= ~MESON_CPU_CLK_MUX1;
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writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
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+ MESON_CPU_CLK_CNTL);
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udelay(100);
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/* switch MUX2 to sys-pll */
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cpu_clk_cntl |= MESON_CPU_CLK_MUX2;
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writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
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+ MESON_CPU_CLK_CNTL);
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return 0;
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}
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/* FIXME MUX1 & MUX2 should be struct clk_hw objects */
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static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
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struct clk_notifier_data *ndata)
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{
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u32 cpu_clk_cntl;
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/* switch MUX1 to divisors' output */
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cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off
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+ MESON_CPU_CLK_CNTL);
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cpu_clk_cntl |= MESON_CPU_CLK_MUX1;
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writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
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+ MESON_CPU_CLK_CNTL);
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udelay(100);
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return 0;
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}
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/*
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* This clock notifier is called when the frequency of the of the parent
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* PLL clock is to be changed. We use the xtal input as temporary parent
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* while the PLL frequency is stabilized.
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*/
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int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_nb(nb);
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int ret = 0;
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if (event == PRE_RATE_CHANGE)
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ret = meson_clk_cpu_pre_rate_change(clk_cpu, ndata);
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else if (event == POST_RATE_CHANGE)
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ret = meson_clk_cpu_post_rate_change(clk_cpu, ndata);
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return notifier_from_errno(ret);
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}
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const struct clk_ops meson_clk_cpu_ops = {
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.recalc_rate = meson_clk_cpu_recalc_rate,
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.round_rate = meson_clk_cpu_round_rate,
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.set_rate = meson_clk_cpu_set_rate,
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};
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@ -101,17 +101,6 @@ struct meson_clk_pll_data {
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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struct meson_clk_cpu {
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struct clk_hw hw;
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void __iomem *base;
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u16 reg_off;
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struct notifier_block clk_nb;
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const struct clk_div_table *div_table;
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};
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int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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struct meson_clk_mpll_data {
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struct parm sdm;
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struct parm sdm_en;
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