staging: comedi: pcmmio: cleanup the digital i/o register defines
Redefine the registers used to access the digital i/o so that they are based on the dev->iobase of the board instead of the 'asic_iobase' that is stored in the private data. Remove the then unused 'asic_iobase'. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -133,6 +133,34 @@ Configuration Options:
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#define PCMMIO_AO_RESOURCE_ENA_REG 0x0b
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#define PCMMIO_AO_2ND_DAC_OFFSET 0x04
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/*
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* WinSystems WS16C48
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*
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* Offset Page 0 Page 1 Page 2 Page 3
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* ------ ----------- ----------- ----------- -----------
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* 0x10 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
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* 0x11 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
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* 0x12 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
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* 0x13 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
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* 0x14 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
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* 0x15 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
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* 0x16 INT_PENDING INT_PENDING INT_PENDING INT_PENDING
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* 0x17 Page/Lock Page/Lock Page/Lock Page/Lock
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* 0x18 N/A POL_0 ENAB_0 INT_ID0
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* 0x19 N/A POL_1 ENAB_1 INT_ID1
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* 0x1a N/A POL_2 ENAB_2 INT_ID2
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*/
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#define PCMMIO_PORT_REG(x) (0x10 + (x))
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#define PCMMIO_INT_PENDING_REG 0x16
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#define PCMMIO_PAGE_LOCK_REG 0x17
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#define PCMMIO_LOCK_PORT(x) ((1 << (x)) & 0x3f)
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#define PCMMIO_PAGE(x) (((x) & 0x3) << 6)
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#define PCMMIO_PAGE_MASK PCMUIO_PAGE(3)
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#define PCMMIO_PAGE_POL 1
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#define PCMMIO_PAGE_ENAB 2
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#define PCMMIO_PAGE_INT_ID 3
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#define PCMMIO_PAGE_REG(x) (0x18 + (x))
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/* This stuff is all from pcmuio.c -- it refers to the DIO subdevices only */
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#define CHANS_PER_PORT 8
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#define PORTS_PER_ASIC 6
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@ -149,51 +177,9 @@ Configuration Options:
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#define ASIC_IOSIZE (0x0B)
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#define PCMMIO48_IOSIZE ASIC_IOSIZE
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/* Some offsets - these are all in the 16byte IO memory offset from
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the base address. Note that there is a paging scheme to swap out
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offsets 0x8-0xA using the PAGELOCK register. See the table below.
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Register(s) Pages R/W? Description
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--------------------------------------------------------------
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REG_PORTx All R/W Read/Write/Configure IO
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REG_INT_PENDING All ReadOnly Quickly see which INT_IDx has int.
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REG_PAGELOCK All WriteOnly Select a page
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REG_POLx Pg. 1 only WriteOnly Select edge-detection polarity
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REG_ENABx Pg. 2 only WriteOnly Enable/Disable edge-detect. int.
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REG_INT_IDx Pg. 3 only R/W See which ports/bits have ints.
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*/
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#define REG_PORT0 0x0
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#define REG_PORT1 0x1
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#define REG_PORT2 0x2
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#define REG_PORT3 0x3
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#define REG_PORT4 0x4
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#define REG_PORT5 0x5
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#define REG_INT_PENDING 0x6
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#define REG_PAGELOCK 0x7 /*
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* page selector register, upper 2 bits select
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* a page and bits 0-5 are used to 'lock down'
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* a particular port above to make it readonly.
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*/
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#define REG_POL0 0x8
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#define REG_POL1 0x9
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#define REG_POL2 0xA
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#define REG_ENAB0 0x8
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#define REG_ENAB1 0x9
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#define REG_ENAB2 0xA
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#define REG_INT_ID0 0x8
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#define REG_INT_ID1 0x9
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#define REG_INT_ID2 0xA
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#define NUM_PAGED_REGS 3
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#define NUM_PAGES 4
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#define FIRST_PAGED_REG 0x8
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#define REG_PAGE_BITOFFSET 6
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#define REG_LOCK_BITOFFSET 0
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#define REG_PAGE_MASK (~((0x1<<REG_PAGE_BITOFFSET)-1))
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#define REG_LOCK_MASK (~(REG_PAGE_MASK))
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#define PAGE_POL 1
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#define PAGE_ENAB 2
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#define PAGE_INT_ID 3
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static const struct comedi_lrange pcmmio_ai_ranges = {
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4, {
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@ -268,7 +254,6 @@ struct pcmmio_subdev_private {
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* feel free to suggest moving the variable to the struct comedi_device struct.
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*/
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struct pcmmio_private {
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unsigned long asic_iobase;
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spinlock_t spinlock;
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struct pcmmio_subdev_private *sprivs;
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@ -365,31 +350,26 @@ static int pcmmio_dio_insn_config(struct comedi_device *dev,
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static void switch_page(struct comedi_device *dev, int page)
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{
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struct pcmmio_private *devpriv = dev->private;
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outb(page << REG_PAGE_BITOFFSET, devpriv->asic_iobase + REG_PAGELOCK);
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outb(PCMMIO_PAGE(page), dev->iobase + PCMMIO_PAGE_LOCK_REG);
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}
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static void pcmmio_reset(struct comedi_device *dev)
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{
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struct pcmmio_private *devpriv = dev->private;
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unsigned long baseaddr = devpriv->asic_iobase;
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int port, page;
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switch_page(dev, 0); /* switch back to page 0 */
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/* first, clear all the DIO port bits */
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for (port = 0; port < PORTS_PER_ASIC; ++port)
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outb(0, baseaddr + REG_PORT0 + port);
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outb(0, dev->iobase + PCMMIO_PORT_REG(port));
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/* Next, clear all the paged registers for each page */
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for (page = 1; page < NUM_PAGES; ++page) {
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int reg;
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/* now clear all the paged registers */
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switch_page(dev, page);
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for (reg = FIRST_PAGED_REG;
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reg < FIRST_PAGED_REG + NUM_PAGED_REGS; ++reg)
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outb(0, baseaddr + reg);
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for (reg = 0; reg < NUM_PAGED_REGS; ++reg)
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outb(0, dev->iobase + PCMMIO_PAGE_REG(reg));
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}
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/* switch back to default page 0 */
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@ -399,7 +379,6 @@ static void pcmmio_reset(struct comedi_device *dev)
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static void pcmmio_stop_intr(struct comedi_device *dev,
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struct comedi_subdevice *s)
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{
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struct pcmmio_private *devpriv = dev->private;
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int nports, firstport, asic, port;
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asic = subpriv->dio.intr.asic;
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@ -411,10 +390,10 @@ static void pcmmio_stop_intr(struct comedi_device *dev,
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s->async->inttrig = NULL;
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nports = subpriv->dio.intr.num_asic_chans / CHANS_PER_PORT;
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firstport = subpriv->dio.intr.asic_chan / CHANS_PER_PORT;
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switch_page(dev, PAGE_ENAB);
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switch_page(dev, PCMMIO_PAGE_ENAB);
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for (port = firstport; port < firstport + nports; ++port) {
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/* disable all intrs for this subdev.. */
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outb(0, devpriv->asic_iobase + REG_ENAB0 + port);
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outb(0, dev->iobase + PCMMIO_PAGE_REG(port));
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}
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}
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@ -429,13 +408,13 @@ static irqreturn_t interrupt_pcmmio(int irq, void *d)
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if (irq == dev->irq) {
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unsigned long flags;
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unsigned triggered = 0;
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unsigned long iobase = devpriv->asic_iobase;
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/* it is an interrupt for ASIC #asic */
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unsigned char int_pend;
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spin_lock_irqsave(&devpriv->spinlock, flags);
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int_pend = inb(iobase + REG_INT_PENDING) & 0x07;
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int_pend = inb(dev->iobase + PCMMIO_INT_PENDING_REG);
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int_pend &= 0x07;
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if (int_pend) {
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int port;
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@ -444,19 +423,18 @@ static irqreturn_t interrupt_pcmmio(int irq, void *d)
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if (int_pend & (0x1 << port)) {
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unsigned char
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io_lines_with_edges = 0;
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switch_page(dev, PAGE_INT_ID);
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switch_page(dev, PCMMIO_PAGE_INT_ID);
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io_lines_with_edges =
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inb(iobase +
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REG_INT_ID0 + port);
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inb(dev->iobase +
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PCMMIO_PAGE_REG(port));
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if (io_lines_with_edges)
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/*
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* clear pending
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* interrupt
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*/
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outb(0, iobase +
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REG_INT_ID0 +
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port);
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outb(0, dev->iobase +
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PCMMIO_PAGE_REG(port));
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triggered |=
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io_lines_with_edges <<
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@ -578,8 +556,6 @@ static irqreturn_t interrupt_pcmmio(int irq, void *d)
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static int pcmmio_start_intr(struct comedi_device *dev,
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struct comedi_subdevice *s)
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{
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struct pcmmio_private *devpriv = dev->private;
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if (!subpriv->dio.intr.continuous && subpriv->dio.intr.stop_count == 0) {
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/* An empty acquisition! */
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s->async->events |= COMEDI_CB_EOA;
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@ -628,7 +604,7 @@ static int pcmmio_start_intr(struct comedi_device *dev,
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/* done, we told the board what irq to use */
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}
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switch_page(dev, PAGE_ENAB);
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switch_page(dev, PCMMIO_PAGE_ENAB);
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for (port = firstport; port < firstport + nports; ++port) {
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unsigned enab =
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bits >> (subpriv->dio.intr.first_chan + (port -
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@ -637,9 +613,9 @@ static int pcmmio_start_intr(struct comedi_device *dev,
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pol_bits >> (subpriv->dio.intr.first_chan +
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(port - firstport) * 8) & 0xff;
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/* set enab intrs for this subdev.. */
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outb(enab, devpriv->asic_iobase + REG_ENAB0 + port);
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switch_page(dev, PAGE_POL);
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outb(pol, devpriv->asic_iobase + REG_ENAB0 + port);
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outb(enab, dev->iobase + PCMMIO_PAGE_REG(port));
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switch_page(dev, PCMMIO_PAGE_POL);
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outb(pol, dev->iobase + PCMMIO_PAGE_REG(port));
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}
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}
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return 0;
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@ -955,7 +931,6 @@ static int pcmmio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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if (!devpriv)
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return -ENOMEM;
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devpriv->asic_iobase = dev->iobase + 16;
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spin_lock_init(&devpriv->spinlock);
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chans_left = CHANS_PER_ASIC * 1;
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@ -1029,7 +1004,8 @@ static int pcmmio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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++asic;
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thisasic_chanct = 0;
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}
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subpriv->iobases[byte_no] = devpriv->asic_iobase + port;
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subpriv->iobases[byte_no] = dev->iobase +
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PCMMIO_PORT_REG(port);
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if (thisasic_chanct <
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CHANS_PER_PORT * INTR_PORTS_PER_ASIC
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