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serial: imx: rename variables to match the register names 

Now the variable holding the value of register USR1 is called usr1
instead of sts which is more straight forward. The same is also done for
sts2 which is called usr2 now.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Uwe Kleine-König 2018-02-18 22:02:43 +01:00 committed by Greg Kroah-Hartman
parent 135ccb0129
commit 0399fd6147
1 changed files with 10 additions and 11 deletions
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21
drivers/tty/serial/imx.c
View File

@ -758,27 +758,26 @@ static void imx_mctrl_check(struct imx_port *sport)
static irqreturn_t imx_int(int irq, void *dev_id)
{
struct imx_port *sport = dev_id;
unsigned int sts;
unsigned int sts2;
unsigned int usr1, usr2;
irqreturn_t ret = IRQ_NONE;
sts = readl(sport->port.membase + USR1);
sts2 = readl(sport->port.membase + USR2);
usr1 = readl(sport->port.membase + USR1);
usr2 = readl(sport->port.membase + USR2);
if (!sport->dma_is_enabled && (sts & (USR1_RRDY | USR1_AGTIM))) {
if (!sport->dma_is_enabled && (usr1 & (USR1_RRDY | USR1_AGTIM))) {
imx_rxint(irq, dev_id);
ret = IRQ_HANDLED;
}
if ((sts & USR1_TRDY &&
if ((usr1 & USR1_TRDY &&
readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
(sts2 & USR2_TXDC &&
(usr2 & USR2_TXDC &&
readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
imx_txint(irq, dev_id);
ret = IRQ_HANDLED;
}
if (sts & USR1_DTRD) {
if (usr1 & USR1_DTRD) {
unsigned long flags;
writel(USR1_DTRD, sport->port.membase + USR1);
@ -790,17 +789,17 @@ static irqreturn_t imx_int(int irq, void *dev_id)
ret = IRQ_HANDLED;
}
if (sts & USR1_RTSD) {
if (usr1 & USR1_RTSD) {
imx_rtsint(irq, dev_id);
ret = IRQ_HANDLED;
}
if (sts & USR1_AWAKE) {
if (usr1 & USR1_AWAKE) {
writel(USR1_AWAKE, sport->port.membase + USR1);
ret = IRQ_HANDLED;
}
if (sts2 & USR2_ORE) {
if (usr2 & USR2_ORE) {
sport->port.icount.overrun++;
writel(USR2_ORE, sport->port.membase + USR2);
ret = IRQ_HANDLED;