dt-bindings: gpio: tegra: Add Tegra186 support
Adds device tree bindings for the GPIO and AON controllers found on the Tegra186 SoC. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXI3wAAAoJEN0jrNd/PrOhV2gQAJBrcTZ762hsnxvsbprE9cfc th8hq750wVhqT7rJLLHcPcUMNAnhZyg69DEEKmhZGMCUfkTfWOMBcP0Iga4uP84G RilK4A7srs/knUklK07XLBS1vhlnaikyUhpsHv0XTstsAsbRoLX1sBdRjWxf9uOM 8G0rptLsI6+BfTVZISWiXgZ9uuEkavFaPb8xonjtG1KVSq8S8x8p509hUZ6m5QOC lTj2+Pt6MYwtJ1BBcdOtYEJGClmdjYGWfo8spQDQZFTywDU20TCIkdEe8QZVeoP1 WA/7Rgpn3VJJiSyUzBVcjRzWqjwpUa44yeGOqFegvQrOt+fK0Bh9KYaE9RhbAhMI la4T5n401dgRb2VWzLXDCGIyMYcu64XYG537IxqoSuG8hAqhQt+FrkTo2wMotpxh ErHmIIFTcivJQ2kEBEMd/QY8V+ey+99rFmrqaExLrHV+vmP+TEuw58GyCuNDSQ1T xEvUwBZYFDpfm33DPm3IHJkYapAJ/sW+VFKBNT+Leim3tm8HqKap0OoP7aarCRYI IjfkFd0NSFQ/Sxa3sGzbK4zS2MlfPQ9svAoy+YNDYZWmB7mwPaG4+/pOEygQXNdg CkJxopNpdTpdmdmJE+Q2iGQc7w1fiUnKMlsKl5KHIO6Q9lWWp3ZDEYWxYvbpRMBB VwgHyRoet1oKU/yjkOLA =6MhO -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.7-gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 Merge "dt-bindings: gpio: tegra: Add Tegra186 support" from Thierry Reding: Adds device tree bindings for the GPIO and AON controllers found on the Tegra186 SoC. * tag 'tegra-for-4.7-gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Add DT binding for Tegra186 GPIO controllers ARM: tegra: Fix naming in GPIO DT binding header
This commit is contained in:
Arnd Bergmann
commit
0378fe89d8
|
|
@ -0,0 +1,161 @@
|
|||
NVIDIA Tegra186 GPIO controllers
|
||||
|
||||
Tegra186 contains two GPIO controllers; a main controller and an "AON"
|
||||
controller. This binding document applies to both controllers. The register
|
||||
layouts for the controllers share many similarities, but also some significant
|
||||
differences. Hence, this document describes closely related but different
|
||||
bindings and compatible values.
|
||||
|
||||
The Tegra186 GPIO controller allows software to set the IO direction of, and
|
||||
read/write the value of, numerous GPIO signals. Routing of GPIO signals to
|
||||
package balls is under the control of a separate pin controller HW block. Two
|
||||
major sets of registers exist:
|
||||
|
||||
a) Security registers, which allow configuration of allowed access to the GPIO
|
||||
register set. These registers exist in a single contiguous block of physical
|
||||
address space. The size of this block, and the security features available,
|
||||
varies between the different GPIO controllers.
|
||||
|
||||
Access to this set of registers is not necessary in all circumstances. Code
|
||||
that wishes to configure access to the GPIO registers needs access to these
|
||||
registers to do so. Code which simply wishes to read or write GPIO data does not
|
||||
need access to these registers.
|
||||
|
||||
b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
|
||||
controllers, these registers are exposed via multiple "physical aliases" in
|
||||
address space, each of which access the same underlying state. See the hardware
|
||||
documentation for rationale. Any particular GPIO client is expected to access
|
||||
just one of these physical aliases.
|
||||
|
||||
Tegra HW documentation describes a unified naming convention for all GPIOs
|
||||
implemented by the SoC. Each GPIO is assigned to a port, and a port may control
|
||||
a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
|
||||
name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
|
||||
or GPIO_PCC3.
|
||||
|
||||
The number of ports implemented by each GPIO controller varies. The number of
|
||||
implemented GPIOs within each port varies. GPIO registers within a controller
|
||||
are grouped and laid out according to the port they affect.
|
||||
|
||||
The mapping from port name to the GPIO controller that implements that port, and
|
||||
the mapping from port name to register offset within a controller, are both
|
||||
extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
|
||||
describes the port-level mapping. In that file, the naming convention for ports
|
||||
matches the HW documentation. The values chosen for the names are alphabetically
|
||||
sorted within a particular controller. Drivers need to map between the DT GPIO
|
||||
IDs and HW register offsets using a lookup table.
|
||||
|
||||
Each GPIO controller can generate a number of interrupt signals. Each signal
|
||||
represents the aggregate status for all GPIOs within a set of ports. Thus, the
|
||||
number of interrupt signals generated by a controller varies as a rough function
|
||||
of the number of ports it implements. Note that the HW documentation refers to
|
||||
both the overall controller HW module and the sets-of-ports as "controllers".
|
||||
|
||||
Each GPIO controller in fact generates multiple interrupts signals for each set
|
||||
of ports. Each GPIO may be configured to feed into a specific one of the
|
||||
interrupt signals generated by a set-of-ports. The intent is for each generated
|
||||
signal to be routed to a different CPU, thus allowing different CPUs to each
|
||||
handle subsets of the interrupts within a port. The status of each of these
|
||||
per-port-set signals is reported via a separate register. Thus, a driver needs
|
||||
to know which status register to observe. This binding currently defines no
|
||||
configuration mechanism for this. By default, drivers should use register
|
||||
GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
|
||||
define a property to configure this.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Array of strings.
|
||||
One of:
|
||||
- "nvidia,tegra186-gpio".
|
||||
- "nvidia,tegra186-gpio-aon".
|
||||
- reg-names
|
||||
Array of strings.
|
||||
Contains a list of names for the register spaces described by the reg
|
||||
property. May contain the following entries, in any order:
|
||||
- "gpio": Mandatory. GPIO control registers. This may cover either:
|
||||
a) The single physical alias that this OS should use.
|
||||
b) All physical aliases that exist in the controller. This is
|
||||
appropriate when the OS is responsible for managing assignment of
|
||||
the physical aliases.
|
||||
- "security": Optional. Security configuration registers.
|
||||
Users of this binding MUST look up entries in the reg property by name,
|
||||
using this reg-names property to do so.
|
||||
- reg
|
||||
Array of (physical base address, length) tuples.
|
||||
Must contain one entry per entry in the reg-names property, in a matching
|
||||
order.
|
||||
- interrupts
|
||||
Array of interrupt specifiers.
|
||||
The interrupt outputs from the HW block, one per set of ports, in the
|
||||
order the HW manual describes them. The number of entries required varies
|
||||
depending on compatible value:
|
||||
- "nvidia,tegra186-gpio": 6 entries.
|
||||
- "nvidia,tegra186-gpio-aon": 1 entry.
|
||||
- gpio-controller
|
||||
Boolean.
|
||||
Marks the device node as a GPIO controller/provider.
|
||||
- #gpio-cells
|
||||
Single-cell integer.
|
||||
Must be <2>.
|
||||
Indicates how many cells are used in a consumer's GPIO specifier.
|
||||
In the specifier:
|
||||
- The first cell is the pin number.
|
||||
See <dt-bindings/gpio/tegra186-gpio.h>.
|
||||
- The second cell contains flags:
|
||||
- Bit 0 specifies polarity
|
||||
- 0: Active-high (normal).
|
||||
- 1: Active-low (inverted).
|
||||
- interrupt-controller
|
||||
Boolean.
|
||||
Marks the device node as an interrupt controller/provider.
|
||||
- #interrupt-cells
|
||||
Single-cell integer.
|
||||
Must be <2>.
|
||||
Indicates how many cells are used in a consumer's interrupt specifier.
|
||||
In the specifier:
|
||||
- The first cell is the GPIO number.
|
||||
See <dt-bindings/gpio/tegra186-gpio.h>.
|
||||
- The second cell is contains flags:
|
||||
- Bits [3:0] indicate trigger type and level:
|
||||
- 1: Low-to-high edge triggered.
|
||||
- 2: High-to-low edge triggered.
|
||||
- 4: Active high level-sensitive.
|
||||
- 8: Active low level-sensitive.
|
||||
Valid combinations are 1, 2, 3, 4, 8.
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
gpio@2200000 {
|
||||
compatible = "nvidia,tegra186-gpio";
|
||||
reg-names = "security", "gpio";
|
||||
reg =
|
||||
<0x0 0x2200000 0x0 0x10000>,
|
||||
<0x0 0x2210000 0x0 0x10000>;
|
||||
interrupts =
|
||||
<0 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio@c2f0000 {
|
||||
compatible = "nvidia,tegra186-gpio-aon";
|
||||
reg-names = "security", "gpio";
|
||||
reg =
|
||||
<0x0 0xc2f0000 0x0 0x1000>,
|
||||
<0x0 0xc2f1000 0x0 0x1000>;
|
||||
interrupts =
|
||||
<0 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -12,40 +12,40 @@
|
|||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#define TEGRA_GPIO_BANK_ID_A 0
|
||||
#define TEGRA_GPIO_BANK_ID_B 1
|
||||
#define TEGRA_GPIO_BANK_ID_C 2
|
||||
#define TEGRA_GPIO_BANK_ID_D 3
|
||||
#define TEGRA_GPIO_BANK_ID_E 4
|
||||
#define TEGRA_GPIO_BANK_ID_F 5
|
||||
#define TEGRA_GPIO_BANK_ID_G 6
|
||||
#define TEGRA_GPIO_BANK_ID_H 7
|
||||
#define TEGRA_GPIO_BANK_ID_I 8
|
||||
#define TEGRA_GPIO_BANK_ID_J 9
|
||||
#define TEGRA_GPIO_BANK_ID_K 10
|
||||
#define TEGRA_GPIO_BANK_ID_L 11
|
||||
#define TEGRA_GPIO_BANK_ID_M 12
|
||||
#define TEGRA_GPIO_BANK_ID_N 13
|
||||
#define TEGRA_GPIO_BANK_ID_O 14
|
||||
#define TEGRA_GPIO_BANK_ID_P 15
|
||||
#define TEGRA_GPIO_BANK_ID_Q 16
|
||||
#define TEGRA_GPIO_BANK_ID_R 17
|
||||
#define TEGRA_GPIO_BANK_ID_S 18
|
||||
#define TEGRA_GPIO_BANK_ID_T 19
|
||||
#define TEGRA_GPIO_BANK_ID_U 20
|
||||
#define TEGRA_GPIO_BANK_ID_V 21
|
||||
#define TEGRA_GPIO_BANK_ID_W 22
|
||||
#define TEGRA_GPIO_BANK_ID_X 23
|
||||
#define TEGRA_GPIO_BANK_ID_Y 24
|
||||
#define TEGRA_GPIO_BANK_ID_Z 25
|
||||
#define TEGRA_GPIO_BANK_ID_AA 26
|
||||
#define TEGRA_GPIO_BANK_ID_BB 27
|
||||
#define TEGRA_GPIO_BANK_ID_CC 28
|
||||
#define TEGRA_GPIO_BANK_ID_DD 29
|
||||
#define TEGRA_GPIO_BANK_ID_EE 30
|
||||
#define TEGRA_GPIO_BANK_ID_FF 31
|
||||
#define TEGRA_GPIO_PORT_A 0
|
||||
#define TEGRA_GPIO_PORT_B 1
|
||||
#define TEGRA_GPIO_PORT_C 2
|
||||
#define TEGRA_GPIO_PORT_D 3
|
||||
#define TEGRA_GPIO_PORT_E 4
|
||||
#define TEGRA_GPIO_PORT_F 5
|
||||
#define TEGRA_GPIO_PORT_G 6
|
||||
#define TEGRA_GPIO_PORT_H 7
|
||||
#define TEGRA_GPIO_PORT_I 8
|
||||
#define TEGRA_GPIO_PORT_J 9
|
||||
#define TEGRA_GPIO_PORT_K 10
|
||||
#define TEGRA_GPIO_PORT_L 11
|
||||
#define TEGRA_GPIO_PORT_M 12
|
||||
#define TEGRA_GPIO_PORT_N 13
|
||||
#define TEGRA_GPIO_PORT_O 14
|
||||
#define TEGRA_GPIO_PORT_P 15
|
||||
#define TEGRA_GPIO_PORT_Q 16
|
||||
#define TEGRA_GPIO_PORT_R 17
|
||||
#define TEGRA_GPIO_PORT_S 18
|
||||
#define TEGRA_GPIO_PORT_T 19
|
||||
#define TEGRA_GPIO_PORT_U 20
|
||||
#define TEGRA_GPIO_PORT_V 21
|
||||
#define TEGRA_GPIO_PORT_W 22
|
||||
#define TEGRA_GPIO_PORT_X 23
|
||||
#define TEGRA_GPIO_PORT_Y 24
|
||||
#define TEGRA_GPIO_PORT_Z 25
|
||||
#define TEGRA_GPIO_PORT_AA 26
|
||||
#define TEGRA_GPIO_PORT_BB 27
|
||||
#define TEGRA_GPIO_PORT_CC 28
|
||||
#define TEGRA_GPIO_PORT_DD 29
|
||||
#define TEGRA_GPIO_PORT_EE 30
|
||||
#define TEGRA_GPIO_PORT_FF 31
|
||||
|
||||
#define TEGRA_GPIO(bank, offset) \
|
||||
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
|
||||
#define TEGRA_GPIO(port, offset) \
|
||||
((TEGRA_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This header provides constants for binding nvidia,tegra186-gpio*.
|
||||
*
|
||||
* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
|
||||
* provide names for this.
|
||||
*
|
||||
* The second cell contains standard flag values specified in gpio.h.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
|
||||
#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/* GPIOs implemented by main GPIO controller */
|
||||
#define TEGRA_MAIN_GPIO_PORT_A 0
|
||||
#define TEGRA_MAIN_GPIO_PORT_B 1
|
||||
#define TEGRA_MAIN_GPIO_PORT_C 2
|
||||
#define TEGRA_MAIN_GPIO_PORT_D 3
|
||||
#define TEGRA_MAIN_GPIO_PORT_E 4
|
||||
#define TEGRA_MAIN_GPIO_PORT_F 5
|
||||
#define TEGRA_MAIN_GPIO_PORT_G 6
|
||||
#define TEGRA_MAIN_GPIO_PORT_H 7
|
||||
#define TEGRA_MAIN_GPIO_PORT_I 8
|
||||
#define TEGRA_MAIN_GPIO_PORT_J 9
|
||||
#define TEGRA_MAIN_GPIO_PORT_K 10
|
||||
#define TEGRA_MAIN_GPIO_PORT_L 11
|
||||
#define TEGRA_MAIN_GPIO_PORT_M 12
|
||||
#define TEGRA_MAIN_GPIO_PORT_N 13
|
||||
#define TEGRA_MAIN_GPIO_PORT_O 14
|
||||
#define TEGRA_MAIN_GPIO_PORT_P 15
|
||||
#define TEGRA_MAIN_GPIO_PORT_Q 16
|
||||
#define TEGRA_MAIN_GPIO_PORT_R 17
|
||||
#define TEGRA_MAIN_GPIO_PORT_T 18
|
||||
#define TEGRA_MAIN_GPIO_PORT_X 19
|
||||
#define TEGRA_MAIN_GPIO_PORT_Y 20
|
||||
#define TEGRA_MAIN_GPIO_PORT_BB 21
|
||||
#define TEGRA_MAIN_GPIO_PORT_CC 22
|
||||
|
||||
#define TEGRA_MAIN_GPIO(port, offset) \
|
||||
((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
/* GPIOs implemented by AON GPIO controller */
|
||||
#define TEGRA_AON_GPIO_PORT_S 0
|
||||
#define TEGRA_AON_GPIO_PORT_U 1
|
||||
#define TEGRA_AON_GPIO_PORT_V 2
|
||||
#define TEGRA_AON_GPIO_PORT_W 3
|
||||
#define TEGRA_AON_GPIO_PORT_Z 4
|
||||
#define TEGRA_AON_GPIO_PORT_AA 5
|
||||
#define TEGRA_AON_GPIO_PORT_EE 6
|
||||
#define TEGRA_AON_GPIO_PORT_FF 7
|
||||
|
||||
#define TEGRA_AON_GPIO(port, offset) \
|
||||
((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue