ARM: dts: am335x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Cc: Teresa Remmet <t.remmet@phytec.de> Cc: Ilya Ledvich <ilya@compulab.co.il> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Rostislav Lisovy <lisovy@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -236,7 +236,11 @@
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status = "okay";
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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ti,nand-xfer-type = "polled";
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@ -7,6 +7,7 @@
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* published by the Free Software Foundation.
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*/
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Grinn AM335x ChiliSOM";
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@ -218,7 +219,11 @@
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "CompuLab CM-T335";
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@ -302,7 +303,11 @@ status = "okay";
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -519,7 +519,11 @@
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pinctrl-0 = <&nandflash_pins_s0>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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@ -11,6 +11,7 @@
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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cpus {
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@ -129,7 +130,11 @@
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-width = <1>;
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@ -8,6 +8,7 @@
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*/
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Phytec AM335x phyCORE";
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@ -165,7 +166,11 @@
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pinctrl-0 = <&nandflash_pins>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
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nandflash: nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-nand = "true";
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@ -865,6 +865,8 @@
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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