Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/tclib into base
This commit is contained in:
Haavard Skinnemoen
commit
03414e57ad
|
|
@ -1,3 +1,4 @@
|
|||
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
|
||||
obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
|
||||
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
|
||||
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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||||
|
|
|
|||
|
|
@ -0,0 +1,302 @@
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|||
#include <linux/init.h>
|
||||
#include <linux/clocksource.h>
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||||
#include <linux/clockchips.h>
|
||||
#include <linux/interrupt.h>
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#include <linux/irq.h>
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||||
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#include <linux/clk.h>
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#include <linux/err.h>
|
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#include <linux/ioport.h>
|
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#include <linux/io.h>
|
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#include <linux/platform_device.h>
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#include <linux/atmel_tc.h>
|
||||
|
||||
|
||||
/*
|
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* We're configured to use a specific TC block, one that's not hooked
|
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* up to external hardware, to provide a time solution:
|
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*
|
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* - Two channels combine to create a free-running 32 bit counter
|
||||
* with a base rate of 5+ MHz, packaged as a clocksource (with
|
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* resolution better than 200 nsec).
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*
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* - The third channel may be used to provide a 16-bit clockevent
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* source, used in either periodic or oneshot mode. This runs
|
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* at 32 KiHZ, and can handle delays of up to two seconds.
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*
|
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* A boot clocksource and clockevent source are also currently needed,
|
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* unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
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* this code can be used when init_timers() is called, well before most
|
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* devices are set up. (Some low end AT91 parts, which can run uClinux,
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||||
* have only the timers in one TC block... they currently don't support
|
||||
* the tclib code, because of that initialization issue.)
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*
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||||
* REVISIT behavior during system suspend states... we should disable
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* all clocks and save the power. Easily done for clockevent devices,
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* but clocksources won't necessarily get the needed notifications.
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* For deeper system sleep states, this will be mandatory...
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||||
*/
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static void __iomem *tcaddr;
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static cycle_t tc_get_cycles(void)
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{
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unsigned long flags;
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u32 lower, upper;
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|
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raw_local_irq_save(flags);
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do {
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upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
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lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
|
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} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
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|
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raw_local_irq_restore(flags);
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return (upper << 16) | lower;
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}
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static struct clocksource clksrc = {
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.name = "tcb_clksrc",
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.rating = 200,
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.read = tc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 18,
|
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#ifdef CONFIG_GENERIC_CLOCKEVENTS
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struct tc_clkevt_device {
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struct clock_event_device clkevt;
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struct clk *clk;
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void __iomem *regs;
|
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};
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static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
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{
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return container_of(clkevt, struct tc_clkevt_device, clkevt);
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}
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|
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/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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* because using one of the divided clocks would usually mean the
|
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* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
|
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*
|
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* A divided clock could be good for high resolution timers, since
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* 30.5 usec resolution can seem "low".
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*/
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static u32 timer_clock;
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static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
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{
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struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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void __iomem *regs = tcd->regs;
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|
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if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
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|| tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
|
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__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
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__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
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clk_disable(tcd->clk);
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}
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|
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switch (m) {
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|
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/* By not making the gentime core emulate periodic mode on top
|
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* of oneshot, we get lower overhead and improved accuracy.
|
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*/
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case CLOCK_EVT_MODE_PERIODIC:
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clk_enable(tcd->clk);
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|
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/* slow clock, count up to RC, then irq and restart */
|
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__raw_writel(timer_clock
|
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| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
|
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regs + ATMEL_TC_REG(2, CMR));
|
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__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
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|
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/* Enable clock and interrupts on RC compare */
|
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__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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|
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/* go go gadget! */
|
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__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
|
||||
regs + ATMEL_TC_REG(2, CCR));
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
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clk_enable(tcd->clk);
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|
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/* slow clock, count up to RC, then irq and stop */
|
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__raw_writel(timer_clock | ATMEL_TC_CPCSTOP
|
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| ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
|
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regs + ATMEL_TC_REG(2, CMR));
|
||||
__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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||||
|
||||
/* set_next_event() configures and starts the timer */
|
||||
break;
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||||
|
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default:
|
||||
break;
|
||||
}
|
||||
}
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|
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static int tc_next_event(unsigned long delta, struct clock_event_device *d)
|
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{
|
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__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
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|
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/* go go gadget! */
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__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
|
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tcaddr + ATMEL_TC_REG(2, CCR));
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return 0;
|
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}
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|
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static struct tc_clkevt_device clkevt = {
|
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.clkevt = {
|
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.name = "tc_clkevt",
|
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.features = CLOCK_EVT_FEAT_PERIODIC
|
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| CLOCK_EVT_FEAT_ONESHOT,
|
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.shift = 32,
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/* Should be lower than at91rm9200's system timer */
|
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.rating = 125,
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.cpumask = CPU_MASK_CPU0,
|
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.set_next_event = tc_next_event,
|
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.set_mode = tc_mode,
|
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},
|
||||
};
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|
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static irqreturn_t ch2_irq(int irq, void *handle)
|
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{
|
||||
struct tc_clkevt_device *dev = handle;
|
||||
unsigned int sr;
|
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|
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sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
|
||||
if (sr & ATMEL_TC_CPCS) {
|
||||
dev->clkevt.event_handler(&dev->clkevt);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static struct irqaction tc_irqaction = {
|
||||
.name = "tc_clkevt",
|
||||
.flags = IRQF_TIMER | IRQF_DISABLED,
|
||||
.handler = ch2_irq,
|
||||
};
|
||||
|
||||
static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
|
||||
{
|
||||
struct clk *t2_clk = tc->clk[2];
|
||||
int irq = tc->irq[2];
|
||||
|
||||
clkevt.regs = tc->regs;
|
||||
clkevt.clk = t2_clk;
|
||||
tc_irqaction.dev_id = &clkevt;
|
||||
|
||||
timer_clock = clk32k_divisor_idx;
|
||||
|
||||
clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
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||||
clkevt.clkevt.max_delta_ns
|
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= clockevent_delta2ns(0xffff, &clkevt.clkevt);
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clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
|
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|
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setup_irq(irq, &tc_irqaction);
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|
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clockevents_register_device(&clkevt.clkevt);
|
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}
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|
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#else /* !CONFIG_GENERIC_CLOCKEVENTS */
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|
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static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
|
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{
|
||||
/* NOTHING */
|
||||
}
|
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|
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#endif
|
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|
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static int __init tcb_clksrc_init(void)
|
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{
|
||||
static char bootinfo[] __initdata
|
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= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
|
||||
|
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struct platform_device *pdev;
|
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struct atmel_tc *tc;
|
||||
struct clk *t0_clk;
|
||||
u32 rate, divided_rate = 0;
|
||||
int best_divisor_idx = -1;
|
||||
int clk32k_divisor_idx = -1;
|
||||
int i;
|
||||
|
||||
tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
|
||||
if (!tc) {
|
||||
pr_debug("can't alloc TC for clocksource\n");
|
||||
return -ENODEV;
|
||||
}
|
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tcaddr = tc->regs;
|
||||
pdev = tc->pdev;
|
||||
|
||||
t0_clk = tc->clk[0];
|
||||
clk_enable(t0_clk);
|
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|
||||
/* How fast will we be counting? Pick something over 5 MHz. */
|
||||
rate = (u32) clk_get_rate(t0_clk);
|
||||
for (i = 0; i < 5; i++) {
|
||||
unsigned divisor = atmel_tc_divisors[i];
|
||||
unsigned tmp;
|
||||
|
||||
/* remember 32 KiHz clock for later */
|
||||
if (!divisor) {
|
||||
clk32k_divisor_idx = i;
|
||||
continue;
|
||||
}
|
||||
|
||||
tmp = rate / divisor;
|
||||
pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
|
||||
if (best_divisor_idx > 0) {
|
||||
if (tmp < 5 * 1000 * 1000)
|
||||
continue;
|
||||
}
|
||||
divided_rate = tmp;
|
||||
best_divisor_idx = i;
|
||||
}
|
||||
|
||||
clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
|
||||
|
||||
printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
|
||||
divided_rate / 1000000,
|
||||
((divided_rate + 500000) % 1000000) / 1000);
|
||||
|
||||
/* tclib will give us three clocks no matter what the
|
||||
* underlying platform supports.
|
||||
*/
|
||||
clk_enable(tc->clk[1]);
|
||||
|
||||
/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
|
||||
__raw_writel(best_divisor_idx /* likely divide-by-8 */
|
||||
| ATMEL_TC_WAVE
|
||||
| ATMEL_TC_WAVESEL_UP /* free-run */
|
||||
| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
|
||||
| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
|
||||
tcaddr + ATMEL_TC_REG(0, CMR));
|
||||
__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
|
||||
__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
|
||||
__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
|
||||
__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
|
||||
|
||||
/* channel 1: waveform mode, input TIOA0 */
|
||||
__raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
|
||||
| ATMEL_TC_WAVE
|
||||
| ATMEL_TC_WAVESEL_UP, /* free-run */
|
||||
tcaddr + ATMEL_TC_REG(1, CMR));
|
||||
__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
|
||||
__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
|
||||
|
||||
/* chain channel 0 to channel 1, then reset all the timers */
|
||||
__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
|
||||
__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
|
||||
|
||||
/* and away we go! */
|
||||
clocksource_register(&clksrc);
|
||||
|
||||
/* channel 2: periodic and oneshot timer support */
|
||||
setup_clkevents(tc, clk32k_divisor_idx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(tcb_clksrc_init);
|
||||
|
|
@ -22,6 +22,39 @@ config ATMEL_PWM
|
|||
purposes including software controlled power-efficent backlights
|
||||
on LCD displays, motor control, and waveform generation.
|
||||
|
||||
config ATMEL_TCLIB
|
||||
bool "Atmel AT32/AT91 Timer/Counter Library"
|
||||
depends on (AVR32 || ARCH_AT91)
|
||||
help
|
||||
Select this if you want a library to allocate the Timer/Counter
|
||||
blocks found on many Atmel processors. This facilitates using
|
||||
these blocks by different drivers despite processor differences.
|
||||
|
||||
config ATMEL_TCB_CLKSRC
|
||||
bool "TC Block Clocksource"
|
||||
depends on ATMEL_TCLIB && GENERIC_TIME
|
||||
default y
|
||||
help
|
||||
Select this to get a high precision clocksource based on a
|
||||
TC block with a 5+ MHz base clock rate. Two timer channels
|
||||
are combined to make a single 32-bit timer.
|
||||
|
||||
When GENERIC_CLOCKEVENTS is defined, the third timer channel
|
||||
may be used as a clock event device supporting oneshot mode
|
||||
(delays of up to two seconds) based on the 32 KiHz clock.
|
||||
|
||||
config ATMEL_TCB_CLKSRC_BLOCK
|
||||
int
|
||||
depends on ATMEL_TCB_CLKSRC
|
||||
prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
|
||||
default 0
|
||||
range 0 1
|
||||
help
|
||||
Some chips provide more than one TC block, so you have the
|
||||
choice of which one to use for the clock framework. The other
|
||||
TC can be used for other purposes, such as PWM generation and
|
||||
interval timing.
|
||||
|
||||
config IBM_ASM
|
||||
tristate "Device driver for IBM RSA service processor"
|
||||
depends on X86 && PCI && INPUT && EXPERIMENTAL
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_ACER_WMI) += acer-wmi.o
|
|||
obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
|
||||
obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
|
||||
obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
|
||||
obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
|
||||
obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
|
||||
obj-$(CONFIG_LKDTM) += lkdtm.o
|
||||
obj-$(CONFIG_TIFM_CORE) += tifm_core.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
#include <linux/atmel_tc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/* Number of bytes to reserve for the iomem resource */
|
||||
#define ATMEL_TC_IOMEM_SIZE 256
|
||||
|
||||
|
||||
/*
|
||||
* This is a thin library to solve the problem of how to portably allocate
|
||||
* one of the TC blocks. For simplicity, it doesn't currently expect to
|
||||
* share individual timers between different drivers.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_AVR32)
|
||||
/* AVR32 has these divide PBB */
|
||||
const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
|
||||
EXPORT_SYMBOL(atmel_tc_divisors);
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91)
|
||||
/* AT91 has these divide MCK */
|
||||
const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
|
||||
EXPORT_SYMBOL(atmel_tc_divisors);
|
||||
|
||||
#endif
|
||||
|
||||
static DEFINE_SPINLOCK(tc_list_lock);
|
||||
static LIST_HEAD(tc_list);
|
||||
|
||||
/**
|
||||
* atmel_tc_alloc - allocate a specified TC block
|
||||
* @block: which block to allocate
|
||||
* @name: name to be associated with the iomem resource
|
||||
*
|
||||
* Caller allocates a block. If it is available, a pointer to a
|
||||
* pre-initialized struct atmel_tc is returned. The caller can access
|
||||
* the registers directly through the "regs" field.
|
||||
*/
|
||||
struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
|
||||
{
|
||||
struct atmel_tc *tc;
|
||||
struct platform_device *pdev = NULL;
|
||||
struct resource *r;
|
||||
|
||||
spin_lock(&tc_list_lock);
|
||||
list_for_each_entry(tc, &tc_list, node) {
|
||||
if (tc->pdev->id == block) {
|
||||
pdev = tc->pdev;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!pdev || tc->iomem)
|
||||
goto fail;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
|
||||
if (!r)
|
||||
goto fail;
|
||||
|
||||
tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
|
||||
if (!tc->regs)
|
||||
goto fail_ioremap;
|
||||
|
||||
tc->iomem = r;
|
||||
|
||||
out:
|
||||
spin_unlock(&tc_list_lock);
|
||||
return tc;
|
||||
|
||||
fail_ioremap:
|
||||
release_resource(r);
|
||||
fail:
|
||||
tc = NULL;
|
||||
goto out;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(atmel_tc_alloc);
|
||||
|
||||
/**
|
||||
* atmel_tc_free - release a specified TC block
|
||||
* @tc: Timer/counter block that was returned by atmel_tc_alloc()
|
||||
*
|
||||
* This reverses the effect of atmel_tc_alloc(), unmapping the I/O
|
||||
* registers, invalidating the resource returned by that routine and
|
||||
* making the TC available to other drivers.
|
||||
*/
|
||||
void atmel_tc_free(struct atmel_tc *tc)
|
||||
{
|
||||
spin_lock(&tc_list_lock);
|
||||
if (tc->regs) {
|
||||
iounmap(tc->regs);
|
||||
release_resource(tc->iomem);
|
||||
tc->regs = NULL;
|
||||
tc->iomem = NULL;
|
||||
}
|
||||
spin_unlock(&tc_list_lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(atmel_tc_free);
|
||||
|
||||
static int __init tc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct atmel_tc *tc;
|
||||
struct clk *clk;
|
||||
int irq;
|
||||
|
||||
if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
|
||||
return -EINVAL;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return -EINVAL;
|
||||
|
||||
tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
|
||||
if (!tc)
|
||||
return -ENOMEM;
|
||||
|
||||
tc->pdev = pdev;
|
||||
|
||||
clk = clk_get(&pdev->dev, "t0_clk");
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(tc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tc->clk[0] = clk;
|
||||
tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
|
||||
if (IS_ERR(tc->clk[1]))
|
||||
tc->clk[1] = clk;
|
||||
tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
|
||||
if (IS_ERR(tc->clk[2]))
|
||||
tc->clk[2] = clk;
|
||||
|
||||
tc->irq[0] = irq;
|
||||
tc->irq[1] = platform_get_irq(pdev, 1);
|
||||
if (tc->irq[1] < 0)
|
||||
tc->irq[1] = irq;
|
||||
tc->irq[2] = platform_get_irq(pdev, 2);
|
||||
if (tc->irq[2] < 0)
|
||||
tc->irq[2] = irq;
|
||||
|
||||
spin_lock(&tc_list_lock);
|
||||
list_add_tail(&tc->node, &tc_list);
|
||||
spin_unlock(&tc_list_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tc_driver = {
|
||||
.driver.name = "atmel_tcb",
|
||||
};
|
||||
|
||||
static int __init tc_init(void)
|
||||
{
|
||||
return platform_driver_probe(&tc_driver, tc_probe);
|
||||
}
|
||||
arch_initcall(tc_init);
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
/*
|
||||
* Timer/Counter Unit (TC) registers.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef ATMEL_TC_H
|
||||
#define ATMEL_TC_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
/*
|
||||
* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
|
||||
* three general-purpose 16-bit timers. These timers share one register bank.
|
||||
* Depending on the SOC, each timer may have its own clock and IRQ, or those
|
||||
* may be shared by the whole TC block.
|
||||
*
|
||||
* These TC blocks may have up to nine external pins: TCLK0..2 signals for
|
||||
* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
|
||||
* or triggering. Those pins need to be set up for use with the TC block,
|
||||
* else they will be used as GPIOs or for a different controller.
|
||||
*
|
||||
* Although we expect each TC block to have a platform_device node, those
|
||||
* nodes are not what drivers bind to. Instead, they ask for a specific
|
||||
* TC block, by number ... which is a common approach on systems with many
|
||||
* timers. Then they use clk_get() and platform_get_irq() to get clock and
|
||||
* IRQ resources.
|
||||
*/
|
||||
|
||||
struct clk;
|
||||
|
||||
/**
|
||||
* struct atmel_tc - information about a Timer/Counter Block
|
||||
* @pdev: physical device
|
||||
* @iomem: resource associated with the I/O register
|
||||
* @regs: mapping through which the I/O registers can be accessed
|
||||
* @irq: irq for each of the three channels
|
||||
* @clk: internal clock source for each of the three channels
|
||||
* @node: list node, for tclib internal use
|
||||
*
|
||||
* On some platforms, each TC channel has its own clocks and IRQs,
|
||||
* while on others, all TC channels share the same clock and IRQ.
|
||||
* Drivers should clk_enable() all the clocks they need even though
|
||||
* all the entries in @clk may point to the same physical clock.
|
||||
* Likewise, drivers should request irqs independently for each
|
||||
* channel, but they must use IRQF_SHARED in case some of the entries
|
||||
* in @irq are actually the same IRQ.
|
||||
*/
|
||||
struct atmel_tc {
|
||||
struct platform_device *pdev;
|
||||
struct resource *iomem;
|
||||
void __iomem *regs;
|
||||
int irq[3];
|
||||
struct clk *clk[3];
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
|
||||
extern void atmel_tc_free(struct atmel_tc *tc);
|
||||
|
||||
/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
|
||||
extern const u8 atmel_tc_divisors[5];
|
||||
|
||||
|
||||
/*
|
||||
* Two registers have block-wide controls. These are: configuring the three
|
||||
* "external" clocks (or event sources) used by the timer channels; and
|
||||
* synchronizing the timers by resetting them all at once.
|
||||
*
|
||||
* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
|
||||
* signals. Or, it can mean "external to timer", using the TIOA output from
|
||||
* one of the other two timers that's being run in waveform mode.
|
||||
*/
|
||||
|
||||
#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
|
||||
#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
|
||||
|
||||
#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
|
||||
#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
|
||||
#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
|
||||
#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
|
||||
#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
|
||||
#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
|
||||
#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
|
||||
|
||||
|
||||
/*
|
||||
* Each TC block has three "channels", each with one counter and controls.
|
||||
*
|
||||
* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
|
||||
* when it's not "external") is silicon-specific. AT91 platforms use one
|
||||
* set of definitions; AVR32 platforms use a different set. Don't hard-wire
|
||||
* such knowledge into your code, use the global "atmel_tc_divisors" ...
|
||||
* where index N is the divisor for clock N+1, else zero to indicate it uses
|
||||
* the 32 KiHz clock.
|
||||
*
|
||||
* The timers can be chained in various ways, and operated in "waveform"
|
||||
* generation mode (including PWM) or "capture" mode (to time events). In
|
||||
* both modes, behavior can be configured in many ways.
|
||||
*
|
||||
* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
|
||||
* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
|
||||
* uses them only as inputs.
|
||||
*/
|
||||
#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
|
||||
#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
|
||||
|
||||
#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
|
||||
#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
|
||||
#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
|
||||
#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
|
||||
|
||||
#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
|
||||
|
||||
/* Both modes share some CMR bits */
|
||||
#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
|
||||
#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
|
||||
#define ATMEL_TC_XC0 (5 << 0)
|
||||
#define ATMEL_TC_XC1 (6 << 0)
|
||||
#define ATMEL_TC_XC2 (7 << 0)
|
||||
#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
|
||||
#define ATMEL_TC_BURST (3 << 4) /* clock gating */
|
||||
#define ATMEL_TC_GATE_NONE (0 << 4)
|
||||
#define ATMEL_TC_GATE_XC0 (1 << 4)
|
||||
#define ATMEL_TC_GATE_XC1 (2 << 4)
|
||||
#define ATMEL_TC_GATE_XC2 (3 << 4)
|
||||
#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
|
||||
|
||||
/* CAPTURE mode CMR bits */
|
||||
#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
|
||||
#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
|
||||
#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
|
||||
#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
|
||||
#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
|
||||
#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
|
||||
#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
|
||||
#define ATMEL_TC_LDRA_NONE (0 << 16)
|
||||
#define ATMEL_TC_LDRA_RISING (1 << 16)
|
||||
#define ATMEL_TC_LDRA_FALLING (2 << 16)
|
||||
#define ATMEL_TC_LDRA_BOTH (3 << 16)
|
||||
#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
|
||||
#define ATMEL_TC_LDRB_NONE (0 << 18)
|
||||
#define ATMEL_TC_LDRB_RISING (1 << 18)
|
||||
#define ATMEL_TC_LDRB_FALLING (2 << 18)
|
||||
#define ATMEL_TC_LDRB_BOTH (3 << 18)
|
||||
|
||||
/* WAVEFORM mode CMR bits */
|
||||
#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
|
||||
#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
|
||||
#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
|
||||
#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
|
||||
#define ATMEL_TC_EEVT (3 << 10) /* external event source */
|
||||
#define ATMEL_TC_EEVT_TIOB (0 << 10)
|
||||
#define ATMEL_TC_EEVT_XC0 (1 << 10)
|
||||
#define ATMEL_TC_EEVT_XC1 (2 << 10)
|
||||
#define ATMEL_TC_EEVT_XC2 (3 << 10)
|
||||
#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
|
||||
#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
|
||||
#define ATMEL_TC_WAVESEL_UP (0 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
|
||||
#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
|
||||
#define ATMEL_TC_ACPA_NONE (0 << 16)
|
||||
#define ATMEL_TC_ACPA_SET (1 << 16)
|
||||
#define ATMEL_TC_ACPA_CLEAR (2 << 16)
|
||||
#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
|
||||
#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
|
||||
#define ATMEL_TC_ACPC_NONE (0 << 18)
|
||||
#define ATMEL_TC_ACPC_SET (1 << 18)
|
||||
#define ATMEL_TC_ACPC_CLEAR (2 << 18)
|
||||
#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
|
||||
#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
|
||||
#define ATMEL_TC_AEEVT_NONE (0 << 20)
|
||||
#define ATMEL_TC_AEEVT_SET (1 << 20)
|
||||
#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
|
||||
#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
|
||||
#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
|
||||
#define ATMEL_TC_ASWTRG_NONE (0 << 22)
|
||||
#define ATMEL_TC_ASWTRG_SET (1 << 22)
|
||||
#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
|
||||
#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
|
||||
#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
|
||||
#define ATMEL_TC_BCPB_NONE (0 << 24)
|
||||
#define ATMEL_TC_BCPB_SET (1 << 24)
|
||||
#define ATMEL_TC_BCPB_CLEAR (2 << 24)
|
||||
#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
|
||||
#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
|
||||
#define ATMEL_TC_BCPC_NONE (0 << 26)
|
||||
#define ATMEL_TC_BCPC_SET (1 << 26)
|
||||
#define ATMEL_TC_BCPC_CLEAR (2 << 26)
|
||||
#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
|
||||
#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
|
||||
#define ATMEL_TC_BEEVT_NONE (0 << 28)
|
||||
#define ATMEL_TC_BEEVT_SET (1 << 28)
|
||||
#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
|
||||
#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
|
||||
#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
|
||||
#define ATMEL_TC_BSWTRG_NONE (0 << 30)
|
||||
#define ATMEL_TC_BSWTRG_SET (1 << 30)
|
||||
#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
|
||||
#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
|
||||
|
||||
#define ATMEL_TC_CV 0x10 /* counter Value */
|
||||
#define ATMEL_TC_RA 0x14 /* register A */
|
||||
#define ATMEL_TC_RB 0x18 /* register B */
|
||||
#define ATMEL_TC_RC 0x1c /* register C */
|
||||
|
||||
#define ATMEL_TC_SR 0x20 /* status (read-only) */
|
||||
/* Status-only flags */
|
||||
#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
|
||||
#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
|
||||
#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
|
||||
|
||||
#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
|
||||
#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
|
||||
#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
|
||||
|
||||
/* Status and IRQ flags */
|
||||
#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
|
||||
#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
|
||||
#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
|
||||
#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
|
||||
#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
|
||||
#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
|
||||
#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
|
||||
#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue