i2c: piix4: Add support for AMD ML and CZ SMBus changes
The locations of SMBus register base address and enablement bit are changed from AMD ML, which need this patch to be supported. Signed-off-by: Shane Huang <shane.huang@amd.com> Reviewed-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@vger.kernel.org
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@ -13,7 +13,7 @@ Supported adapters:
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* AMD SP5100 (SB700 derivative found on some server mainboards)
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* AMD SP5100 (SB700 derivative found on some server mainboards)
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Datasheet: Publicly available at the AMD website
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Datasheet: Publicly available at the AMD website
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http://support.amd.com/us/Embedded_TechDocs/44413.pdf
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http://support.amd.com/us/Embedded_TechDocs/44413.pdf
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* AMD Hudson-2, CZ
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* AMD Hudson-2, ML, CZ
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Datasheet: Not publicly available
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Datasheet: Not publicly available
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* Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
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* Standard Microsystems (SMSC) SLC90E66 (Victory66) southbridge
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Datasheet: Publicly available at the SMSC website http://www.smsc.com
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Datasheet: Publicly available at the SMSC website http://www.smsc.com
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@ -152,6 +152,7 @@ config I2C_PIIX4
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ATI SB700/SP5100
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ATI SB700/SP5100
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ATI SB800
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ATI SB800
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AMD Hudson-2
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AMD Hudson-2
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AMD ML
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AMD CZ
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AMD CZ
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Serverworks OSB4
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Serverworks OSB4
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Serverworks CSB5
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Serverworks CSB5
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@ -22,7 +22,7 @@
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Intel PIIX4, 440MX
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Intel PIIX4, 440MX
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Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
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Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
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ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
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ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
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AMD Hudson-2, CZ
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AMD Hudson-2, ML, CZ
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SMSC Victory66
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SMSC Victory66
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Note: we assume there can only be one device, with one or more
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Note: we assume there can only be one device, with one or more
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@ -235,7 +235,8 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
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{
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{
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unsigned short piix4_smba;
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unsigned short piix4_smba;
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unsigned short smba_idx = 0xcd6;
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unsigned short smba_idx = 0xcd6;
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u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en;
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u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status;
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u8 i2ccfg, i2ccfg_offset = 0x10;
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/* SB800 and later SMBus does not support forcing address */
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/* SB800 and later SMBus does not support forcing address */
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if (force || force_addr) {
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if (force || force_addr) {
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@ -245,6 +246,14 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
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}
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}
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/* Determine the address of the SMBus areas */
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/* Determine the address of the SMBus areas */
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if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
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PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
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PIIX4_dev->revision >= 0x41) ||
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(PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
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PIIX4_dev->device == 0x790b &&
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PIIX4_dev->revision >= 0x49))
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smb_en = 0x00;
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else
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smb_en = (aux) ? 0x28 : 0x2c;
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smb_en = (aux) ? 0x28 : 0x2c;
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if (!request_region(smba_idx, 2, "smba_idx")) {
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if (!request_region(smba_idx, 2, "smba_idx")) {
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@ -258,13 +267,22 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
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smba_en_hi = inb_p(smba_idx + 1);
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smba_en_hi = inb_p(smba_idx + 1);
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release_region(smba_idx, 2);
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release_region(smba_idx, 2);
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if ((smba_en_lo & 1) == 0) {
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if (!smb_en) {
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smb_en_status = smba_en_lo & 0x10;
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piix4_smba = smba_en_hi << 8;
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if (aux)
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piix4_smba |= 0x20;
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} else {
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smb_en_status = smba_en_lo & 0x01;
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piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
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}
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if (!smb_en_status) {
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dev_err(&PIIX4_dev->dev,
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dev_err(&PIIX4_dev->dev,
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"Host SMBus controller not enabled!\n");
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"Host SMBus controller not enabled!\n");
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return -ENODEV;
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return -ENODEV;
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}
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}
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piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
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if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
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if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
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return -ENODEV;
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return -ENODEV;
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