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perf vendor events intel: Update HaswellX events to V19 

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Andi Kleen 2018-01-18 04:49:26 -08:00 committed by Arnaldo Carvalho de Melo
parent ca3a2d055d
commit 032c16b296
7 changed files with 1064 additions and 1004 deletions
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381
tools/perf/pmu-events/arch/x86/haswellx/cache.json
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@ -10,6 +10,58 @@
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x22",
"BriefDescription": "RFO requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x24",
"BriefDescription": "L2 cache misses when fetching instructions",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x27",
"BriefDescription": "Demand requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"Errata": "HSD78",
"PublicDescription": "Demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x30",
"BriefDescription": "L2 prefetch requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x3f",
"BriefDescription": "All requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.MISS",
"Errata": "HSD78",
"PublicDescription": "All requests that missed L2.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x41",
@ -23,11 +75,21 @@
},
{
"EventCode": "0x24",
"UMask": "0x30",
"BriefDescription": "L2 prefetch requests that miss L2 cache",
"UMask": "0x42",
"BriefDescription": "RFO requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x44",
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
@ -72,6 +134,17 @@
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0xe7",
"BriefDescription": "Demand requests to L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"Errata": "HSD78",
"PublicDescription": "Demand requests to L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0xf8",
@ -82,6 +155,17 @@
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0xff",
"BriefDescription": "All L2 requests",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.REFERENCES",
"Errata": "HSD78",
"PublicDescription": "All requests to L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x27",
"UMask": "0x50",
@ -122,6 +206,27 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
"AnyThread": "1",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x2",
@ -133,13 +238,13 @@
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"UMask": "0x2",
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"EventName": "L1D_PEND_MISS.FB_FULL",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x51",
@ -162,6 +267,28 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"CounterMask": "1",
"Errata": "HSD78, HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
"CounterMask": "6",
"Errata": "HSD78, HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x2",
@ -184,6 +311,17 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x4",
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"CounterMask": "1",
"Errata": "HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x8",
@ -195,17 +333,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"CounterMask": "1",
"Errata": "HSD78, HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x8",
@ -217,17 +344,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x4",
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"CounterMask": "1",
"Errata": "HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x63",
"UMask": "0x2",
@ -288,10 +404,19 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xB7, 0xBB",
"UMask": "0x1",
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x11",
"BriefDescription": "Retired load uops that miss the STLB.",
"BriefDescription": "Retired load uops that miss the STLB. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -303,20 +428,20 @@
{
"EventCode": "0xD0",
"UMask": "0x12",
"BriefDescription": "Retired store uops that miss the STLB.",
"BriefDescription": "Retired store uops that miss the STLB. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"Errata": "HSD29, HSM30",
"SampleAfterValue": "100003",
"L1_Hit_Indication": "1",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x21",
"BriefDescription": "Retired load uops with locked access.",
"BriefDescription": "Retired load uops with locked access. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -328,32 +453,34 @@
{
"EventCode": "0xD0",
"UMask": "0x41",
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
"BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"Errata": "HSD29, HSM30",
"PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x42",
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
"BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"Errata": "HSD29, HSM30",
"SampleAfterValue": "100003",
"L1_Hit_Indication": "1",
"PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x81",
"BriefDescription": "All retired load uops.",
"BriefDescription": "All retired load uops. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -365,14 +492,15 @@
{
"EventCode": "0xD0",
"UMask": "0x82",
"BriefDescription": "All retired store uops.",
"BriefDescription": "All retired store uops. (precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"Errata": "HSD29, HSM30",
"SampleAfterValue": "2000003",
"L1_Hit_Indication": "1",
"PublicDescription": "This event counts all store uops retired. This is a precise event.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
@ -402,13 +530,13 @@
{
"EventCode": "0xD1",
"UMask": "0x4",
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"PublicDescription": "Retired load uops with L3 cache hits as data sources.",
"PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "50021",
"CounterHTOff": "0,1,2,3"
},
@ -421,20 +549,19 @@
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"Errata": "HSM30",
"PublicDescription": "Retired load uops missed L1 cache as data sources.",
"PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD1",
"UMask": "0x10",
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
"BriefDescription": "Retired load uops with L2 cache misses as data sources.",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"Errata": "HSD29, HSM30",
"PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
"SampleAfterValue": "50021",
"CounterHTOff": "0,1,2,3"
},
@ -447,7 +574,6 @@
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
"Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
"PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -478,24 +604,26 @@
{
"EventCode": "0xD2",
"UMask": "0x2",
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "20011",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD2",
"UMask": "0x4",
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
"Errata": "HSD29, HSD25, HSM26, HSM30",
"PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "20011",
"CounterHTOff": "0,1,2,3"
},
@ -514,20 +642,19 @@
{
"EventCode": "0xD3",
"UMask": "0x1",
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
"Errata": "HSD74, HSD29, HSD25, HSM30",
"PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
"PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD3",
"UMask": "0x4",
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -539,7 +666,7 @@
{
"EventCode": "0xD3",
"UMask": "0x10",
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -551,7 +678,7 @@
{
"EventCode": "0xD3",
"UMask": "0x20",
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3",
@ -706,134 +833,10 @@
"BriefDescription": "Split locks in SQ",
"Counter": "0,1,2,3",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x42",
"BriefDescription": "RFO requests that hit L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x22",
"BriefDescription": "RFO requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x44",
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Number of instruction fetches that hit the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x24",
"BriefDescription": "L2 cache misses when fetching instructions",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Number of instruction fetches that missed the L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x27",
"BriefDescription": "Demand requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"Errata": "HSD78",
"PublicDescription": "Demand requests that miss L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0xe7",
"BriefDescription": "Demand requests to L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"Errata": "HSD78",
"PublicDescription": "Demand requests to L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0x3f",
"BriefDescription": "All requests that miss L2 cache",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.MISS",
"Errata": "HSD78",
"PublicDescription": "All requests that missed L2.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x24",
"UMask": "0xff",
"BriefDescription": "All L2 requests",
"Counter": "0,1,2,3",
"EventName": "L2_RQSTS.REFERENCES",
"Errata": "HSD78",
"PublicDescription": "All requests to L2 cache.",
"SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xB7, 0xBB",
"UMask": "0x1",
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
"CounterMask": "6",
"Errata": "HSD78, HSD62, HSD61",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
"AnyThread": "1",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x2",
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"EventName": "L1D_PEND_MISS.FB_FULL",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"Offcore": "1",
"EventCode": "0xB7, 0xBB",
@ -843,6 +846,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -855,6 +859,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -867,6 +872,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -879,6 +885,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -891,6 +898,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -903,6 +911,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -915,6 +924,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -927,6 +937,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -939,6 +950,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -951,6 +963,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -963,6 +976,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -975,6 +989,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -987,6 +1002,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -999,6 +1015,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1011,6 +1028,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1023,6 +1041,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1035,6 +1054,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1047,6 +1067,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1059,6 +1080,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -1071,6 +1093,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
}

20
tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
View File

@ -19,6 +19,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC6",
"UMask": "0x7",
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
"Counter": "0,1,2,3",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xCA",
"UMask": "0x2",
@ -69,15 +79,5 @@
"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xC6",
"UMask": "0x7",
"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
"Counter": "0,1,2,3",
"EventName": "AVX_INSTS.ALL",
"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]

142
tools/perf/pmu-events/arch/x86/haswellx/frontend.json
View File

@ -20,57 +20,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x8",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x10",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x20",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_CYCLES",
"CounterMask": "1",
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x4",
@ -81,6 +30,16 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x8",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x8",
@ -91,6 +50,16 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x10",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x10",
@ -134,6 +103,16 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x20",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x24",
@ -156,6 +135,38 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_CYCLES",
"CounterMask": "1",
"PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EdgeDetect": "1",
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_SWITCHES",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x79",
"UMask": "0x3c",
@ -194,6 +205,15 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x80",
"UMask": "0x4",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x9C",
"UMask": "0x1",
@ -270,25 +290,5 @@
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EdgeDetect": "1",
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"EventName": "IDQ.MS_SWITCHES",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x80",
"UMask": "0x4",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"EventName": "ICACHE.IFDATA_STALL",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]

28
tools/perf/pmu-events/arch/x86/haswellx/memory.json
View File

@ -409,6 +409,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -421,6 +422,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -433,6 +435,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -445,6 +448,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -457,6 +461,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -469,6 +474,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -481,6 +487,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -493,6 +500,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -505,6 +513,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -517,6 +526,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -529,6 +539,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -541,6 +552,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -553,6 +565,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -565,6 +578,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -577,6 +591,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -589,6 +604,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -601,6 +617,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -613,6 +630,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -625,6 +643,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -637,6 +656,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -649,6 +669,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -661,6 +682,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -673,6 +695,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -685,6 +708,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -697,6 +721,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -709,6 +734,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -721,6 +747,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
@ -733,6 +760,7 @@
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
}

20
tools/perf/pmu-events/arch/x86/haswellx/other.json
View File

@ -9,16 +9,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x5C",
"UMask": "0x2",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EdgeDetect": "1",
"EventCode": "0x5C",
@ -30,6 +20,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x5C",
"UMask": "0x2",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x63",
"UMask": "0x1",

1187
tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
View File

File diff suppressed because it is too large Load Diff

290
tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
View File

@ -38,6 +38,16 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0xe",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0x10",
@ -68,6 +78,16 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0x60",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0x80",
@ -117,6 +137,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0xe",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0x10",
@ -147,6 +177,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0x60",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0x80",
@ -205,6 +245,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"UMask": "0xe",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"UMask": "0x10",
@ -235,6 +285,16 @@
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"UMask": "0x60",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
"Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xae",
"UMask": "0x1",
@ -255,34 +315,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x21",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x41",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x81",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x12",
@ -293,34 +325,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x22",
"BriefDescription": "Number of ITLB page walker hits in the L2",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x42",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x82",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x14",
@ -332,35 +336,6 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x24",
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"Errata": "HSD25",
"PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x44",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x84",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x18",
@ -372,6 +347,37 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x21",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x22",
"BriefDescription": "Number of ITLB page walker hits in the L2",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"PublicDescription": "Number of ITLB page walker loads that hit in the L2.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x24",
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"Errata": "HSD25",
"PublicDescription": "Number of ITLB page walker loads that hit in the L3.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x28",
@ -383,6 +389,33 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x41",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x42",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x44",
"BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x48",
@ -392,6 +425,33 @@
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x81",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x82",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x84",
"BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.",
"Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xBC",
"UMask": "0x88",
@ -420,65 +480,5 @@
"PublicDescription": "Count number of STLB flush attempts.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0xe",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x08",
"UMask": "0x60",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Number of cache load STLB hits. No page walk.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0xe",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x49",
"UMask": "0x60",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
"Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"UMask": "0xe",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
"Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Completed page walks in ITLB of any page size.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85",
"UMask": "0x60",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
"Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT",
"PublicDescription": "ITLB misses that hit STLB. No page walk.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
}
]