Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next
* clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock
This commit is contained in:
Stephen Boyd
commit
032405a754
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@ -6,6 +6,7 @@ Required properties :
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- "allwinner,sun8i-a83t-de2-clk"
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- "allwinner,sun8i-h3-de2-clk"
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-a64-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- reg: Must contain the registers base address and length
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@ -92,6 +92,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
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base = of_iomap(np, 0);
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of_node_put(np);
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WARN_ON(!base);
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/* Do not bypass PLLs initially */
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@ -402,6 +402,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20);
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clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
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clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
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clks[IMX6SX_CLK_OCRAM_S] = imx_clk_gate2("ocram_s", "ahb", base + 0x6c, 28);
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clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30);
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/* CCGR2 */
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@ -135,6 +135,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
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base = of_iomap(np, 0);
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of_node_put(np);
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WARN_ON(!base);
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clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
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@ -288,17 +288,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
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.compatible = "allwinner,sun8i-v3s-de2-clk",
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.data = &sun8i_v3s_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-a64-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-h5-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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},
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/*
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* The Allwinner A64 SoC needs some bit to be poke in syscon to make
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* DE2 really working.
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* So there's currently no A64 compatible here.
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* H5 shares the same reset line with A64, so here H5 is using the
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* clock description of A64.
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*/
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{ }
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};
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@ -66,17 +66,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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CLK_SET_RATE_UNGATE);
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
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"osc24M", 0x0010,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
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"osc24M", 0x0010,
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192000000, /* Minimum rate */
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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@ -152,17 +153,18 @@ static struct ccu_nk pll_periph1_clk = {
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};
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
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"osc24M", 0x030,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
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"osc24M", 0x030,
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192000000, /* Minimum rate */
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static struct ccu_nkm pll_sata_clk = {
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.enable = BIT(31),
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@ -654,7 +656,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
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static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
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static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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0x104, 0, 4, 24, 3, BIT(31), 0);
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0x104, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
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0x108, 0, 4, 24, 3, BIT(31), 0);
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@ -666,9 +669,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
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static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
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0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
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0x118, 0, 4, 24, 3, BIT(31), 0);
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0x118, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
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0x11c, 0, 4, 24, 3, BIT(31), 0);
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0x11c, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static const char * const deinterlace_parents[] = { "pll-periph0",
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"pll-periph1" };
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@ -698,7 +703,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
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static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
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0x150, 0, 4, 24, 2, BIT(31), 0);
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0x150, 0, 4, 24, 2, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
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0x154, BIT(31), 0);
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@ -25,7 +25,9 @@
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#define CLK_PLL_AUDIO_2X 4
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#define CLK_PLL_AUDIO_4X 5
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#define CLK_PLL_AUDIO_8X 6
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#define CLK_PLL_VIDEO0 7
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/* PLL_VIDEO0 is exported */
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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@ -34,7 +36,9 @@
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#define CLK_PLL_PERIPH0_2X 13
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#define CLK_PLL_PERIPH1 14
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#define CLK_PLL_PERIPH1_2X 15
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#define CLK_PLL_VIDEO1 16
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/* PLL_VIDEO1 is exported */
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#define CLK_PLL_VIDEO1_2X 17
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#define CLK_PLL_SATA 18
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#define CLK_PLL_SATA_OUT 19
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@ -8,6 +8,7 @@ obj-y += clk-periph-fixed.o
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obj-y += clk-periph-gate.o
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obj-y += clk-pll.o
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obj-y += clk-pll-out.o
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obj-y += clk-sdmmc-mux.o
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obj-y += clk-super.o
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obj-y += clk-tegra-audio.o
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obj-y += clk-tegra-periph.o
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@ -24,3 +25,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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obj-y += cvb.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
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obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o
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obj-y += clk-utils.o
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@ -32,35 +32,15 @@
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static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
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unsigned long parent_rate)
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{
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u64 divider_ux1 = parent_rate;
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u8 flags = divider->flags;
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int mul;
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int div;
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if (!rate)
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div = div_frac_get(rate, parent_rate, divider->width,
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divider->frac_width, divider->flags);
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if (div < 0)
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return 0;
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mul = get_mul(divider);
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if (!(flags & TEGRA_DIVIDER_INT))
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divider_ux1 *= mul;
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if (flags & TEGRA_DIVIDER_ROUND_UP)
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divider_ux1 += rate - 1;
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do_div(divider_ux1, rate);
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if (flags & TEGRA_DIVIDER_INT)
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divider_ux1 *= mul;
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divider_ux1 -= mul;
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if ((s64)divider_ux1 < 0)
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return 0;
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if (divider_ux1 > get_max_div(divider))
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return get_max_div(divider);
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return divider_ux1;
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return div;
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}
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static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
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@ -227,13 +227,11 @@ enum clk_id {
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tegra_clk_sdmmc1_9,
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tegra_clk_sdmmc2,
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tegra_clk_sdmmc2_8,
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tegra_clk_sdmmc2_9,
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tegra_clk_sdmmc3,
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tegra_clk_sdmmc3_8,
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tegra_clk_sdmmc3_9,
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tegra_clk_sdmmc4,
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tegra_clk_sdmmc4_8,
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tegra_clk_sdmmc4_9,
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tegra_clk_se,
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tegra_clk_soc_therm,
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tegra_clk_soc_therm_8,
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|
|
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@ -0,0 +1,251 @@
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|||
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
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*
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||||
* based on clk-mux.c
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||||
*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
|
||||
* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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||||
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define DIV_MASK GENMASK(7, 0)
|
||||
#define MUX_SHIFT 29
|
||||
#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
|
||||
#define SDMMC_MUL 2
|
||||
|
||||
#define get_max_div(d) DIV_MASK
|
||||
#define get_div_field(val) ((val) & DIV_MASK)
|
||||
#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
|
||||
|
||||
static const char * const mux_sdmmc_parents[] = {
|
||||
"pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
|
||||
};
|
||||
|
||||
static const u8 mux_lj_idx[] = {
|
||||
[0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
|
||||
};
|
||||
|
||||
static const u8 mux_non_lj_idx[] = {
|
||||
[0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
|
||||
};
|
||||
|
||||
static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
int num_parents, i;
|
||||
u32 src, val;
|
||||
const u8 *mux_idx;
|
||||
|
||||
num_parents = clk_hw_get_num_parents(hw);
|
||||
|
||||
val = readl_relaxed(sdmmc_mux->reg);
|
||||
src = get_mux_field(val);
|
||||
if (get_div_field(val))
|
||||
mux_idx = mux_non_lj_idx;
|
||||
else
|
||||
mux_idx = mux_lj_idx;
|
||||
|
||||
for (i = 0; i < num_parents; i++) {
|
||||
if (mux_idx[i] == src)
|
||||
return i;
|
||||
}
|
||||
|
||||
WARN(1, "Unknown parent selector %d\n", src);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
u32 val;
|
||||
|
||||
|
||||
val = readl_relaxed(sdmmc_mux->reg);
|
||||
if (get_div_field(val))
|
||||
index = mux_non_lj_idx[index];
|
||||
else
|
||||
index = mux_lj_idx[index];
|
||||
|
||||
val &= ~MUX_MASK;
|
||||
val |= index << MUX_SHIFT;
|
||||
|
||||
writel(val, sdmmc_mux->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
u32 val;
|
||||
int div;
|
||||
u64 rate = parent_rate;
|
||||
|
||||
val = readl_relaxed(sdmmc_mux->reg);
|
||||
div = get_div_field(val);
|
||||
|
||||
div += SDMMC_MUL;
|
||||
|
||||
rate *= SDMMC_MUL;
|
||||
rate += div - 1;
|
||||
do_div(rate, div);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
int div;
|
||||
unsigned long output_rate = req->best_parent_rate;
|
||||
|
||||
req->rate = max(req->rate, req->min_rate);
|
||||
req->rate = min(req->rate, req->max_rate);
|
||||
|
||||
if (!req->rate)
|
||||
return output_rate;
|
||||
|
||||
div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
|
||||
if (div < 0)
|
||||
div = 0;
|
||||
|
||||
if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
|
||||
req->rate = DIV_ROUND_UP(output_rate * SDMMC_MUL,
|
||||
div + SDMMC_MUL);
|
||||
else
|
||||
req->rate = output_rate * SDMMC_MUL / (div + SDMMC_MUL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
int div;
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
u8 src;
|
||||
|
||||
div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
|
||||
if (div < 0)
|
||||
return div;
|
||||
|
||||
if (sdmmc_mux->lock)
|
||||
spin_lock_irqsave(sdmmc_mux->lock, flags);
|
||||
|
||||
src = clk_sdmmc_mux_get_parent(hw);
|
||||
if (div)
|
||||
src = mux_non_lj_idx[src];
|
||||
else
|
||||
src = mux_lj_idx[src];
|
||||
|
||||
val = src << MUX_SHIFT;
|
||||
val |= div;
|
||||
writel(val, sdmmc_mux->reg);
|
||||
fence_udelay(2, sdmmc_mux->reg);
|
||||
|
||||
if (sdmmc_mux->lock)
|
||||
spin_unlock_irqrestore(sdmmc_mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
|
||||
struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
|
||||
|
||||
__clk_hw_set_clk(gate_hw, hw);
|
||||
|
||||
return gate_ops->is_enabled(gate_hw);
|
||||
}
|
||||
|
||||
static int clk_sdmmc_mux_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
|
||||
struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
|
||||
|
||||
__clk_hw_set_clk(gate_hw, hw);
|
||||
|
||||
return gate_ops->enable(gate_hw);
|
||||
}
|
||||
|
||||
static void clk_sdmmc_mux_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
|
||||
const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
|
||||
struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
|
||||
|
||||
gate_ops->disable(gate_hw);
|
||||
}
|
||||
|
||||
static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
|
||||
.get_parent = clk_sdmmc_mux_get_parent,
|
||||
.set_parent = clk_sdmmc_mux_set_parent,
|
||||
.determine_rate = clk_sdmmc_mux_determine_rate,
|
||||
.recalc_rate = clk_sdmmc_mux_recalc_rate,
|
||||
.set_rate = clk_sdmmc_mux_set_rate,
|
||||
.is_enabled = clk_sdmmc_mux_is_enabled,
|
||||
.enable = clk_sdmmc_mux_enable,
|
||||
.disable = clk_sdmmc_mux_disable,
|
||||
};
|
||||
|
||||
struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
|
||||
void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
|
||||
unsigned long flags, void *lock)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
const struct tegra_clk_periph_regs *bank;
|
||||
struct tegra_sdmmc_mux *sdmmc_mux;
|
||||
|
||||
init.ops = &tegra_clk_sdmmc_mux_ops;
|
||||
init.name = name;
|
||||
init.flags = flags;
|
||||
init.parent_names = mux_sdmmc_parents;
|
||||
init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
|
||||
|
||||
bank = get_reg_bank(clk_num);
|
||||
if (!bank)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
|
||||
if (!sdmmc_mux)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* Data in .init is copied by clk_register(), so stack variable OK */
|
||||
sdmmc_mux->hw.init = &init;
|
||||
sdmmc_mux->reg = clk_base + offset;
|
||||
sdmmc_mux->lock = lock;
|
||||
sdmmc_mux->gate.clk_base = clk_base;
|
||||
sdmmc_mux->gate.regs = bank;
|
||||
sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
|
||||
sdmmc_mux->gate.clk_num = clk_num;
|
||||
sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
|
||||
sdmmc_mux->div_flags = div_flags;
|
||||
sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
|
||||
|
||||
clk = clk_register(NULL, &sdmmc_mux->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(sdmmc_mux);
|
||||
return clk;
|
||||
}
|
||||
|
||||
sdmmc_mux->gate.hw.clk = clk;
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
|
@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
|
|||
[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
|
||||
};
|
||||
|
||||
static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
|
||||
"pll_p",
|
||||
"pll_c4_out2", "pll_c4_out0", /* LJ input */
|
||||
"pll_c4_out2", "pll_c4_out1",
|
||||
"pll_c4_out1", /* LJ input */
|
||||
"clk_m", "pll_c4_out0"
|
||||
};
|
||||
#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
|
||||
|
||||
static const char *mux_pllp_pllc2_c_c3_clkm[] = {
|
||||
"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
|
||||
};
|
||||
|
|
@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
|
||||
MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
|
||||
MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
|
||||
MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
|
||||
MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
|
||||
MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
|
||||
MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
|
||||
MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
|
||||
MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
|
||||
|
|
|
|||
|
|
@ -44,6 +44,8 @@
|
|||
#define CLK_SOURCE_EMC 0x19c
|
||||
#define CLK_SOURCE_SOR1 0x410
|
||||
#define CLK_SOURCE_LA 0x1f8
|
||||
#define CLK_SOURCE_SDMMC2 0x154
|
||||
#define CLK_SOURCE_SDMMC4 0x164
|
||||
|
||||
#define PLLC_BASE 0x80
|
||||
#define PLLC_OUT 0x84
|
||||
|
|
@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
|
||||
[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
|
||||
[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
|
||||
[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
|
||||
[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
|
||||
[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
|
||||
[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
|
||||
[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
|
||||
[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
|
||||
[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
|
||||
[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
|
||||
|
|
@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
|
|||
0, NULL);
|
||||
clks[TEGRA210_CLK_ACLK] = clk;
|
||||
|
||||
clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
|
||||
CLK_SOURCE_SDMMC2, 9,
|
||||
TEGRA_DIVIDER_ROUND_UP, 0, NULL);
|
||||
clks[TEGRA210_CLK_SDMMC2] = clk;
|
||||
|
||||
clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
|
||||
CLK_SOURCE_SDMMC4, 15,
|
||||
TEGRA_DIVIDER_ROUND_UP, 0, NULL);
|
||||
clks[TEGRA210_CLK_SDMMC4] = clk;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
|
||||
struct tegra_periph_init_data *init = &tegra210_periph[i];
|
||||
struct clk **clkp;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define div_mask(w) ((1 << (w)) - 1)
|
||||
|
||||
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
|
||||
u8 frac_width, u8 flags)
|
||||
{
|
||||
u64 divider_ux1 = parent_rate;
|
||||
int mul;
|
||||
|
||||
if (!rate)
|
||||
return 0;
|
||||
|
||||
mul = 1 << frac_width;
|
||||
|
||||
if (!(flags & TEGRA_DIVIDER_INT))
|
||||
divider_ux1 *= mul;
|
||||
|
||||
if (flags & TEGRA_DIVIDER_ROUND_UP)
|
||||
divider_ux1 += rate - 1;
|
||||
|
||||
do_div(divider_ux1, rate);
|
||||
|
||||
if (flags & TEGRA_DIVIDER_INT)
|
||||
divider_ux1 *= mul;
|
||||
|
||||
if (divider_ux1 < mul)
|
||||
return 0;
|
||||
|
||||
divider_ux1 -= mul;
|
||||
|
||||
if (divider_ux1 > div_mask(width))
|
||||
return div_mask(width);
|
||||
|
||||
return divider_ux1;
|
||||
}
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/**
|
||||
* struct tegra_clk_sync_source - external clock source from codec
|
||||
|
|
@ -705,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char *name,
|
|||
const char * const *parent_names, u8 num_parents,
|
||||
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
|
||||
spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
|
||||
*
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @reg: register controlling mux and divider
|
||||
* @flags: hardware-specific flags
|
||||
* @lock: optional register lock
|
||||
* @gate: gate clock
|
||||
* @gate_ops: gate clock ops
|
||||
*/
|
||||
struct tegra_sdmmc_mux {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
spinlock_t *lock;
|
||||
const struct clk_ops *gate_ops;
|
||||
struct tegra_clk_periph_gate gate;
|
||||
u8 div_flags;
|
||||
};
|
||||
|
||||
#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
|
||||
|
||||
struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
|
||||
void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
|
||||
unsigned long flags, void *lock);
|
||||
|
||||
/**
|
||||
* struct clk_init_table - clock initialization table
|
||||
* @clk_id: clock id as mentioned in device tree bindings
|
||||
|
|
@ -811,6 +838,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
|||
int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
|
||||
u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
|
||||
int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
|
||||
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
|
||||
u8 frac_width, u8 flags);
|
||||
|
||||
|
||||
/* Combined read fence with delay */
|
||||
#define fence_udelay(delay, reg) \
|
||||
|
|
|
|||
|
|
@ -27,6 +27,12 @@
|
|||
#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
|
||||
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
|
||||
|
||||
#define UNIPHIER_PERI_CLK_SCSSI(idx) \
|
||||
UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)
|
||||
|
||||
#define UNIPHIER_PERI_CLK_MCSSI(idx) \
|
||||
UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
|
||||
|
||||
const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
|
||||
UNIPHIER_PERI_CLK_UART(0, 0),
|
||||
UNIPHIER_PERI_CLK_UART(1, 1),
|
||||
|
|
@ -38,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
|
|||
UNIPHIER_PERI_CLK_I2C(6, 2),
|
||||
UNIPHIER_PERI_CLK_I2C(7, 3),
|
||||
UNIPHIER_PERI_CLK_I2C(8, 4),
|
||||
UNIPHIER_PERI_CLK_SCSSI(11),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
@ -53,5 +60,7 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
|
|||
UNIPHIER_PERI_CLK_FI2C(8, 4),
|
||||
UNIPHIER_PERI_CLK_FI2C(9, 5),
|
||||
UNIPHIER_PERI_CLK_FI2C(10, 6),
|
||||
UNIPHIER_PERI_CLK_SCSSI(11),
|
||||
UNIPHIER_PERI_CLK_MCSSI(12),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,18 +29,20 @@
|
|||
UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
|
||||
UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
|
||||
|
||||
/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
|
||||
#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
|
||||
UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
|
||||
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
|
||||
|
||||
#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
|
||||
UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
|
||||
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
|
||||
|
||||
#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
|
||||
UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
|
||||
UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
|
||||
UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
|
||||
|
||||
#define UNIPHIER_SYS_CLK_NAND_4X(idx) \
|
||||
UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
|
||||
|
||||
#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
|
||||
UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
|
||||
|
|
@ -93,7 +95,9 @@ const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
|
||||
UNIPHIER_LD4_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD4_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
|
||||
|
|
@ -108,7 +112,9 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
|
||||
UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
|
||||
UNIPHIER_LD4_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD4_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
|
||||
|
|
@ -118,6 +124,9 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
|
|||
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
|
||||
UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
|
||||
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
|
||||
UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
|
||||
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
|
||||
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
|
||||
UNIPHIER_PRO4_SYS_CLK_AIO(40),
|
||||
|
|
@ -130,7 +139,9 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
|
||||
UNIPHIER_LD4_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD4_SYS_CLK_SD,
|
||||
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
|
||||
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
|
||||
|
|
@ -143,7 +154,9 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
|
||||
UNIPHIER_PRO5_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_PRO5_SYS_CLK_SD,
|
||||
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
|
||||
UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
|
||||
|
|
@ -158,7 +171,9 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
|
||||
UNIPHIER_PRO5_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_PRO5_SYS_CLK_SD,
|
||||
UNIPHIER_PRO4_SYS_CLK_ETHER(6),
|
||||
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
|
||||
|
|
@ -166,8 +181,11 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
|
|||
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
|
||||
UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
|
||||
/* The document mentions 0x2104 bit 18, but not functional */
|
||||
UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
|
||||
UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
|
||||
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
|
||||
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
|
||||
UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
|
||||
UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
|
||||
UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
|
||||
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
|
||||
UNIPHIER_PRO5_SYS_CLK_AIO(40),
|
||||
{ /* sentinel */ }
|
||||
|
|
@ -180,7 +198,9 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
|
||||
UNIPHIER_LD11_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD11_SYS_CLK_EMMC(4),
|
||||
/* Index 5 reserved for eMMC PHY */
|
||||
UNIPHIER_LD11_SYS_CLK_ETHER(6),
|
||||
|
|
@ -213,7 +233,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
|
||||
UNIPHIER_LD11_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD11_SYS_CLK_EMMC(4),
|
||||
/* Index 5 reserved for eMMC PHY */
|
||||
UNIPHIER_LD20_SYS_CLK_SD,
|
||||
|
|
@ -226,8 +248,10 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
|
|||
* We do not use bit 15 here.
|
||||
*/
|
||||
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
|
||||
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
|
||||
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
|
||||
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
|
||||
UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
|
||||
UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
|
||||
UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
|
||||
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
|
||||
UNIPHIER_LD11_SYS_CLK_AIO(40),
|
||||
UNIPHIER_LD11_SYS_CLK_EVEA(41),
|
||||
|
|
@ -254,19 +278,21 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
|
|||
UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
|
||||
UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
|
||||
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
|
||||
UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
|
||||
UNIPHIER_LD20_SYS_CLK_SD,
|
||||
UNIPHIER_LD11_SYS_CLK_NAND(2),
|
||||
UNIPHIER_SYS_CLK_NAND_4X(3),
|
||||
UNIPHIER_LD11_SYS_CLK_EMMC(4),
|
||||
UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
|
||||
UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
|
||||
UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
|
||||
UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
|
||||
UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
|
||||
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
|
||||
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
|
||||
UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
|
||||
UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
|
||||
UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
|
||||
UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
|
||||
UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
|
||||
UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
|
||||
UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
|
||||
UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
|
||||
UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
|
||||
UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
|
||||
UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@
|
|||
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
|
||||
#define CLK_PLL_VIDEO0 7
|
||||
|
||||
#define CLK_PLL_VIDEO1 16
|
||||
|
||||
#define CLK_CPU 24
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 29
|
||||
|
|
|
|||
Loading…
Reference in New Issue