rtc: stm32: rework register management to prepare other version of RTC
This patch reworks register/bits management because next version of RTC uses the same way of working but with different register's offset or bits moved in new registers. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Amelie Delaunay
Alexandre Belloni
parent
819cbde521
commit
02b0cc345c
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@ -16,15 +16,6 @@
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#define DRIVER_NAME "stm32_rtc"
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/* STM32 RTC registers */
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#define STM32_RTC_TR 0x00
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#define STM32_RTC_DR 0x04
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#define STM32_RTC_CR 0x08
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#define STM32_RTC_ISR 0x0C
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#define STM32_RTC_PRER 0x10
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#define STM32_RTC_ALRMAR 0x1C
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#define STM32_RTC_WPR 0x24
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/* STM32_RTC_TR bit fields */
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#define STM32_RTC_TR_SEC_SHIFT 0
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#define STM32_RTC_TR_SEC GENMASK(6, 0)
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@ -85,7 +76,26 @@
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#define RTC_WPR_2ND_KEY 0x53
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#define RTC_WPR_WRONG_KEY 0xFF
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struct stm32_rtc;
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struct stm32_rtc_registers {
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u8 tr;
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u8 dr;
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u8 cr;
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u8 isr;
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u8 prer;
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u8 alrmar;
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u8 wpr;
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};
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struct stm32_rtc_events {
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u32 alra;
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};
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struct stm32_rtc_data {
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const struct stm32_rtc_registers regs;
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const struct stm32_rtc_events events;
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void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
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bool has_pclk;
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bool need_dbp;
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};
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@ -96,30 +106,35 @@ struct stm32_rtc {
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struct regmap *dbp;
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unsigned int dbp_reg;
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unsigned int dbp_mask;
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struct stm32_rtc_data *data;
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struct clk *pclk;
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struct clk *rtc_ck;
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const struct stm32_rtc_data *data;
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int irq_alarm;
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};
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static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
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{
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writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + STM32_RTC_WPR);
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writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + STM32_RTC_WPR);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
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writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
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}
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static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
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{
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writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + STM32_RTC_WPR);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
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}
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static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
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{
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unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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if (!(isr & STM32_RTC_ISR_INITF)) {
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isr |= STM32_RTC_ISR_INIT;
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writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
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writel_relaxed(isr, rtc->base + regs->isr);
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/*
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* It takes around 2 rtc_ck clock cycles to enter in
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@ -128,7 +143,7 @@ static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
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* 1MHz, we poll every 10 us with a timeout of 100ms.
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*/
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return readl_relaxed_poll_timeout_atomic(
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rtc->base + STM32_RTC_ISR,
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rtc->base + regs->isr,
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isr, (isr & STM32_RTC_ISR_INITF),
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10, 100000);
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}
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@ -138,40 +153,50 @@ static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
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static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
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{
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unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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isr &= ~STM32_RTC_ISR_INIT;
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writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
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writel_relaxed(isr, rtc->base + regs->isr);
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}
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static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
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{
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unsigned int isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int isr = readl_relaxed(rtc->base + regs->isr);
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isr &= ~STM32_RTC_ISR_RSF;
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writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
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writel_relaxed(isr, rtc->base + regs->isr);
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/*
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* Wait for RSF to be set to ensure the calendar registers are
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* synchronised, it takes around 2 rtc_ck clock cycles
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*/
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return readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
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return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
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isr,
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(isr & STM32_RTC_ISR_RSF),
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10, 100000);
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}
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static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
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unsigned int flags)
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{
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rtc->data->clear_events(rtc, flags);
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}
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static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
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{
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struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
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unsigned int isr, cr;
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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unsigned int status, cr;
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mutex_lock(&rtc->rtc_dev->ops_lock);
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isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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cr = readl_relaxed(rtc->base + STM32_RTC_CR);
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status = readl_relaxed(rtc->base + regs->isr);
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cr = readl_relaxed(rtc->base + regs->cr);
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if ((isr & STM32_RTC_ISR_ALRAF) &&
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if ((status & evts->alra) &&
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(cr & STM32_RTC_CR_ALRAIE)) {
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/* Alarm A flag - Alarm interrupt */
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dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
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@ -179,9 +204,8 @@ static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
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/* Pass event to the kernel */
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rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
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/* Clear event flag, otherwise new events won't be received */
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writel_relaxed(isr & ~STM32_RTC_ISR_ALRAF,
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rtc->base + STM32_RTC_ISR);
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/* Clear event flags, otherwise new events won't be received */
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stm32_rtc_clear_event_flags(rtc, evts->alra);
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}
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mutex_unlock(&rtc->rtc_dev->ops_lock);
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@ -228,11 +252,12 @@ static void bcd2tm(struct rtc_time *tm)
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static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int tr, dr;
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/* Time and Date in BCD format */
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tr = readl_relaxed(rtc->base + STM32_RTC_TR);
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dr = readl_relaxed(rtc->base + STM32_RTC_DR);
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tr = readl_relaxed(rtc->base + regs->tr);
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dr = readl_relaxed(rtc->base + regs->dr);
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tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
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tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
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@ -253,6 +278,7 @@ static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
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static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int tr, dr;
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int ret = 0;
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@ -277,8 +303,8 @@ static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
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goto end;
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}
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writel_relaxed(tr, rtc->base + STM32_RTC_TR);
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writel_relaxed(dr, rtc->base + STM32_RTC_DR);
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writel_relaxed(tr, rtc->base + regs->tr);
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writel_relaxed(dr, rtc->base + regs->dr);
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stm32_rtc_exit_init_mode(rtc);
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@ -292,12 +318,14 @@ end:
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static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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struct rtc_time *tm = &alrm->time;
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unsigned int alrmar, cr, isr;
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unsigned int alrmar, cr, status;
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alrmar = readl_relaxed(rtc->base + STM32_RTC_ALRMAR);
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cr = readl_relaxed(rtc->base + STM32_RTC_CR);
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isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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alrmar = readl_relaxed(rtc->base + regs->alrmar);
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cr = readl_relaxed(rtc->base + regs->cr);
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status = readl_relaxed(rtc->base + regs->isr);
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if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
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/*
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@ -350,7 +378,7 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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bcd2tm(tm);
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alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
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alrm->pending = (isr & STM32_RTC_ISR_ALRAF) ? 1 : 0;
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alrm->pending = (status & evts->alra) ? 1 : 0;
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return 0;
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}
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@ -358,9 +386,11 @@ static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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unsigned int isr, cr;
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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const struct stm32_rtc_events *evts = &rtc->data->events;
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unsigned int cr;
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cr = readl_relaxed(rtc->base + STM32_RTC_CR);
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cr = readl_relaxed(rtc->base + regs->cr);
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stm32_rtc_wpr_unlock(rtc);
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@ -369,12 +399,10 @@ static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
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else
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cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
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writel_relaxed(cr, rtc->base + STM32_RTC_CR);
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writel_relaxed(cr, rtc->base + regs->cr);
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/* Clear event flag, otherwise new events won't be received */
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isr = readl_relaxed(rtc->base + STM32_RTC_ISR);
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isr &= ~STM32_RTC_ISR_ALRAF;
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writel_relaxed(isr, rtc->base + STM32_RTC_ISR);
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/* Clear event flags, otherwise new events won't be received */
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stm32_rtc_clear_event_flags(rtc, evts->alra);
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stm32_rtc_wpr_lock(rtc);
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@ -383,9 +411,10 @@ static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
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unsigned int dr = readl_relaxed(rtc->base + STM32_RTC_DR);
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unsigned int tr = readl_relaxed(rtc->base + STM32_RTC_TR);
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unsigned int dr = readl_relaxed(rtc->base + regs->dr);
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unsigned int tr = readl_relaxed(rtc->base + regs->tr);
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cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
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cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
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@ -419,6 +448,7 @@ static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
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static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct stm32_rtc *rtc = dev_get_drvdata(dev);
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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struct rtc_time *tm = &alrm->time;
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unsigned int cr, isr, alrmar;
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int ret = 0;
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@ -450,15 +480,15 @@ static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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stm32_rtc_wpr_unlock(rtc);
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/* Disable Alarm */
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cr = readl_relaxed(rtc->base + STM32_RTC_CR);
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cr = readl_relaxed(rtc->base + regs->cr);
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cr &= ~STM32_RTC_CR_ALRAE;
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writel_relaxed(cr, rtc->base + STM32_RTC_CR);
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writel_relaxed(cr, rtc->base + regs->cr);
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/*
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* Poll Alarm write flag to be sure that Alarm update is allowed: it
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* takes around 2 rtc_ck clock cycles
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*/
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ret = readl_relaxed_poll_timeout_atomic(rtc->base + STM32_RTC_ISR,
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ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
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isr,
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(isr & STM32_RTC_ISR_ALRAWF),
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10, 100000);
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@ -469,7 +499,7 @@ static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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}
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/* Write to Alarm register */
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writel_relaxed(alrmar, rtc->base + STM32_RTC_ALRMAR);
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writel_relaxed(alrmar, rtc->base + regs->alrmar);
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if (alrm->enabled)
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stm32_rtc_alarm_irq_enable(dev, 1);
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@ -490,14 +520,50 @@ static const struct rtc_class_ops stm32_rtc_ops = {
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.alarm_irq_enable = stm32_rtc_alarm_irq_enable,
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};
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static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
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unsigned int flags)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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/* Flags are cleared by writing 0 in RTC_ISR */
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writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
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rtc->base + regs->isr);
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}
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static const struct stm32_rtc_data stm32_rtc_data = {
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.has_pclk = false,
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.need_dbp = true,
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.regs = {
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.tr = 0x00,
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.dr = 0x04,
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.cr = 0x08,
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.isr = 0x0C,
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.prer = 0x10,
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.alrmar = 0x1C,
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.wpr = 0x24,
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},
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.events = {
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.alra = STM32_RTC_ISR_ALRAF,
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},
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.clear_events = stm32_rtc_clear_events,
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};
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static const struct stm32_rtc_data stm32h7_rtc_data = {
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.has_pclk = true,
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.need_dbp = true,
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.regs = {
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.tr = 0x00,
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.dr = 0x04,
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.cr = 0x08,
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.isr = 0x0C,
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.prer = 0x10,
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.alrmar = 0x1C,
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.wpr = 0x24,
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},
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.events = {
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.alra = STM32_RTC_ISR_ALRAF,
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},
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.clear_events = stm32_rtc_clear_events,
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};
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static const struct of_device_id stm32_rtc_of_match[] = {
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@ -510,6 +576,7 @@ MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
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static int stm32_rtc_init(struct platform_device *pdev,
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struct stm32_rtc *rtc)
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{
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const struct stm32_rtc_registers *regs = &rtc->data->regs;
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unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
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unsigned int rate;
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int ret = 0;
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@ -550,14 +617,14 @@ static int stm32_rtc_init(struct platform_device *pdev,
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}
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prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
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writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
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writel_relaxed(prer, rtc->base + regs->prer);
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prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
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writel_relaxed(prer, rtc->base + STM32_RTC_PRER);
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writel_relaxed(prer, rtc->base + regs->prer);
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/* Force 24h time format */
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cr = readl_relaxed(rtc->base + STM32_RTC_CR);
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cr = readl_relaxed(rtc->base + regs->cr);
|
||||
cr &= ~STM32_RTC_CR_FMT;
|
||||
writel_relaxed(cr, rtc->base + STM32_RTC_CR);
|
||||
writel_relaxed(cr, rtc->base + regs->cr);
|
||||
|
||||
stm32_rtc_exit_init_mode(rtc);
|
||||
|
||||
|
|
@ -571,6 +638,7 @@ end:
|
|||
static int stm32_rtc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_rtc *rtc;
|
||||
const struct stm32_rtc_registers *regs;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
|
|
@ -585,6 +653,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
|
|||
|
||||
rtc->data = (struct stm32_rtc_data *)
|
||||
of_device_get_match_data(&pdev->dev);
|
||||
regs = &rtc->data->regs;
|
||||
|
||||
if (rtc->data->need_dbp) {
|
||||
rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||
|
|
@ -688,7 +757,7 @@ static int stm32_rtc_probe(struct platform_device *pdev)
|
|||
* If INITS flag is reset (calendar year field set to 0x00), calendar
|
||||
* must be initialized
|
||||
*/
|
||||
if (!(readl_relaxed(rtc->base + STM32_RTC_ISR) & STM32_RTC_ISR_INITS))
|
||||
if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
|
||||
dev_warn(&pdev->dev, "Date/Time must be initialized\n");
|
||||
|
||||
return 0;
|
||||
|
|
@ -708,13 +777,14 @@ err:
|
|||
static int stm32_rtc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_rtc *rtc = platform_get_drvdata(pdev);
|
||||
const struct stm32_rtc_registers *regs = &rtc->data->regs;
|
||||
unsigned int cr;
|
||||
|
||||
/* Disable interrupts */
|
||||
stm32_rtc_wpr_unlock(rtc);
|
||||
cr = readl_relaxed(rtc->base + STM32_RTC_CR);
|
||||
cr = readl_relaxed(rtc->base + regs->cr);
|
||||
cr &= ~STM32_RTC_CR_ALRAIE;
|
||||
writel_relaxed(cr, rtc->base + STM32_RTC_CR);
|
||||
writel_relaxed(cr, rtc->base + regs->cr);
|
||||
stm32_rtc_wpr_lock(rtc);
|
||||
|
||||
clk_disable_unprepare(rtc->rtc_ck);
|
||||
|
|
|
|||
Loading…
Reference in New Issue