powerpc: Various typo fixes
Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Michael Ellerman
parent
e289086f65
commit
027dfac694
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@ -2,7 +2,7 @@ IBM OPAL real-time clock
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------------------------
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Required properties:
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- comapatible: Should be "ibm,opal-rtc"
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- compatible: Should be "ibm,opal-rtc"
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Optional properties:
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- wakeup-source: Decides if the wakeup is supported or not
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@ -18,7 +18,7 @@
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#define rLN r7 /* length of data to be processed */
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#define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */
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#define rKT r9 /* pointer to tweak key (XTS mode) */
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#define rT0 r11 /* pointers to en-/decrpytion tables */
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#define rT0 r11 /* pointers to en-/decryption tables */
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#define rT1 r10
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#define rD0 r9 /* data */
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#define rD1 r14
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@ -434,7 +434,7 @@ extern void slb_set_size(u16 size);
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* function. Used in slb_allocate() and do_stab_bolted. The function
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* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
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*
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* rt = register continaing the proto-VSID and into which the
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* rt = register containing the proto-VSID and into which the
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* VSID will be stored
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* rx = scratch register (clobbered)
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*
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@ -57,7 +57,7 @@ struct pci_dn;
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/*
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* The struct is used to trace PE related EEH functionality.
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* In theory, there will have one instance of the struct to
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* be created against particular PE. In nature, PEs corelate
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* be created against particular PE. In nature, PEs correlate
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* to each other. the struct has to reflect that hierarchy in
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* order to easily pick up those affected PEs when one particular
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* PE has EEH errors.
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@ -32,7 +32,7 @@
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* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
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*
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* Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
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* TLB2 storage attibute fields. Those are:
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* TLB2 storage attribute fields. Those are:
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*
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* TLB2:
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* 0...10 11 12 13 14 15 16...31
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@ -802,7 +802,7 @@ struct opal_sg_entry {
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};
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/*
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* Candiate image SG list.
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* Candidate image SG list.
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*
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* length = VER | length
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*/
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@ -852,7 +852,7 @@ struct opal_i2c_request {
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* with individual elements being 16 bits wide to fetch the system
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* wide EPOW status. Each element in the buffer will contain the
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* EPOW status in it's bit representation for a particular EPOW sub
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* class as defiend here. So multiple detailed EPOW status bits
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* class as defined here. So multiple detailed EPOW status bits
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* specific for any sub class can be represented in a single buffer
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* element as it's bit representation.
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*/
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@ -210,7 +210,7 @@ static inline long pmac_call_feature(int selector, struct device_node* node,
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/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
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* enable/disable the sound chip, whatever it is and provided it can
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* acually be controlled
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* actually be controlled
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*/
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#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
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@ -224,7 +224,7 @@ struct thread_struct {
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unsigned int align_ctl; /* alignment handling control */
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#ifdef CONFIG_PPC64
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unsigned long start_tb; /* Start purr when proc switched in */
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unsigned long accum_tb; /* Total accumilated purr for process */
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unsigned long accum_tb; /* Total accumulated purr for process */
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct perf_event *ptrace_bps[HBP_NUM];
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/*
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@ -104,7 +104,7 @@
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#define PS3AV_CMD_AV_INPUTLEN_16 0x02
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#define PS3AV_CMD_AV_INPUTLEN_20 0x0a
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#define PS3AV_CMD_AV_INPUTLEN_24 0x0b
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/* alayout */
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/* av_layout */
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#define PS3AV_CMD_AV_LAYOUT_32 (1 << 0)
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#define PS3AV_CMD_AV_LAYOUT_44 (1 << 1)
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#define PS3AV_CMD_AV_LAYOUT_48 (1 << 2)
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@ -96,7 +96,7 @@ static inline bool pte_user(pte_t pte)
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#define PTE_RPN_SHIFT (PAGE_SHIFT)
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#endif
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/* The mask convered by the RPN must be a ULL on 32-bit platforms with
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/* The mask covered by the RPN must be a ULL on 32-bit platforms with
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* 64-bit PTEs
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*/
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#if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
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@ -185,7 +185,7 @@
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* x = processor mask
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* y = op. point index
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* z = processor freq. step index
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* I haven't yet decyphered result codes
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* I haven't yet deciphered result codes
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*
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*/
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#define SMU_CMD_POWER_COMMAND 0xaa
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@ -77,7 +77,7 @@
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* nodes if your board uses the Broadcom PHYs
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*/
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#define TSI108_PHY_MV88E 0 /* Marvel 88Exxxx PHY */
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#define TSI108_PHY_BCM54XX 1 /* Broardcom BCM54xx PHY */
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#define TSI108_PHY_BCM54XX 1 /* Broadcom BCM54xx PHY */
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/* Global variables */
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@ -156,7 +156,7 @@ setup_7410_workarounds:
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blr
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/* 740/750/7400/7410
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* Enable Store Gathering (SGE), Address Brodcast (ABE),
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* Enable Store Gathering (SGE), Address Broadcast (ABE),
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* Branch History Table (BHTE), Branch Target ICache (BTIC)
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* Dynamic Power Management (DPM), Speculative (SPD)
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* Clear Instruction cache throttling (ICTC)
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@ -139,7 +139,7 @@ static void eeh_enable_irq(struct pci_dev *dev)
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* into it.
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*
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* That's just wrong.The warning in the core code is
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* there to tell people to fix their assymetries in
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* there to tell people to fix their asymmetries in
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* their own code, not by abusing the core information
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* to avoid it.
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*
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@ -453,7 +453,7 @@ exc_##n##_bad_stack: \
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sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
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b bad_stack_book3e; /* bad stack error */
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/* WARNING: If you change the layout of this stub, make sure you chcek
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/* WARNING: If you change the layout of this stub, make sure you check
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* the debug exception handler which handles single stepping
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* into exceptions from userspace, and the MM code in
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* arch/powerpc/mm/tlb_nohash.c which patches the branch here
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@ -82,7 +82,7 @@ int pcibios_unmap_io_space(struct pci_bus *bus)
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/* If this is not a PHB, we only flush the hash table over
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* the area mapped by this bridge. We don't play with the PTE
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* mappings since we might have to deal with sub-page alignemnts
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* mappings since we might have to deal with sub-page alignments
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* so flushing the hash table is the only sane way to make sure
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* that no hash entries are covering that removed bridge area
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* while still allowing other busses overlapping those pages
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@ -802,7 +802,7 @@ static void tm_reclaim_thread(struct thread_struct *thr,
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* this state.
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* We do this using the current MSR, rather tracking it in
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* some specific thread_struct bit, as it has the additional
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* benifit of checking for a potential TM bad thing exception.
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* benefit of checking for a potential TM bad thing exception.
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*/
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if (!MSR_TM_SUSPENDED(mfmsr()))
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return;
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@ -698,7 +698,7 @@ static void check_location(struct seq_file *m, const char *c)
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/*
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* Format:
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* ${LETTER}${NUMBER}[[-/]${LETTER}${NUMBER} [ ... ] ]
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* the '.' may be an abbrevation
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* the '.' may be an abbreviation
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*/
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static void check_location_string(struct seq_file *m, const char *c)
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{
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@ -325,7 +325,7 @@ void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks,
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}
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EXPORT_SYMBOL_GPL(rh_init);
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/* Attach a free memory region, coalesces regions if adjuscent */
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/* Attach a free memory region, coalesces regions if adjacent */
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int rh_attach_region(rh_info_t * info, unsigned long start, int size)
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{
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rh_block_t *blk;
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@ -55,7 +55,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
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* We need 14 to 65 bits of va for a tlibe of 4K page
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* With vpn we ignore the lower VPN_SHIFT bits already.
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* And top two bits are already ignored because we can
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* only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
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* only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
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* of 12.
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*/
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va = vpn << VPN_SHIFT;
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@ -605,7 +605,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
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* crashdump and all bets are off anyway.
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*
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* TODO: add batching support when enabled. remember, no dynamic memory here,
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* athough there is the control page available...
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* although there is the control page available...
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*/
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static void native_hpte_clear(void)
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{
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@ -51,7 +51,7 @@ static void spu_buff_add(unsigned long int value, int spu)
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* That way we can tell the difference between the
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* buffer being full versus empty.
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*
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* ASSUPTION: the buffer_lock is held when this function
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* ASSUMPTION: the buffer_lock is held when this function
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* is called to lock the buffer, head and tail.
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*/
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int full = 1;
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@ -992,7 +992,7 @@ static u64 check_and_compute_delta(u64 prev, u64 val)
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* than the previous value it will cause the delta and the counter to
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* have bogus values unless we rolled a counter over. If a coutner is
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* rolled back, it will be smaller, but within 256, which is the maximum
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* number of events to rollback at once. If we dectect a rollback
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* number of events to rollback at once. If we detect a rollback
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* return 0. This can lead to a small lack of precision in the
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* counters.
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*/
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@ -1298,7 +1298,7 @@ static void h_24x7_event_read(struct perf_event *event)
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__this_cpu_write(hv_24x7_txn_err, ret);
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} else {
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/*
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* Assoicate the event with the HCALL request index,
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* Associate the event with the HCALL request index,
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* so ->commit_txn() can quickly find/update count.
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*/
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i = request_buffer->num_requests - 1;
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@ -66,7 +66,7 @@ struct hv_24x7_result_element {
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/* -1 if @performance_domain does not refer to a virtual processor */
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__be32 lpar_cfg_instance_id;
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/* size = @result_element_data_size of cointaining result. */
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/* size = @result_element_data_size of containing result. */
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__u64 element_data[1];
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} __packed;
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@ -719,7 +719,7 @@ static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq)
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* most one of a mux, div, and gate each into one 'struct clk'
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* item
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* - PSC/MSCAN/SPDIF clock generation OTOH already is very
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* specific and cannot get mapped to componsites (at least not
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* specific and cannot get mapped to composites (at least not
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* a single one, maybe two of them, but then some of these
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* intermediate clock signals get referenced elsewhere (e.g.
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* in the clock frequency measurement, CFM) and thus need
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@ -178,7 +178,7 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
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* default for now.*/
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#ifdef CELL_IOMMU_STRICT_PROTECTION
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/* to avoid referencing a global, we use a trick here to setup the
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* protection bit. "prot" is setup to be 3 fields of 4 bits apprended
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* protection bit. "prot" is setup to be 3 fields of 4 bits appended
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* together for each of the 3 supported direction values. It is then
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* shifted left so that the fields matching the desired direction
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* lands on the appropriate bits, and other bits are masked out.
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@ -338,7 +338,7 @@ static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
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start_seg = base >> IO_SEGMENT_SHIFT;
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segments = size >> IO_SEGMENT_SHIFT;
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pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
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/* PTEs for each segment must start on a 4K bounday */
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/* PTEs for each segment must start on a 4K boundary */
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pages_per_segment = max(pages_per_segment,
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(1 << 12) / sizeof(unsigned long));
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@ -217,7 +217,7 @@ static void spider_irq_cascade(struct irq_desc *desc)
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chip->irq_eoi(&desc->irq_data);
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}
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/* For hooking up the cascace we have a problem. Our device-tree is
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/* For hooking up the cascade we have a problem. Our device-tree is
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* crap and we don't know on which BE iic interrupt we are hooked on at
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* least not the "standard" way. We can reconstitute it based on two
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* informations though: which BE node we are connected to and whether
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@ -69,7 +69,7 @@ static DEFINE_SPINLOCK(spu_lock);
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* spu_full_list_lock and spu_full_list_mutex held, while iterating
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* through it requires either of these locks.
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*
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* In addition spu_full_list_lock protects all assignmens to
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* In addition spu_full_list_lock protects all assignments to
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* spu->mm.
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*/
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static LIST_HEAD(spu_full_list);
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@ -253,7 +253,7 @@ static inline int __slb_present(struct copro_slb *slbs, int nr_slbs,
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* Setup the SPU kernel SLBs, in preparation for a context save/restore. We
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* need to map both the context save area, and the save/restore code.
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*
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* Because the lscsa and code may cross segment boundaires, we check to see
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* Because the lscsa and code may cross segment boundaries, we check to see
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* if mappings are required for the start and end of each range. We currently
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* assume that the mappings are smaller that one segment - if not, something
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* is seriously wrong.
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@ -866,7 +866,7 @@ void spufs_wbox_callback(struct spu *spu)
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* - end of the mapped area
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*
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* If the file is opened without O_NONBLOCK, we wait here until
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* space is availabyl, but return when we have been able to
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* space is available, but return when we have been able to
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* write something.
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*/
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static ssize_t spufs_wbox_write(struct file *file, const char __user *buf,
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@ -435,7 +435,7 @@ long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *event)
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/* Note: we don't need to force_sig SIGTRAP on single-step
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* since we have TIF_SINGLESTEP set, thus the kernel will do
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* it upon return from the syscall anyawy
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* it upon return from the syscall anyway.
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*/
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if (unlikely(status & SPU_STATUS_SINGLE_STEP))
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ret = -ERESTARTSYS;
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@ -622,7 +622,7 @@ static struct spu *spu_get_idle(struct spu_context *ctx)
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/**
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* find_victim - find a lower priority context to preempt
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* @ctx: canidate context for running
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* @ctx: candidate context for running
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*
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* Returns the freed physical spu to run the new context on.
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*/
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@ -15,7 +15,7 @@
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* This file thus provides a simple low level unified i2c interface for
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* powermac that covers the various types of i2c busses used in Apple machines.
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* For now, keywest, PMU and SMU, though we could add Cuda, or other bit
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* banging busses found on older chipstes in earlier machines if we ever need
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* banging busses found on older chipsets in earlier machines if we ever need
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* one of them.
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*
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* The drivers in this file are synchronous/blocking. In addition, the
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@ -197,7 +197,7 @@ static int pnv_ioda2_init_m64(struct pnv_phb *phb)
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/*
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* Strip off the segment used by the reserved PE, which is
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* expected to be 0 or last one of PE capabicity.
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* expected to be 0 or last one of PE capability.
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*/
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r = &phb->hose->mem_resources[1];
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if (phb->ioda.reserved_pe_idx == 0)
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@ -2,7 +2,7 @@
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* The file intends to implement the platform dependent EEH operations on pseries.
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* Actually, the pseries platform is built based on RTAS heavily. That means the
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* pseries platform dependent EEH operations will be built on RTAS calls. The functions
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* are devired from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
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* are derived from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
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* been done.
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*
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* Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
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@ -113,7 +113,7 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
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* - The owner of an event is determined by combinations of scope,
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* event type, and sub-type. There is no easy way to pre-sort clients
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* by scope or event type alone. For example, Torrent ISR route change
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* event is reported with scope 0x00 (Not Applicatable) rather than
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* event is reported with scope 0x00 (Not Applicable) rather than
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* 0x3B (Torrent-hub). It is better to let the clients to identify
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* who owns the event.
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*/
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@ -367,7 +367,7 @@ static void pseries_lpar_idle(void)
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{
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||||
/*
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* Default handler to go into low thread priority and possibly
|
||||
* low power mode by cedeing processor to hypervisor
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||||
* low power mode by ceding processor to hypervisor
|
||||
*/
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||||
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||||
/* Indicate to hypervisor that we are idle. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue