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spi/rockchip: fix endian mode for 16-bit transfers 

16-bit transfers must be in big endian mode on wire.

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Alexander Kochetkov 2016-03-06 13:04:17 +03:00 committed by Mark Brown
parent b920cc3191
commit 0277e01aeb
1 changed files with 2 additions and 1 deletions
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3
drivers/spi/spi-rockchip.c
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@ -506,7 +506,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
int rsd = 0;
u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
| (CR0_SSD_ONE << CR0_SSD_OFFSET);
| (CR0_SSD_ONE << CR0_SSD_OFFSET)
| (CR0_EM_BIG << CR0_EM_OFFSET);
cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);