microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver
Modify the Microblaze PCI subsystem to work with the generic drivers/pci/host/pcie-xilinx.c driver on Microblaze and Zynq. [bhelgaas: changelog] Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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@ -267,6 +267,9 @@ config PCI
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config PCI_DOMAINS
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def_bool PCI
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config PCI_DOMAINS_GENERIC
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def_bool PCI_DOMAINS
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config PCI_SYSCALL
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def_bool PCI
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@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
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}
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EXPORT_SYMBOL_GPL(pci_address_to_pio);
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/*
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* Return the domain number for this bus.
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*/
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int pci_domain_nr(struct pci_bus *bus)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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return hose->global_number;
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}
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EXPORT_SYMBOL(pci_domain_nr);
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/* This routine is meant to be used early during boot, when the
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* PCI bus numbers have not yet been assigned, and you need to
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* issue PCI config cycles to an OF device.
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@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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/* When called from the generic PCI probe, read PCI<->PCI bridge
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* bases. This is -not- called when generating the PCI tree from
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* the OF device-tree.
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*/
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if (bus->self != NULL)
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pci_read_bridge_bases(bus);
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/* Now fixup the bus bus */
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pcibios_setup_bus_self(bus);
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/* Now fixup devices on that bus */
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pcibios_setup_bus_devices(bus);
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/* nothing to do */
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}
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EXPORT_SYMBOL(pcibios_fixup_bus);
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static int skip_isa_ioresource_align(struct pci_dev *dev)
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{
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return 0;
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}
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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@ -899,20 +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (skip_isa_ioresource_align(dev))
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return start;
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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}
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return start;
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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int pcibios_add_device(struct pci_dev *dev)
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{
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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return 0;
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}
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EXPORT_SYMBOL(pcibios_add_device);
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/*
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* Reparent resource children of pr that conflict with res
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* under res, and make res replace those children.
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@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
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(unsigned long)hose->io_base_virt - _IO_BASE);
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}
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return of_node_get(hose->dn);
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}
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static void pcibios_scan_phb(struct pci_controller *hose)
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{
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LIST_HEAD(resources);
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@ -81,7 +81,7 @@ config PCI_KEYSTONE
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config PCIE_XILINX
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bool "Xilinx AXI PCIe host bridge support"
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depends on ARCH_ZYNQ
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depends on ARCH_ZYNQ || MICROBLAZE
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help
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Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
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Host Bridge driver.
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