KVM: SVM: use explicit 64bit storage for sysenter values
Since AMD does not support sysenter in 64bit mode, the VMCB fields storing the MSRs are truncated to 32bit upon VMRUN/#VMEXIT. So store the values in a separate 64bit storage to avoid truncation. [andre: fix amd->amd migration] Signed-off-by: Christoph Egger <christoph.egger@amd.com> Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -27,6 +27,8 @@ struct vcpu_svm {
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unsigned long vmcb_pa;
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struct svm_cpu_data *svm_data;
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uint64_t asid_generation;
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uint64_t sysenter_esp;
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uint64_t sysenter_eip;
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u64 next_rip;
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@ -367,8 +367,6 @@ static void svm_vcpu_init_msrpm(u32 *msrpm)
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#endif
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set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
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set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
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}
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static void svm_enable_lbrv(struct vcpu_svm *svm)
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@ -1981,10 +1979,10 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
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*data = svm->vmcb->save.sysenter_cs;
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break;
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case MSR_IA32_SYSENTER_EIP:
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*data = svm->vmcb->save.sysenter_eip;
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*data = svm->sysenter_eip;
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break;
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case MSR_IA32_SYSENTER_ESP:
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*data = svm->vmcb->save.sysenter_esp;
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*data = svm->sysenter_esp;
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break;
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/* Nobody will change the following 5 values in the VMCB so
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we can safely return them on rdmsr. They will always be 0
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@ -2071,9 +2069,11 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
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svm->vmcb->save.sysenter_cs = data;
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break;
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case MSR_IA32_SYSENTER_EIP:
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svm->sysenter_eip = data;
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svm->vmcb->save.sysenter_eip = data;
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break;
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case MSR_IA32_SYSENTER_ESP:
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svm->sysenter_esp = data;
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svm->vmcb->save.sysenter_esp = data;
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break;
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case MSR_IA32_DEBUGCTLMSR:
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