From 017210d1c0dc2e2d3b142985cb31d90b98dc0f0f Mon Sep 17 00:00:00 2001 From: Paul Osmialowski Date: Wed, 4 Feb 2015 10:16:59 +0100 Subject: [PATCH] mmc: sdhci-s3c: solve problem with sleeping in atomic context This change addresses following problem: [ 2.560726] ------------[ cut here ]------------ [ 2.565341] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2744 lockdep_trace_alloc+0xec/0x118() [ 2.574439] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) [ 2.579821] Modules linked in: [ 2.583038] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.18.0-next-20141216-00002-g4ff197fc1902-dirty #1318 [ 2.593796] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 2.599892] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 2.607612] [] (show_stack) from [] (dump_stack+0x70/0xbc) [ 2.614822] [] (dump_stack) from [] (warn_slowpath_common+0x74/0xb0) [ 2.622885] [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) [ 2.631569] [] (warn_slowpath_fmt) from [] (lockdep_trace_alloc+0xec/0x118) [ 2.640246] [] (lockdep_trace_alloc) from [] (__kmalloc+0x3c/0x1cc) [ 2.648240] [] (__kmalloc) from [] (clk_fetch_parent_index+0xb8/0xd4) [ 2.656390] [] (clk_fetch_parent_index) from [] (clk_calc_new_rates+0xe0/0x1fc) [ 2.665415] [] (clk_calc_new_rates) from [] (clk_calc_new_rates+0x1b4/0x1fc) [ 2.674181] [] (clk_calc_new_rates) from [] (clk_set_rate+0x50/0xc8) [ 2.682265] [] (clk_set_rate) from [] (sdhci_cmu_set_clock+0x68/0x16c) [ 2.690503] [] (sdhci_cmu_set_clock) from [] (sdhci_do_set_ios+0xf0/0x64c) [ 2.699095] [] (sdhci_do_set_ios) from [] (sdhci_set_ios+0x20/0x2c) [ 2.707080] [] (sdhci_set_ios) from [] (mmc_power_up+0x118/0x1fc) [ 2.714889] [] (mmc_power_up) from [] (mmc_start_host+0x44/0x6c) [ 2.722615] [] (mmc_start_host) from [] (mmc_add_host+0x58/0x7c) [ 2.730341] [] (mmc_add_host) from [] (sdhci_add_host+0x968/0xd94) [ 2.738240] [] (sdhci_add_host) from [] (sdhci_s3c_probe+0x354/0x52c) [ 2.746406] [] (sdhci_s3c_probe) from [] (platform_drv_probe+0x48/0xa4) [ 2.754733] [] (platform_drv_probe) from [] (driver_probe_device+0x13c/0x37c) [ 2.763585] [] (driver_probe_device) from [] (__driver_attach+0x94/0x98) [ 2.772003] [] (__driver_attach) from [] (bus_for_each_dev+0x54/0x88) [ 2.780163] [] (bus_for_each_dev) from [] (bus_add_driver+0xe4/0x200) [ 2.788322] [] (bus_add_driver) from [] (driver_register+0x78/0xf4) [ 2.796308] [] (driver_register) from [] (do_one_initcall+0xac/0x1f0) [ 2.804473] [] (do_one_initcall) from [] (kernel_init_freeable+0x10c/0x1d8) [ 2.813153] [] (kernel_init_freeable) from [] (kernel_init+0x28/0x108) [ 2.821398] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c) [ 2.828939] ---[ end trace 03cc00e539849d1f ]--- clk_set_rate() tries to take clk's prepare_lock mutex while being in atomic context entered in sdhci_do_set_ios(). The solution is inspired by similar situation in sdhci_set_power() also called from sdhci_do_set_ios(): spin_unlock_irq(&host->lock); mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); spin_lock_irq(&host->lock); Note that since sdhci_s3c_set_clock() sets SDHCI_CLOCK_CARD_EN, proposed change first resets this bit. It is reset anyway (by setting SDHCI_CLOCK_INT_EN bit only) after call to clk_set_rate() in order to wait for the clock to stabilize and is set again as soon as the clock becomes stable. Signed-off-by: Paul Osmialowski Tested-by: Jaehoon Chung Acked-by: Jaehoon Chung Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-s3c.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index a2828222709c..c6d2dd7317c1 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -312,7 +313,14 @@ static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_s3c_set_clock(host, clock); + /* Reset SD Clock Enable */ + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + spin_unlock_irq(&host->lock); ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); + spin_lock_irq(&host->lock); if (ret != 0) { dev_err(dev, "%s: failed to set clock rate %uHz\n", mmc_hostname(host->mmc), clock);