metag: Fix ioremap_wc/ioremap_cached build errors
When ioremap_wc() or ioremap_cached() are used without first including asm/pgtable.h, the _PAGE_CACHEABLE or _PAGE_WR_COMBINE definitions aren't found, resulting in build errors like the following (in next-20150323 due to "lib: devres: add a helper function for ioremap_wc"): lib/devres.c: In function ‘devm_ioremap_wc’: lib/devres.c:91: error: ‘_PAGE_WR_COMBINE’ undeclared We can't easily include asm/pgtable.h in asm/io.h due to dependency problems, so split out the _PAGE_* definitions from asm/pgtable.h into a separate asm/pgtable-bits.h header (as a couple of other architectures already do), and include that in io.h instead. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-metag@vger.kernel.org Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
James Hogan
parent
9eccca0843
commit
0164a711c9
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@ -2,6 +2,7 @@
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#define _ASM_METAG_IO_H
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#include <linux/types.h>
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#include <asm/pgtable-bits.h>
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#define IO_SPACE_LIMIT 0
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@ -0,0 +1,104 @@
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/*
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* Meta page table definitions.
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*/
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#ifndef _METAG_PGTABLE_BITS_H
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#define _METAG_PGTABLE_BITS_H
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#include <asm/metag_mem.h>
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/*
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* Definitions for MMU descriptors
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*
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* These are the hardware bits in the MMCU pte entries.
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* Derived from the Meta toolkit headers.
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*/
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#define _PAGE_PRESENT MMCU_ENTRY_VAL_BIT
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#define _PAGE_WRITE MMCU_ENTRY_WR_BIT
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#define _PAGE_PRIV MMCU_ENTRY_PRIV_BIT
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/* Write combine bit - this can cause writes to occur out of order */
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#define _PAGE_WR_COMBINE MMCU_ENTRY_WRC_BIT
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/* Sys coherent bit - this bit is never used by Linux */
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#define _PAGE_SYS_COHERENT MMCU_ENTRY_SYS_BIT
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#define _PAGE_ALWAYS_ZERO_1 0x020
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#define _PAGE_CACHE_CTRL0 0x040
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#define _PAGE_CACHE_CTRL1 0x080
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#define _PAGE_ALWAYS_ZERO_2 0x100
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#define _PAGE_ALWAYS_ZERO_3 0x200
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#define _PAGE_ALWAYS_ZERO_4 0x400
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#define _PAGE_ALWAYS_ZERO_5 0x800
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/* These are software bits that we stuff into the gaps in the hardware
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* pte entries that are not used. Note, these DO get stored in the actual
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* hardware, but the hardware just does not use them.
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*/
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#define _PAGE_ACCESSED _PAGE_ALWAYS_ZERO_1
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#define _PAGE_DIRTY _PAGE_ALWAYS_ZERO_2
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/* Pages owned, and protected by, the kernel. */
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#define _PAGE_KERNEL _PAGE_PRIV
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/* No cacheing of this page */
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#define _PAGE_CACHE_WIN0 (MMCU_CWIN_UNCACHED << MMCU_ENTRY_CWIN_S)
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/* burst cacheing - good for data streaming */
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#define _PAGE_CACHE_WIN1 (MMCU_CWIN_BURST << MMCU_ENTRY_CWIN_S)
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/* One cache way per thread */
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#define _PAGE_CACHE_WIN2 (MMCU_CWIN_C1SET << MMCU_ENTRY_CWIN_S)
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/* Full on cacheing */
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#define _PAGE_CACHE_WIN3 (MMCU_CWIN_CACHED << MMCU_ENTRY_CWIN_S)
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#define _PAGE_CACHEABLE (_PAGE_CACHE_WIN3 | _PAGE_WR_COMBINE)
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/* which bits are used for cache control ... */
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#define _PAGE_CACHE_MASK (_PAGE_CACHE_CTRL0 | _PAGE_CACHE_CTRL1 | \
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_PAGE_WR_COMBINE)
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/* This is a mask of the bits that pte_modify is allowed to change. */
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#define _PAGE_CHG_MASK (PAGE_MASK)
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#define _PAGE_SZ_SHIFT 1
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#define _PAGE_SZ_4K (0x0)
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#define _PAGE_SZ_8K (0x1 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_16K (0x2 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_32K (0x3 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_64K (0x4 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_128K (0x5 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_256K (0x6 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_512K (0x7 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_1M (0x8 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_2M (0x9 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_4M (0xa << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_MASK (0xf << _PAGE_SZ_SHIFT)
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#if defined(CONFIG_PAGE_SIZE_4K)
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#define _PAGE_SZ (_PAGE_SZ_4K)
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#elif defined(CONFIG_PAGE_SIZE_8K)
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#define _PAGE_SZ (_PAGE_SZ_8K)
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#elif defined(CONFIG_PAGE_SIZE_16K)
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#define _PAGE_SZ (_PAGE_SZ_16K)
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#endif
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#define _PAGE_TABLE (_PAGE_SZ | _PAGE_PRESENT)
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#if defined(CONFIG_HUGETLB_PAGE_SIZE_8K)
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# define _PAGE_SZHUGE (_PAGE_SZ_8K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_16K)
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# define _PAGE_SZHUGE (_PAGE_SZ_16K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_32K)
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# define _PAGE_SZHUGE (_PAGE_SZ_32K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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# define _PAGE_SZHUGE (_PAGE_SZ_64K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_128K)
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# define _PAGE_SZHUGE (_PAGE_SZ_128K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
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# define _PAGE_SZHUGE (_PAGE_SZ_256K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
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# define _PAGE_SZHUGE (_PAGE_SZ_512K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1M)
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# define _PAGE_SZHUGE (_PAGE_SZ_1M)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_2M)
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# define _PAGE_SZHUGE (_PAGE_SZ_2M)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4M)
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# define _PAGE_SZHUGE (_PAGE_SZ_4M)
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#endif
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#endif /* _METAG_PGTABLE_BITS_H */
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@ -5,6 +5,7 @@
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#ifndef _METAG_PGTABLE_H
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#define _METAG_PGTABLE_H
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#include <asm/pgtable-bits.h>
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#include <asm-generic/pgtable-nopmd.h>
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/* Invalid regions on Meta: 0x00000000-0x001FFFFF and 0xFFFF0000-0xFFFFFFFF */
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@ -20,100 +21,6 @@
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#define VMALLOC_END 0x7FFFFFFF
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#endif
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/*
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* Definitions for MMU descriptors
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*
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* These are the hardware bits in the MMCU pte entries.
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* Derived from the Meta toolkit headers.
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*/
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#define _PAGE_PRESENT MMCU_ENTRY_VAL_BIT
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#define _PAGE_WRITE MMCU_ENTRY_WR_BIT
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#define _PAGE_PRIV MMCU_ENTRY_PRIV_BIT
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/* Write combine bit - this can cause writes to occur out of order */
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#define _PAGE_WR_COMBINE MMCU_ENTRY_WRC_BIT
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/* Sys coherent bit - this bit is never used by Linux */
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#define _PAGE_SYS_COHERENT MMCU_ENTRY_SYS_BIT
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#define _PAGE_ALWAYS_ZERO_1 0x020
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#define _PAGE_CACHE_CTRL0 0x040
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#define _PAGE_CACHE_CTRL1 0x080
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#define _PAGE_ALWAYS_ZERO_2 0x100
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#define _PAGE_ALWAYS_ZERO_3 0x200
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#define _PAGE_ALWAYS_ZERO_4 0x400
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#define _PAGE_ALWAYS_ZERO_5 0x800
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/* These are software bits that we stuff into the gaps in the hardware
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* pte entries that are not used. Note, these DO get stored in the actual
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* hardware, but the hardware just does not use them.
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*/
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#define _PAGE_ACCESSED _PAGE_ALWAYS_ZERO_1
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#define _PAGE_DIRTY _PAGE_ALWAYS_ZERO_2
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/* Pages owned, and protected by, the kernel. */
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#define _PAGE_KERNEL _PAGE_PRIV
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/* No cacheing of this page */
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#define _PAGE_CACHE_WIN0 (MMCU_CWIN_UNCACHED << MMCU_ENTRY_CWIN_S)
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/* burst cacheing - good for data streaming */
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#define _PAGE_CACHE_WIN1 (MMCU_CWIN_BURST << MMCU_ENTRY_CWIN_S)
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/* One cache way per thread */
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#define _PAGE_CACHE_WIN2 (MMCU_CWIN_C1SET << MMCU_ENTRY_CWIN_S)
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/* Full on cacheing */
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#define _PAGE_CACHE_WIN3 (MMCU_CWIN_CACHED << MMCU_ENTRY_CWIN_S)
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#define _PAGE_CACHEABLE (_PAGE_CACHE_WIN3 | _PAGE_WR_COMBINE)
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/* which bits are used for cache control ... */
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#define _PAGE_CACHE_MASK (_PAGE_CACHE_CTRL0 | _PAGE_CACHE_CTRL1 | \
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_PAGE_WR_COMBINE)
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/* This is a mask of the bits that pte_modify is allowed to change. */
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#define _PAGE_CHG_MASK (PAGE_MASK)
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#define _PAGE_SZ_SHIFT 1
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#define _PAGE_SZ_4K (0x0)
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#define _PAGE_SZ_8K (0x1 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_16K (0x2 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_32K (0x3 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_64K (0x4 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_128K (0x5 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_256K (0x6 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_512K (0x7 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_1M (0x8 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_2M (0x9 << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_4M (0xa << _PAGE_SZ_SHIFT)
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#define _PAGE_SZ_MASK (0xf << _PAGE_SZ_SHIFT)
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#if defined(CONFIG_PAGE_SIZE_4K)
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#define _PAGE_SZ (_PAGE_SZ_4K)
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#elif defined(CONFIG_PAGE_SIZE_8K)
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#define _PAGE_SZ (_PAGE_SZ_8K)
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#elif defined(CONFIG_PAGE_SIZE_16K)
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#define _PAGE_SZ (_PAGE_SZ_16K)
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#endif
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#define _PAGE_TABLE (_PAGE_SZ | _PAGE_PRESENT)
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#if defined(CONFIG_HUGETLB_PAGE_SIZE_8K)
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# define _PAGE_SZHUGE (_PAGE_SZ_8K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_16K)
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# define _PAGE_SZHUGE (_PAGE_SZ_16K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_32K)
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# define _PAGE_SZHUGE (_PAGE_SZ_32K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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# define _PAGE_SZHUGE (_PAGE_SZ_64K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_128K)
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# define _PAGE_SZHUGE (_PAGE_SZ_128K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
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# define _PAGE_SZHUGE (_PAGE_SZ_256K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
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# define _PAGE_SZHUGE (_PAGE_SZ_512K)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1M)
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# define _PAGE_SZHUGE (_PAGE_SZ_1M)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_2M)
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# define _PAGE_SZHUGE (_PAGE_SZ_2M)
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4M)
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# define _PAGE_SZHUGE (_PAGE_SZ_4M)
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#endif
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* Meta, we use that, but "fold" the mid level into the top-level page
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