Merge branch 'drm-fixes-intel' of git://people.freedesktop.org/~airlied/linux
Pull drm update from Dave Airlie:
"This pull just contains a forward of the Intel fixes from Daniel.
The only annoyance is the RC6 enable, which really should have made
-next, but since Ubuntu are shipping it I reckon its getting a good
testing now by the time 3.4 comes out.
The pull from Daniel contains his pull message to me:
"A few patches for 3.4, major part is 3 regression fixes:
- ppgtt broke hibernate on snb/ivb. Somehow our QA claims that it
still works, which is why this has not been caught earlier.
- ppgtt flails in combination with dmar. I kinda expected this one :(
- fence handling bugfix for gen2/3. Iirc this one is about a year
old, fix curtesy Chris Wilson. I've created an shockingly simple
i-g-t test to catch this in the future."
Wrt regressions I've just got a report that gmbus (newly enabled
again in 3.4) is a bit noisy. I'm looking into this atm.
Also included are the rc6 enable patches for snb from Eugeni. I
wanted to include these in the main 3.4 pull but screwed it up.
Please hit me. Imo these kind of patches really should go in
before -rc1, but in thise case rc6 has brought us tons of press and
guinea pigs^W^W testers and ubuntu is already running with it. So
I estimate a pretty small chance for this to blow up.
And some smaller things:
- two minor locking snafus
- server gt2 ivb pciid
- 2 patches to sanitize the register state left behind by the bios
some more
- 2 new quirk entries
- cs readback trick against missed IRQs from ivb also enabled on snb
- sprite fix from Jesse"
Let's see if the "enable RC6 on sandybridge" finally works and sticks.
I've been enabling it by hand (i915.i915_enable_rc6=1) for several
months on my Macbook Air, and it definitely makes a difference (and has
worked for me). But every time we enabled it before it showed some odd
hw buglet for *somebody*.
This time it's all good, I'm sure.
* 'drm-fixes-intel' of git://people.freedesktop.org/~airlied/linux:
drm/i915: treat src w & h as fixed point in sprite handling code
drm/i915: no-lvds quirk on MSI DC500
drm/i915: Add lock on drm_helper_resume_force_mode
drm/i915: don't leak struct_mutex lock on ppgtt init failures
drm/i915: disable ppgtt on snb when dmar is enabled
drm/i915: add Ivy Bridge GT2 Server entries
drm/i915: properly clear SSC1 bit in the pch refclock init code
drm/i915: apply CS reg readback trick against missed IRQ on snb
drm/i915: quirk away broken OpRegion VBT
drm/i915: enable plain RC6 on Sandy Bridge by default
drm/i915: allow to select rc6 modes via kernel parameter
drm/i915: Mark untiled BLT commands as fenced on gen2/3
drm/i915: properly restore the ppgtt page directory on resume
drm/i915: Sanitize BIOS debugging bits from PIPECONF
This commit is contained in:
Linus Torvalds
commit
01627d968c
|
|
@ -234,6 +234,7 @@
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|||
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
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#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
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int intel_gmch_probe(struct pci_dev *pdev,
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struct agp_bridge_data *bridge);
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|
|
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|||
|
|
@ -1190,7 +1190,6 @@ static inline int needs_idle_maps(void)
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{
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#ifdef CONFIG_INTEL_IOMMU
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const unsigned short gpu_devid = intel_private.pcidev->device;
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extern int intel_iommu_gfx_mapped;
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/* Query intel_iommu to see if we need the workaround. Presumably that
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* was loaded first.
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|
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@ -1459,6 +1458,8 @@ static const struct intel_gtt_driver_description {
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"Ivybridge", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
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"Ivybridge", &sandybridge_gtt_driver },
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{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
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"Ivybridge", &sandybridge_gtt_driver },
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{ 0, NULL, NULL }
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};
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|
|
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|
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@ -1183,6 +1183,21 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
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return can_switch;
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}
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static bool
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intel_enable_ppgtt(struct drm_device *dev)
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{
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if (i915_enable_ppgtt >= 0)
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return i915_enable_ppgtt;
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#ifdef CONFIG_INTEL_IOMMU
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/* Disable ppgtt on SNB if VT-d is on. */
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if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
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return false;
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#endif
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return true;
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}
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static int i915_load_gem_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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|
|
@ -1197,7 +1212,7 @@ static int i915_load_gem_init(struct drm_device *dev)
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drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
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mutex_lock(&dev->struct_mutex);
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if (i915_enable_ppgtt && HAS_ALIASING_PPGTT(dev)) {
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if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
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/* PPGTT pdes are stolen from global gtt ptes, so shrink the
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* aperture accordingly when using aliasing ppgtt. */
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gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
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|
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@ -1207,8 +1222,10 @@ static int i915_load_gem_init(struct drm_device *dev)
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i915_gem_do_init(dev, 0, mappable_size, gtt_size);
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ret = i915_gem_init_aliasing_ppgtt(dev);
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if (ret)
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if (ret) {
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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} else {
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/* Let GEM Manage all of the aperture.
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*
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|
|
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|
|
@ -66,7 +66,11 @@ MODULE_PARM_DESC(semaphores,
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int i915_enable_rc6 __read_mostly = -1;
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module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
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MODULE_PARM_DESC(i915_enable_rc6,
|
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"Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
|
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"Enable power-saving render C-state 6. "
|
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"Different stages can be selected via bitmask values "
|
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"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
|
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"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
|
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"default: -1 (use per-chip default)");
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int i915_enable_fbc __read_mostly = -1;
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module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
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|
|
@ -103,8 +107,8 @@ MODULE_PARM_DESC(enable_hangcheck,
|
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"WARNING: Disabling this can cause system wide hangs. "
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"(default: true)");
|
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|
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bool i915_enable_ppgtt __read_mostly = 1;
|
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module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
|
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int i915_enable_ppgtt __read_mostly = -1;
|
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module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
|
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MODULE_PARM_DESC(i915_enable_ppgtt,
|
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"Enable PPGTT (default: true)");
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|
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|
|
@ -292,6 +296,7 @@ static const struct pci_device_id pciidlist[] = { /* aka */
|
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INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
|
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INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
|
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INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
|
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INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
|
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{0, 0, 0}
|
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};
|
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|
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|
|
@ -533,7 +538,9 @@ static int i915_drm_thaw(struct drm_device *dev)
|
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drm_irq_install(dev);
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|
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/* Resume the modeset for every activated CRTC */
|
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mutex_lock(&dev->mode_config.mutex);
|
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drm_helper_resume_force_mode(dev);
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
if (IS_IRONLAKE_M(dev))
|
||||
ironlake_enable_rc6(dev);
|
||||
|
|
|
|||
|
|
@ -1053,6 +1053,27 @@ struct drm_i915_file_private {
|
|||
|
||||
#include "i915_trace.h"
|
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|
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/**
|
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* RC6 is a special power stage which allows the GPU to enter an very
|
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* low-voltage mode when idle, using down to 0V while at this stage. This
|
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* stage is entered automatically when the GPU is idle when RC6 support is
|
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* enabled, and as soon as new workload arises GPU wakes up automatically as well.
|
||||
*
|
||||
* There are different RC6 modes available in Intel GPU, which differentiate
|
||||
* among each other with the latency required to enter and leave RC6 and
|
||||
* voltage consumed by the GPU in different states.
|
||||
*
|
||||
* The combination of the following flags define which states GPU is allowed
|
||||
* to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
|
||||
* RC6pp is deepest RC6. Their support by hardware varies according to the
|
||||
* GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
|
||||
* which brings the most power savings; deeper states save more power, but
|
||||
* require higher latency to switch to and wake up.
|
||||
*/
|
||||
#define INTEL_RC6_ENABLE (1<<0)
|
||||
#define INTEL_RC6p_ENABLE (1<<1)
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||||
#define INTEL_RC6pp_ENABLE (1<<2)
|
||||
|
||||
extern struct drm_ioctl_desc i915_ioctls[];
|
||||
extern int i915_max_ioctl;
|
||||
extern unsigned int i915_fbpercrtc __always_unused;
|
||||
|
|
@ -1065,7 +1086,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly;
|
|||
extern int i915_enable_rc6 __read_mostly;
|
||||
extern int i915_enable_fbc __read_mostly;
|
||||
extern bool i915_enable_hangcheck __read_mostly;
|
||||
extern bool i915_enable_ppgtt __read_mostly;
|
||||
extern int i915_enable_ppgtt __read_mostly;
|
||||
|
||||
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
|
||||
extern int i915_resume(struct drm_device *dev);
|
||||
|
|
|
|||
|
|
@ -1472,16 +1472,19 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
|
|||
list_move_tail(&obj->ring_list, &ring->active_list);
|
||||
|
||||
obj->last_rendering_seqno = seqno;
|
||||
|
||||
if (obj->fenced_gpu_access) {
|
||||
struct drm_i915_fence_reg *reg;
|
||||
|
||||
BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
|
||||
|
||||
obj->last_fenced_seqno = seqno;
|
||||
obj->last_fenced_ring = ring;
|
||||
|
||||
reg = &dev_priv->fence_regs[obj->fence_reg];
|
||||
list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
|
||||
/* Bump MRU to take account of the delayed flush */
|
||||
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
||||
struct drm_i915_fence_reg *reg;
|
||||
|
||||
reg = &dev_priv->fence_regs[obj->fence_reg];
|
||||
list_move_tail(®->lru_list,
|
||||
&dev_priv->mm.fence_list);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3754,12 +3757,32 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
|
|||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
uint32_t pd_offset;
|
||||
struct intel_ring_buffer *ring;
|
||||
struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
|
||||
uint32_t __iomem *pd_addr;
|
||||
uint32_t pd_entry;
|
||||
int i;
|
||||
|
||||
if (!dev_priv->mm.aliasing_ppgtt)
|
||||
return;
|
||||
|
||||
pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset;
|
||||
|
||||
pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
|
||||
for (i = 0; i < ppgtt->num_pd_entries; i++) {
|
||||
dma_addr_t pt_addr;
|
||||
|
||||
if (dev_priv->mm.gtt->needs_dmar)
|
||||
pt_addr = ppgtt->pt_dma_addr[i];
|
||||
else
|
||||
pt_addr = page_to_phys(ppgtt->pt_pages[i]);
|
||||
|
||||
pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
|
||||
pd_entry |= GEN6_PDE_VALID;
|
||||
|
||||
writel(pd_entry, pd_addr + i);
|
||||
}
|
||||
readl(pd_addr);
|
||||
|
||||
pd_offset = ppgtt->pd_offset;
|
||||
pd_offset /= 64; /* in cachelines, */
|
||||
pd_offset <<= 16;
|
||||
|
||||
|
|
|
|||
|
|
@ -498,8 +498,8 @@ pin_and_fence_object(struct drm_i915_gem_object *obj,
|
|||
if (ret)
|
||||
goto err_unpin;
|
||||
}
|
||||
obj->pending_fenced_gpu_access = true;
|
||||
}
|
||||
obj->pending_fenced_gpu_access = need_fence;
|
||||
}
|
||||
|
||||
entry->offset = obj->gtt_offset;
|
||||
|
|
|
|||
|
|
@ -65,9 +65,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
|
|||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct i915_hw_ppgtt *ppgtt;
|
||||
uint32_t pd_entry;
|
||||
unsigned first_pd_entry_in_global_pt;
|
||||
uint32_t __iomem *pd_addr;
|
||||
int i;
|
||||
int ret = -ENOMEM;
|
||||
|
||||
|
|
@ -100,7 +98,6 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
|
|||
goto err_pt_alloc;
|
||||
}
|
||||
|
||||
pd_addr = dev_priv->mm.gtt->gtt + first_pd_entry_in_global_pt;
|
||||
for (i = 0; i < ppgtt->num_pd_entries; i++) {
|
||||
dma_addr_t pt_addr;
|
||||
if (dev_priv->mm.gtt->needs_dmar) {
|
||||
|
|
@ -117,13 +114,7 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
|
|||
ppgtt->pt_dma_addr[i] = pt_addr;
|
||||
} else
|
||||
pt_addr = page_to_phys(ppgtt->pt_pages[i]);
|
||||
|
||||
pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
|
||||
pd_entry |= GEN6_PDE_VALID;
|
||||
|
||||
writel(pd_entry, pd_addr + i);
|
||||
}
|
||||
readl(pd_addr);
|
||||
|
||||
ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
|
||||
|
||||
|
|
|
|||
|
|
@ -2385,6 +2385,7 @@
|
|||
#define PIPECONF_DISABLE 0
|
||||
#define PIPECONF_DOUBLE_WIDE (1<<30)
|
||||
#define I965_PIPECONF_ACTIVE (1<<30)
|
||||
#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
|
||||
#define PIPECONF_SINGLE_WIDE 0
|
||||
#define PIPECONF_PIPE_UNLOCKED 0
|
||||
#define PIPECONF_PIPE_LOCKED (1<<25)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
* Eric Anholt <eric@anholt.net>
|
||||
*
|
||||
*/
|
||||
#include <linux/dmi.h>
|
||||
#include <drm/drm_dp_helper.h>
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
|
|
@ -621,6 +622,26 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
|
|||
dev_priv->edp.bpp = 18;
|
||||
}
|
||||
|
||||
static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)
|
||||
{
|
||||
DRM_DEBUG_KMS("Falling back to manually reading VBT from "
|
||||
"VBIOS ROM for %s\n",
|
||||
id->ident);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct dmi_system_id intel_no_opregion_vbt[] = {
|
||||
{
|
||||
.callback = intel_no_opregion_vbt_callback,
|
||||
.ident = "ThinkCentre A57",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"),
|
||||
},
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
/**
|
||||
* intel_parse_bios - find VBT and initialize settings from the BIOS
|
||||
* @dev: DRM device
|
||||
|
|
@ -641,7 +662,7 @@ intel_parse_bios(struct drm_device *dev)
|
|||
init_vbt_defaults(dev_priv);
|
||||
|
||||
/* XXX Should this validation be moved to intel_opregion.c? */
|
||||
if (dev_priv->opregion.vbt) {
|
||||
if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt) {
|
||||
struct vbt_header *vbt = dev_priv->opregion.vbt;
|
||||
if (memcmp(vbt->signature, "$VBT", 4) == 0) {
|
||||
DRM_DEBUG_KMS("Using VBT from OpRegion: %20s\n",
|
||||
|
|
|
|||
|
|
@ -5539,7 +5539,8 @@ void ironlake_init_pch_refclk(struct drm_device *dev)
|
|||
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
|
||||
DRM_DEBUG_KMS("Using SSC on panel\n");
|
||||
temp |= DREF_SSC1_ENABLE;
|
||||
}
|
||||
} else
|
||||
temp &= ~DREF_SSC1_ENABLE;
|
||||
|
||||
/* Get SSC going before enabling the outputs */
|
||||
I915_WRITE(PCH_DREF_CONTROL, temp);
|
||||
|
|
@ -7580,6 +7581,12 @@ static void intel_sanitize_modesetting(struct drm_device *dev,
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
u32 reg, val;
|
||||
|
||||
/* Clear any frame start delays used for debugging left by the BIOS */
|
||||
for_each_pipe(pipe) {
|
||||
reg = PIPECONF(pipe);
|
||||
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
|
||||
}
|
||||
|
||||
if (HAS_PCH_SPLIT(dev))
|
||||
return;
|
||||
|
||||
|
|
@ -8215,7 +8222,7 @@ void intel_init_emon(struct drm_device *dev)
|
|||
dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
|
||||
}
|
||||
|
||||
static bool intel_enable_rc6(struct drm_device *dev)
|
||||
static int intel_enable_rc6(struct drm_device *dev)
|
||||
{
|
||||
/*
|
||||
* Respect the kernel parameter if it is set
|
||||
|
|
@ -8233,11 +8240,11 @@ static bool intel_enable_rc6(struct drm_device *dev)
|
|||
* Disable rc6 on Sandybridge
|
||||
*/
|
||||
if (INTEL_INFO(dev)->gen == 6) {
|
||||
DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
|
||||
return 0;
|
||||
DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
|
||||
return INTEL_RC6_ENABLE;
|
||||
}
|
||||
DRM_DEBUG_DRIVER("RC6 enabled\n");
|
||||
return 1;
|
||||
DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
|
||||
return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
|
||||
}
|
||||
|
||||
void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
||||
|
|
@ -8247,6 +8254,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
|||
u32 pcu_mbox, rc6_mask = 0;
|
||||
u32 gtfifodbg;
|
||||
int cur_freq, min_freq, max_freq;
|
||||
int rc6_mode;
|
||||
int i;
|
||||
|
||||
/* Here begins a magic sequence of register writes to enable
|
||||
|
|
@ -8284,9 +8292,20 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
|||
I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
|
||||
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
|
||||
|
||||
if (intel_enable_rc6(dev_priv->dev))
|
||||
rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
|
||||
((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
|
||||
rc6_mode = intel_enable_rc6(dev_priv->dev);
|
||||
if (rc6_mode & INTEL_RC6_ENABLE)
|
||||
rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
|
||||
|
||||
if (rc6_mode & INTEL_RC6p_ENABLE)
|
||||
rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
|
||||
|
||||
if (rc6_mode & INTEL_RC6pp_ENABLE)
|
||||
rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
|
||||
|
||||
DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
|
||||
(rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off",
|
||||
(rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off",
|
||||
(rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off");
|
||||
|
||||
I915_WRITE(GEN6_RC_CONTROL,
|
||||
rc6_mask |
|
||||
|
|
|
|||
|
|
@ -755,6 +755,14 @@ static const struct dmi_system_id intel_no_lvds[] = {
|
|||
DMI_MATCH(DMI_BOARD_NAME, "hp st5747"),
|
||||
},
|
||||
},
|
||||
{
|
||||
.callback = intel_no_lvds_dmi_callback,
|
||||
.ident = "MSI Wind Box DC500",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
|
||||
},
|
||||
},
|
||||
|
||||
{ } /* terminating entry */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -626,7 +626,7 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring)
|
|||
/* Workaround to force correct ordering between irq and seqno writes on
|
||||
* ivb (and maybe also on snb) by reading from a CS register (like
|
||||
* ACTHD) before reading the status page. */
|
||||
if (IS_GEN7(dev))
|
||||
if (IS_GEN6(dev) || IS_GEN7(dev))
|
||||
intel_ring_get_active_head(ring);
|
||||
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -411,6 +411,9 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
|
|||
|
||||
old_obj = intel_plane->obj;
|
||||
|
||||
src_w = src_w >> 16;
|
||||
src_h = src_h >> 16;
|
||||
|
||||
/* Pipe must be running... */
|
||||
if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -44,4 +44,8 @@ void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
|
|||
/* flag for GFDT type */
|
||||
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
|
||||
|
||||
#ifdef CONFIG_INTEL_IOMMU
|
||||
extern int intel_iommu_gfx_mapped;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue