powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts. Currently supported flags values and their details: soft_enabled MSR[EE] 0 0 Disabled (PMI and HMI not masked) 1 1 Enabled "paca->soft_enabled" is initialized to 1 to make the interripts as enabled. arch_local_irq_disable() will toggle the value when interrupts needs to disbled. At this point, the interrupts are not actually disabled, instead, interrupt vector has code to check for the flag and mask it when it occurs. By "mask it", it update interrupt paca->irq_happened and return. arch_local_irq_restore() is called to re-enable interrupts, which checks and replays interrupts if any occured. Now, as mentioned, current logic doesnot mask "performance monitoring interrupts" and PMIs are implemented as NMI. But this patchset depends on local_irq_* for a successful local_* update. Meaning, mask all possible interrupts during local_* update and replay them after the update. So the idea here is to reserve the "paca->soft_enabled" logic. New values and details: soft_enabled MSR[EE] 1 0 Disabled (PMI and HMI not masked) 0 1 Enabled Reason for the this change is to create foundation for a third mask value "0x2" for "soft_enabled" to add support to mask PMIs. When ->soft_enabled is set to a value "3", PMI interrupts are mask and when set to a value of "1", PMI are not mask. With this patch also extends soft_enabled as interrupt disable mask. Current flags are renamed from IRQ_[EN?DIS}ABLED to IRQS_ENABLED and IRQS_DISABLED. Patch also fixes the ptrace call to force the user to see the softe value to be alway 1. Reason being, even though userspace has no business knowing about softe, it is part of pt_regs. Like-wise in signal context. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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acb396d7c2
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01417c6cc7
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@ -499,9 +499,9 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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#define __SOFTEN_TEST(h, vec) \
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lbz r10,PACASOFTIRQEN(r13); \
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cmpwi r10,IRQS_DISABLED; \
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andi. r10,r10,IRQS_DISABLED; \
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li r10,SOFTEN_VALUE_##vec; \
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beq masked_##h##interrupt
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bne masked_##h##interrupt
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#define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec)
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@ -31,8 +31,8 @@
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/*
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* flags for paca->soft_enabled
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*/
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#define IRQS_ENABLED 1
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#define IRQS_DISABLED 0
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#define IRQS_ENABLED 0
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#define IRQS_DISABLED 1
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#endif /* CONFIG_PPC64 */
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@ -68,6 +68,18 @@ static inline notrace unsigned long soft_enabled_return(void)
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*/
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static inline notrace void soft_enabled_set(unsigned long enable)
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{
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#ifdef CONFIG_TRACE_IRQFLAGS
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/*
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* mask must always include LINUX bit if any are set, and
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* interrupts don't get replayed until the Linux interrupt is
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* unmasked. This could be changed to replay partial unmasks
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* in future, which would allow Linux masks to nest inside
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* other masks, among other things. For now, be very dumb and
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* simple.
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*/
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WARN_ON(mask && !(mask & IRQS_DISABLED));
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#endif
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asm volatile(
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"stb %0,%1(13)"
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:
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@ -76,15 +88,19 @@ static inline notrace void soft_enabled_set(unsigned long enable)
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: "memory");
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}
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static inline notrace unsigned long soft_enabled_set_return(unsigned long enable)
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static inline notrace unsigned long soft_enabled_set_return(unsigned long mask)
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{
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unsigned long flags;
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#ifdef CONFIG_TRACE_IRQFLAGS
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WARN_ON(mask && !(mask & IRQS_DISABLED));
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#endif
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asm volatile(
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"lbz %0,%1(13); stb %2,%1(13)"
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: "=&r" (flags)
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: "i" (offsetof(struct paca_struct, soft_enabled)),
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"r" (enable)
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"r" (mask)
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: "memory");
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return flags;
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@ -114,7 +130,7 @@ static inline unsigned long arch_local_irq_save(void)
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static inline bool arch_irqs_disabled_flags(unsigned long flags)
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{
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return flags == IRQS_DISABLED;
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return flags & IRQS_DISABLED;
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}
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static inline bool arch_irqs_disabled(void)
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@ -133,7 +149,7 @@ static inline bool arch_irqs_disabled(void)
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#define hard_irq_disable() do { \
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unsigned long flags; \
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__hard_irq_disable(); \
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flags = soft_enabled_set_return(IRQS_DISABLED); \
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flags = soft_enabled_set_return(IRQS_DISABLED);\
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS; \
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if (!arch_irqs_disabled_flags(flags)) \
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trace_hardirqs_off(); \
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@ -158,7 +174,7 @@ static inline void may_hard_irq_enable(void)
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static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
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{
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return (regs->softe == IRQS_DISABLED);
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return (regs->softe & IRQS_DISABLED);
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}
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extern bool prep_irq_for_idle(void);
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@ -49,11 +49,11 @@
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#define RECONCILE_IRQ_STATE(__rA, __rB) \
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lbz __rA,PACASOFTIRQEN(r13); \
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lbz __rB,PACAIRQHAPPENED(r13); \
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cmpwi cr0,__rA,IRQS_DISABLED;\
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andi. __rA,__rA,IRQS_DISABLED;\
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li __rA,IRQS_DISABLED; \
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ori __rB,__rB,PACA_IRQ_HARD_DIS; \
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stb __rB,PACAIRQHAPPENED(r13); \
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beq 44f; \
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bne 44f; \
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stb __rA,PACASOFTIRQEN(r13); \
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TRACE_DISABLE_INTS; \
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44:
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@ -130,8 +130,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
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*/
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#if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
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lbz r10,PACASOFTIRQEN(r13)
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xori r10,r10,IRQS_ENABLED
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1: tdnei r10,0
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1: tdnei r10,IRQS_ENABLED
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
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#endif
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@ -741,10 +740,10 @@ resume_kernel:
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beq+ restore
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/* Check that preempt_count() == 0 and interrupts are enabled */
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lwz r8,TI_PREEMPT(r9)
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cmpwi cr1,r8,0
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cmpwi cr0,r8,0
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bne restore
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ld r0,SOFTE(r1)
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cmpdi r0,IRQS_DISABLED
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crandc eq,cr1*4+eq,eq
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andi. r0,r0,IRQS_DISABLED
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bne restore
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/*
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@ -783,11 +782,11 @@ restore:
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*/
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ld r5,SOFTE(r1)
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lbz r6,PACASOFTIRQEN(r13)
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cmpwi cr0,r5,IRQS_DISABLED
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beq .Lrestore_irq_off
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andi. r5,r5,IRQS_DISABLED
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bne .Lrestore_irq_off
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/* We are enabling, were we already enabled ? Yes, just return */
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cmpwi cr0,r6,IRQS_ENABLED
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andi. r6,r6,IRQS_DISABLED
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beq cr0,.Ldo_restore
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/*
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@ -1031,15 +1030,15 @@ _GLOBAL(enter_rtas)
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li r0,0
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mtcr r0
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#ifdef CONFIG_BUG
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#ifdef CONFIG_BUG
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/* There is no way it is acceptable to get here with interrupts enabled,
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* check it with the asm equivalent of WARN_ON
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*/
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lbz r0,PACASOFTIRQEN(r13)
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1: tdnei r0,IRQS_DISABLED
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1: tdeqi r0,IRQS_ENABLED
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
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#endif
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/* Hard-disable interrupts */
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mfmsr r6
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rldicl r7,r6,48,1
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@ -210,10 +210,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
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ld r5,SOFTE(r1)
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/* Interrupts had better not already be enabled... */
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twnei r6,IRQS_DISABLED
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tweqi r6,IRQS_ENABLED
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cmpwi cr0,r5,IRQS_DISABLED
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beq 1f
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andi. r6,r5,IRQS_DISABLED
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bne 1f
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TRACE_ENABLE_INTS
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stb r5,PACASOFTIRQEN(r13)
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@ -352,8 +352,8 @@ ret_from_mc_except:
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#define PROLOG_ADDITION_MASKABLE_GEN(n) \
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lbz r10,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
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cmpwi cr0,r10,IRQS_DISABLED; /* yes -> go out of line */ \
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beq masked_interrupt_book3e_##n
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andi. r10,r10,IRQS_DISABLED; /* yes -> go out of line */ \
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bne masked_interrupt_book3e_##n
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#define PROLOG_ADDITION_2REGS_GEN(n) \
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std r14,PACA_EXGEN+EX_R14(r13); \
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@ -219,15 +219,29 @@ notrace unsigned int __check_irq_replay(void)
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return 0;
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}
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notrace void arch_local_irq_restore(unsigned long en)
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notrace void arch_local_irq_restore(unsigned long mask)
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{
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unsigned char irq_happened;
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unsigned int replay;
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/* Write the new soft-enabled value */
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soft_enabled_set(en);
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if (en == IRQS_DISABLED)
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soft_enabled_set(mask);
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if (mask) {
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#ifdef CONFIG_TRACE_IRQFLAGS
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/*
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* mask must always include LINUX bit if any
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* are set, and interrupts don't get replayed until
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* the Linux interrupt is unmasked. This could be
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* changed to replay partial unmasks in future,
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* which would allow Linux masks to nest inside
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* other masks, among other things. For now, be very
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* dumb and simple.
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*/
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WARN_ON(!(mask & IRQS_DISABLED));
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#endif
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return;
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}
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/*
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* From this point onward, we can take interrupts, preempt,
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* etc... unless we got hard-disabled. We check if an event
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@ -322,7 +322,7 @@ static inline void perf_read_regs(struct pt_regs *regs)
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*/
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static inline int perf_intr_is_nmi(struct pt_regs *regs)
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{
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return (regs->softe == IRQS_DISABLED);
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return (regs->softe & IRQS_DISABLED);
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}
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/*
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