net: phy: meson-gxl: define control registers
Define registers and bits in meson-gxl PHY driver to make a bit more human friendly. No functional change. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jerome Brunet
David S. Miller
parent
9042b46eda
commit
00fd73eb29
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@ -24,53 +24,95 @@
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#define TSTCNTL 20
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#define TSTCNTL_READ BIT(15)
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#define TSTCNTL_WRITE BIT(14)
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#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
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#define TSTCNTL_TEST_MODE BIT(10)
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#define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
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#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
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#define TSTREAD1 21
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#define TSTWRITE 23
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#define BANK_ANALOG_DSP 0
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#define BANK_WOL 1
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#define BANK_BIST 3
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/* Analog/DSP Registers */
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#define A6_CONFIG_REG 0x17
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/* WOL Registers */
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#define LPI_STATUS 0xc
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#define LPI_STATUS_RSV12 BIT(12)
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/* BIST Registers */
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#define FR_PLL_CONTROL 0x1b
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#define FR_PLL_DIV0 0x1c
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#define FR_PLL_DIV1 0x1d
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by */
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ret = phy_write(phydev, 0x14, 0x0000);
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0000);
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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/* Write Analog register 23 */
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ret = phy_write(phydev, 0x17, 0x8E0D);
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/* Write CONFIG_A6*/
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ret = phy_write(phydev, TSTWRITE, 0x8e0d);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x4417);
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG));
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if (ret)
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return ret;
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/* Enable fractional PLL */
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ret = phy_write(phydev, 0x17, 0x0005);
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ret = phy_write(phydev, TSTWRITE, 0x0005);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1B);
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL));
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = phy_write(phydev, 0x17, 0x029A);
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ret = phy_write(phydev, TSTWRITE, 0x029a);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1D);
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1));
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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ret = phy_write(phydev, 0x17, 0xAAAA);
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ret = phy_write(phydev, TSTWRITE, 0xaaaa);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x5C1C);
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_WRITE
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0));
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if (ret)
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return ret;
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@ -105,26 +147,30 @@ static int meson_gxl_read_status(struct phy_device *phydev)
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goto read_status_continue;
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/* Need to access WOL bank, make sure the access is open */
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ret = phy_write(phydev, 0x14, 0x0000);
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0000);
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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/* Request LPI_STATUS WOL register */
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ret = phy_write(phydev, 0x14, 0x8D80);
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ret = phy_write(phydev, TSTCNTL,
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TSTCNTL_READ
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| FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_WOL)
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| TSTCNTL_TEST_MODE
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| FIELD_PREP(TSTCNTL_READ_ADDRESS, LPI_STATUS));
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if (ret)
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return ret;
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/* Read LPI_STATUS value */
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wol = phy_read(phydev, 0x15);
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wol = phy_read(phydev, TSTREAD1);
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if (wol < 0)
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return wol;
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@ -136,7 +182,7 @@ static int meson_gxl_read_status(struct phy_device *phydev)
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if (exp < 0)
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return exp;
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if (!(wol & BIT(12)) ||
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if (!(wol & LPI_STATUS_RSV12) ||
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((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
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/* Looks like aneg failed after all */
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phydev_dbg(phydev, "LPA corruption - aneg restart\n");
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