csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Guo Ren
parent
4859bfca11
commit
00a9730e10
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include <linux/syscalls.h>
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#include <linux/spinlock.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/cachectl.h>
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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unsigned long addr;
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_arch_1, &(page)->flags);
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return;
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}
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/*
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* We could delay the flush for the !page_mapping case too. But that
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* case is for exec env/arg pages and those are %99 certainly going to
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* get faulted into the tlb (and thus flushed) anyways.
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*/
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addr = (unsigned long) page_address(page);
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dcache_wb_range(addr, addr + PAGE_SIZE);
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}
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long addr;
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struct page *page;
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unsigned long pfn;
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pfn = pte_pfn(*pte);
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if (unlikely(!pfn_valid(pfn)))
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return;
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page = pfn_to_page(pfn);
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addr = (unsigned long) page_address(page);
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if (vma->vm_flags & VM_EXEC ||
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pages_do_alias(addr, address & PAGE_MASK))
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cache_wbinv_all();
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clear_bit(PG_arch_1, &(page)->flags);
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}
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ABI_CSKY_CACHEFLUSH_H
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#define __ABI_CSKY_CACHEFLUSH_H
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#include <linux/compiler.h>
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#include <asm/string.h>
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#include <asm/cache.h>
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page *);
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#define flush_cache_mm(mm) cache_wbinv_all()
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#define flush_cache_page(vma, page, pfn) cache_wbinv_all()
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#define flush_cache_dup_mm(mm) cache_wbinv_all()
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/*
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* if (current_mm != vma->mm) cache_wbinv_range(start, end) will be broken.
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* Use cache_wbinv_all() here and need to be improved in future.
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*/
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#define flush_cache_range(vma, start, end) cache_wbinv_all()
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#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
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#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
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#define flush_icache_page(vma, page) cache_wbinv_all()
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#define flush_icache_range(start, end) cache_wbinv_range(start, end)
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#define flush_icache_user_range(vma, pg, adr, len) \
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cache_wbinv_range(adr, adr + len)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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cache_wbinv_all(); \
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memcpy(dst, src, len); \
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cache_wbinv_all(); \
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} while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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cache_wbinv_all(); \
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memcpy(dst, src, len); \
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cache_wbinv_all(); \
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} while (0)
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#define flush_dcache_mmap_lock(mapping) do {} while (0)
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#define flush_dcache_mmap_unlock(mapping) do {} while (0)
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#endif /* __ABI_CSKY_CACHEFLUSH_H */
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/highmem.h>
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#include <linux/mm.h>
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#include <asm/cache.h>
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void flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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unsigned long start;
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start = (unsigned long) kmap_atomic(page);
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cache_wbinv_range(start, start + PAGE_SIZE);
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kunmap_atomic((void *)start);
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}
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, int len)
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{
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unsigned long kaddr;
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kaddr = (unsigned long) kmap_atomic(page) + (vaddr & ~PAGE_MASK);
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cache_wbinv_range(kaddr, kaddr + len);
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kunmap_atomic((void *)kaddr);
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}
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void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t *pte)
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{
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unsigned long addr, pfn;
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struct page *page;
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void *va;
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if (!(vma->vm_flags & VM_EXEC))
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return;
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pfn = pte_pfn(*pte);
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if (unlikely(!pfn_valid(pfn)))
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return;
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page = pfn_to_page(pfn);
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if (page == ZERO_PAGE(0))
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return;
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va = page_address(page);
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addr = (unsigned long) va;
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if (va == NULL && PageHighMem(page))
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addr = (unsigned long) kmap_atomic(page);
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cache_wbinv_range(addr, addr + PAGE_SIZE);
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if (va == NULL && PageHighMem(page))
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kunmap_atomic((void *) addr);
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}
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ABI_CSKY_CACHEFLUSH_H
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#define __ABI_CSKY_CACHEFLUSH_H
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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/*
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* The cache doesn't need to be flushed when TLB entries change when
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* the cache is mapped to physical memory, not virtual memory
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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icache_inv_all(); \
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} while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_range(start, end) cache_wbinv_range(start, end)
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void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, int len);
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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cache_wbinv_range((unsigned long)dst, (unsigned long)dst + len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __ABI_CSKY_CACHEFLUSH_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_BARRIER_H
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#define __ASM_CSKY_BARRIER_H
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#ifndef __ASSEMBLY__
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#define nop() asm volatile ("nop\n":::"memory")
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/*
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* sync: completion barrier
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* sync.s: completion barrier and shareable to other cores
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* sync.i: completion barrier with flush cpu pipeline
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* sync.is: completion barrier with flush cpu pipeline and shareable to
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* other cores
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*
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* bar.brwarw: ordering barrier for all load/store instructions before it
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* bar.brwarws: ordering barrier for all load/store instructions before it
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* and shareable to other cores
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* bar.brar: ordering barrier for all load instructions before it
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* bar.brars: ordering barrier for all load instructions before it
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* and shareable to other cores
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* bar.bwaw: ordering barrier for all store instructions before it
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* bar.bwaws: ordering barrier for all store instructions before it
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* and shareable to other cores
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*/
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#ifdef CONFIG_CPU_HAS_CACHEV2
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#define mb() asm volatile ("bar.brwarw\n":::"memory")
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#define rmb() asm volatile ("bar.brar\n":::"memory")
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#define wmb() asm volatile ("bar.bwaw\n":::"memory")
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#ifdef CONFIG_SMP
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#define __smp_mb() asm volatile ("bar.brwarws\n":::"memory")
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#define __smp_rmb() asm volatile ("bar.brars\n":::"memory")
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#define __smp_wmb() asm volatile ("bar.bwaws\n":::"memory")
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#endif /* CONFIG_SMP */
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#define sync_is() asm volatile ("sync.is\n":::"memory")
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#else /* !CONFIG_CPU_HAS_CACHEV2 */
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#define mb() asm volatile ("sync\n":::"memory")
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_CSKY_BARRIER_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_CACHE_H
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#define __ASM_CSKY_CACHE_H
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#ifndef __ASSEMBLY__
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void dcache_wb_line(unsigned long start);
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void icache_inv_range(unsigned long start, unsigned long end);
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void icache_inv_all(void);
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void dcache_wb_range(unsigned long start, unsigned long end);
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void dcache_wbinv_all(void);
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void cache_wbinv_range(unsigned long start, unsigned long end);
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void cache_wbinv_all(void);
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void dma_wbinv_range(unsigned long start, unsigned long end);
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void dma_wb_range(unsigned long start, unsigned long end);
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#endif
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#endif /* __ASM_CSKY_CACHE_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_CACHEFLUSH_H
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#define __ASM_CSKY_CACHEFLUSH_H
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#include <abi/cacheflush.h>
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#endif /* __ASM_CSKY_CACHEFLUSH_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_IO_H
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#define __ASM_CSKY_IO_H
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#include <abi/pgtable-bits.h>
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#include <linux/types.h>
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#include <linux/version.h>
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extern void __iomem *ioremap(phys_addr_t offset, size_t size);
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extern void iounmap(void *addr);
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extern int remap_area_pages(unsigned long address, phys_addr_t phys_addr,
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size_t size, unsigned long flags);
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#define ioremap_nocache(phy, sz) ioremap(phy, sz)
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#define ioremap_wc ioremap_nocache
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#define ioremap_wt ioremap_nocache
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#include <asm-generic/io.h>
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#endif /* __ASM_CSKY_IO_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_TLB_H
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#define __ASM_CSKY_TLB_H
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#include <asm/cacheflush.h>
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#define tlb_start_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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} while (0)
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#define tlb_end_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
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} while (0)
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#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
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#include <asm-generic/tlb.h>
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#endif /* __ASM_CSKY_TLB_H */
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_TLBFLUSH_H
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#define __ASM_TLBFLUSH_H
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/*
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* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLB entries
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* - flush_tlb_mm(mm) flushes the specified mm context TLB entries
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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*/
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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extern void flush_tlb_one(unsigned long vaddr);
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#endif
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_CACHECTL_H
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#define __ASM_CSKY_CACHECTL_H
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/*
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* See "man cacheflush"
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*/
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#define ICACHE (1<<0)
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#define DCACHE (1<<1)
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#define BCACHE (ICACHE|DCACHE)
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#endif /* __ASM_CSKY_CACHECTL_H */
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/spinlock.h>
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#include <asm/cache.h>
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#include <abi/reg_ops.h>
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/* for L1-cache */
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#define INS_CACHE (1 << 0)
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#define DATA_CACHE (1 << 1)
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#define CACHE_INV (1 << 4)
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#define CACHE_CLR (1 << 5)
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#define CACHE_OMS (1 << 6)
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#define CACHE_ITS (1 << 7)
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#define CACHE_LICF (1 << 31)
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/* for L2-cache */
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#define CR22_LEVEL_SHIFT (1)
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#define CR22_SET_SHIFT (7)
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#define CR22_WAY_SHIFT (30)
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#define CR22_WAY_SHIFT_L2 (29)
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static DEFINE_SPINLOCK(cache_lock);
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static inline void cache_op_line(unsigned long i, unsigned int val)
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{
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mtcr("cr22", i);
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mtcr("cr17", val);
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}
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#define CCR2_L2E (1 << 3)
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static void cache_op_all(unsigned int value, unsigned int l2)
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{
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mtcr("cr17", value | CACHE_CLR);
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mb();
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if (l2 && (mfcr_ccr2() & CCR2_L2E)) {
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mtcr("cr24", value | CACHE_CLR);
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mb();
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}
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}
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static void cache_op_range(
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unsigned int start,
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unsigned int end,
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unsigned int value,
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unsigned int l2)
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{
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unsigned long i, flags;
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unsigned int val = value | CACHE_CLR | CACHE_OMS;
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bool l2_sync;
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if (unlikely((end - start) >= PAGE_SIZE) ||
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unlikely(start < PAGE_OFFSET) ||
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unlikely(start >= PAGE_OFFSET + LOWMEM_LIMIT)) {
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cache_op_all(value, l2);
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return;
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}
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|
||||
if ((mfcr_ccr2() & CCR2_L2E) && l2)
|
||||
l2_sync = 1;
|
||||
else
|
||||
l2_sync = 0;
|
||||
|
||||
spin_lock_irqsave(&cache_lock, flags);
|
||||
|
||||
i = start & ~(L1_CACHE_BYTES - 1);
|
||||
for (; i < end; i += L1_CACHE_BYTES) {
|
||||
cache_op_line(i, val);
|
||||
if (l2_sync) {
|
||||
mb();
|
||||
mtcr("cr24", val);
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&cache_lock, flags);
|
||||
|
||||
mb();
|
||||
}
|
||||
|
||||
void dcache_wb_line(unsigned long start)
|
||||
{
|
||||
asm volatile("idly4\n":::"memory");
|
||||
cache_op_line(start, DATA_CACHE|CACHE_CLR);
|
||||
mb();
|
||||
}
|
||||
|
||||
void icache_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
cache_op_range(start, end, INS_CACHE|CACHE_INV, 0);
|
||||
}
|
||||
|
||||
void icache_inv_all(void)
|
||||
{
|
||||
cache_op_all(INS_CACHE|CACHE_INV, 0);
|
||||
}
|
||||
|
||||
void dcache_wb_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
cache_op_range(start, end, DATA_CACHE|CACHE_CLR, 0);
|
||||
}
|
||||
|
||||
void dcache_wbinv_all(void)
|
||||
{
|
||||
cache_op_all(DATA_CACHE|CACHE_CLR|CACHE_INV, 0);
|
||||
}
|
||||
|
||||
void cache_wbinv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
cache_op_range(start, end, INS_CACHE|DATA_CACHE|CACHE_CLR|CACHE_INV, 0);
|
||||
}
|
||||
EXPORT_SYMBOL(cache_wbinv_range);
|
||||
|
||||
void cache_wbinv_all(void)
|
||||
{
|
||||
cache_op_all(INS_CACHE|DATA_CACHE|CACHE_CLR|CACHE_INV, 0);
|
||||
}
|
||||
|
||||
void dma_wbinv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
|
||||
}
|
||||
|
||||
void dma_wb_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
cache_op_range(start, end, DATA_CACHE|CACHE_INV, 1);
|
||||
}
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/barrier.h>
|
||||
|
||||
inline void dcache_wb_line(unsigned long start)
|
||||
{
|
||||
asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void icache_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("icache.iva %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void icache_inv_all(void)
|
||||
{
|
||||
asm volatile("icache.ialls\n":::"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void dcache_wb_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void dcache_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("dcache.civa %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void cache_wbinv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
|
||||
i = start & ~(L1_CACHE_BYTES - 1);
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("icache.iva %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
EXPORT_SYMBOL(cache_wbinv_range);
|
||||
|
||||
void dma_wbinv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("dcache.civa %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
||||
void dma_wb_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long i = start & ~(L1_CACHE_BYTES - 1);
|
||||
|
||||
for (; i < end; i += L1_CACHE_BYTES)
|
||||
asm volatile("dcache.civa %0\n"::"r"(i):"memory");
|
||||
sync_is();
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
||||
|
||||
#include <linux/syscalls.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/cachectl.h>
|
||||
|
||||
SYSCALL_DEFINE3(cacheflush,
|
||||
void __user *, addr,
|
||||
unsigned long, bytes,
|
||||
int, cache)
|
||||
{
|
||||
switch (cache) {
|
||||
case ICACHE:
|
||||
icache_inv_range((unsigned long)addr,
|
||||
(unsigned long)addr + bytes);
|
||||
break;
|
||||
case DCACHE:
|
||||
dcache_wb_range((unsigned long)addr,
|
||||
(unsigned long)addr + bytes);
|
||||
break;
|
||||
case BCACHE:
|
||||
cache_wbinv_range((unsigned long)addr,
|
||||
(unsigned long)addr + bytes);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/setup.h>
|
||||
|
||||
#define CSKY_TLB_SIZE CONFIG_CPU_TLB_SIZE
|
||||
|
||||
void flush_tlb_all(void)
|
||||
{
|
||||
tlb_invalid_all();
|
||||
}
|
||||
|
||||
void flush_tlb_mm(struct mm_struct *mm)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
if (cpu_context(cpu, mm) != 0)
|
||||
drop_mmu_context(mm, cpu);
|
||||
|
||||
tlb_invalid_all();
|
||||
}
|
||||
|
||||
#define restore_asid_inv_utlb(oldpid, newpid) \
|
||||
do { \
|
||||
if ((oldpid & ASID_MASK) == newpid) \
|
||||
write_mmu_entryhi(oldpid + 1); \
|
||||
write_mmu_entryhi(oldpid); \
|
||||
} while (0)
|
||||
|
||||
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
struct mm_struct *mm = vma->vm_mm;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
if (cpu_context(cpu, mm) != 0) {
|
||||
unsigned long size, flags;
|
||||
int newpid = cpu_asid(cpu, mm);
|
||||
|
||||
local_irq_save(flags);
|
||||
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
size = (size + 1) >> 1;
|
||||
if (size <= CSKY_TLB_SIZE/2) {
|
||||
start &= (PAGE_MASK << 1);
|
||||
end += ((PAGE_SIZE << 1) - 1);
|
||||
end &= (PAGE_MASK << 1);
|
||||
#ifdef CONFIG_CPU_HAS_TLBI
|
||||
while (start < end) {
|
||||
asm volatile("tlbi.vaas %0"
|
||||
::"r"(start | newpid));
|
||||
start += (PAGE_SIZE << 1);
|
||||
}
|
||||
sync_is();
|
||||
#else
|
||||
{
|
||||
int oldpid = read_mmu_entryhi();
|
||||
|
||||
while (start < end) {
|
||||
int idx;
|
||||
|
||||
write_mmu_entryhi(start | newpid);
|
||||
start += (PAGE_SIZE << 1);
|
||||
tlb_probe();
|
||||
idx = read_mmu_index();
|
||||
if (idx >= 0)
|
||||
tlb_invalid_indexed();
|
||||
}
|
||||
restore_asid_inv_utlb(oldpid, newpid);
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
drop_mmu_context(mm, cpu);
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
}
|
||||
|
||||
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long size, flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
|
||||
if (size <= CSKY_TLB_SIZE) {
|
||||
start &= (PAGE_MASK << 1);
|
||||
end += ((PAGE_SIZE << 1) - 1);
|
||||
end &= (PAGE_MASK << 1);
|
||||
#ifdef CONFIG_CPU_HAS_TLBI
|
||||
while (start < end) {
|
||||
asm volatile("tlbi.vaas %0"::"r"(start));
|
||||
start += (PAGE_SIZE << 1);
|
||||
}
|
||||
sync_is();
|
||||
#else
|
||||
{
|
||||
int oldpid = read_mmu_entryhi();
|
||||
|
||||
while (start < end) {
|
||||
int idx;
|
||||
|
||||
write_mmu_entryhi(start);
|
||||
start += (PAGE_SIZE << 1);
|
||||
tlb_probe();
|
||||
idx = read_mmu_index();
|
||||
if (idx >= 0)
|
||||
tlb_invalid_indexed();
|
||||
}
|
||||
restore_asid_inv_utlb(oldpid, 0);
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
flush_tlb_all();
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
|
||||
{
|
||||
int cpu = smp_processor_id();
|
||||
int newpid = cpu_asid(cpu, vma->vm_mm);
|
||||
|
||||
if (!vma || cpu_context(cpu, vma->vm_mm) != 0) {
|
||||
page &= (PAGE_MASK << 1);
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_TLBI
|
||||
asm volatile("tlbi.vaas %0"::"r"(page | newpid));
|
||||
sync_is();
|
||||
#else
|
||||
{
|
||||
int oldpid, idx;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
oldpid = read_mmu_entryhi();
|
||||
write_mmu_entryhi(page | newpid);
|
||||
tlb_probe();
|
||||
idx = read_mmu_index();
|
||||
if (idx >= 0)
|
||||
tlb_invalid_indexed();
|
||||
|
||||
restore_asid_inv_utlb(oldpid, newpid);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove one kernel space TLB entry. This entry is assumed to be marked
|
||||
* global so we don't do the ASID thing.
|
||||
*/
|
||||
void flush_tlb_one(unsigned long page)
|
||||
{
|
||||
int oldpid;
|
||||
|
||||
oldpid = read_mmu_entryhi();
|
||||
page &= (PAGE_MASK << 1);
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_TLBI
|
||||
page = page | (oldpid & 0xfff);
|
||||
asm volatile("tlbi.vaas %0"::"r"(page));
|
||||
sync_is();
|
||||
#else
|
||||
{
|
||||
int idx;
|
||||
unsigned long flags;
|
||||
|
||||
page = page | (oldpid & 0xff);
|
||||
|
||||
local_irq_save(flags);
|
||||
write_mmu_entryhi(page);
|
||||
tlb_probe();
|
||||
idx = read_mmu_index();
|
||||
if (idx >= 0)
|
||||
tlb_invalid_indexed();
|
||||
restore_asid_inv_utlb(oldpid, oldpid);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
EXPORT_SYMBOL(flush_tlb_one);
|
||||
|
||||
/* show current 32 jtlbs */
|
||||
void show_jtlb_table(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
int entryhi, entrylo0, entrylo1;
|
||||
int entry;
|
||||
int oldpid;
|
||||
|
||||
local_irq_save(flags);
|
||||
entry = 0;
|
||||
pr_info("\n\n\n");
|
||||
|
||||
oldpid = read_mmu_entryhi();
|
||||
while (entry < CSKY_TLB_SIZE) {
|
||||
write_mmu_index(entry);
|
||||
tlb_read();
|
||||
entryhi = read_mmu_entryhi();
|
||||
entrylo0 = read_mmu_entrylo0();
|
||||
entrylo0 = entrylo0;
|
||||
entrylo1 = read_mmu_entrylo1();
|
||||
entrylo1 = entrylo1;
|
||||
pr_info("jtlb[%d]: entryhi - 0x%x; entrylo0 - 0x%x;"
|
||||
" entrylo1 - 0x%x\n",
|
||||
entry, entryhi, entrylo0, entrylo1);
|
||||
entry++;
|
||||
}
|
||||
write_mmu_entryhi(oldpid);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
Loading…
Reference in New Issue