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linux-sg2042/drivers/clk/qcom/common.h

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clk: qcom: Consolidate common probe code Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-22 08:59:37 +08:00
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __QCOM_CLK_COMMON_H__
#define __QCOM_CLK_COMMON_H__
struct platform_device;
struct regmap_config;
struct clk_regmap;
struct qcom_reset_map;
clk: qcom: Fix PLL rate configurations Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-16 05:59:21 +08:00
struct regmap;
clk: qcom: Consolidate frequency finding logic There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-05 04:21:50 +08:00
struct freq_tbl;
clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-21 00:30:26 +08:00
struct clk_hw;
struct parent_map;
clk: qcom: Consolidate common probe code Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-22 08:59:37 +08:00
clk: qcom: Enable FSM mode for votable alpha PLLs The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-29 16:35:45 +08:00
#define PLL_LOCK_COUNT_SHIFT 8
#define PLL_LOCK_COUNT_MASK 0x3f
#define PLL_BIAS_COUNT_SHIFT 14
#define PLL_BIAS_COUNT_MASK 0x3f
#define PLL_VOTE_FSM_ENA BIT(20)
#define PLL_VOTE_FSM_RESET BIT(21)
clk: qcom: Consolidate common probe code Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-22 08:59:37 +08:00
struct qcom_cc_desc {
const struct regmap_config *config;
struct clk_regmap **clks;
size_t num_clks;
const struct qcom_reset_map *resets;
size_t num_resets;
clk: qcom: gdsc: Prepare common clk probe to register gdscs The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-06 18:37:43 +08:00
struct gdsc **gdscs;
size_t num_gdscs;
clk: qcom: Consolidate common probe code Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-22 08:59:37 +08:00
};
clk: qcom: Consolidate frequency finding logic There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-05 04:21:50 +08:00
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
clk: qcom: Add rcg ops to return floor value closest to the requested rate The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-21 14:37:11 +08:00
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
unsigned long rate);
clk: qcom: Enable FSM mode for votable alpha PLLs The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-29 16:35:45 +08:00
extern void
qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-21 00:30:26 +08:00
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
u8 src);
clk: qcom: Consolidate frequency finding logic There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-05 04:21:50 +08:00
clk: qcom: common: Add API to register board clocks backwards compatibly We want to put the XO board clocks into the dt files, but we also need to be backwards compatible with an older dtb. Add an API to the common code to do this. This also makes a place for us to handle the case when the RPM clock driver is enabled and we don't want to register the fixed factor clock. Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-27 08:11:32 +08:00
extern int qcom_cc_register_board_clk(struct device *dev, const char *path,
const char *name, unsigned long rate);
extern int qcom_cc_register_sleep_clk(struct device *dev);
clk: qcom: Fix PLL rate configurations Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-16 05:59:21 +08:00
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
extern int qcom_cc_really_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc,
struct regmap *regmap);
clk: qcom: Consolidate common probe code Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-22 08:59:37 +08:00
extern int qcom_cc_probe(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
#endif