2019-03-26 22:42:48 +08:00
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/acpi.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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/* Number of pins on BlueField */
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#define MLXBF_GPIO_NR 54
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/* Pad Electrical Controls. */
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#define MLXBF_GPIO_PAD_CONTROL_FIRST_WORD 0x0700
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#define MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD 0x0708
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#define MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD 0x0710
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#define MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD 0x0718
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#define MLXBF_GPIO_PIN_DIR_I 0x1040
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#define MLXBF_GPIO_PIN_DIR_O 0x1048
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#define MLXBF_GPIO_PIN_STATE 0x1000
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#define MLXBF_GPIO_SCRATCHPAD 0x20
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#ifdef CONFIG_PM
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struct mlxbf_gpio_context_save_regs {
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u64 scratchpad;
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u64 pad_control[MLXBF_GPIO_NR];
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u64 pin_dir_i;
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u64 pin_dir_o;
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};
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#endif
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/* Device state structure. */
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struct mlxbf_gpio_state {
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struct gpio_chip gc;
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/* Memory Address */
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void __iomem *base;
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#ifdef CONFIG_PM
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struct mlxbf_gpio_context_save_regs csave_regs;
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#endif
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};
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static int mlxbf_gpio_probe(struct platform_device *pdev)
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{
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struct mlxbf_gpio_state *gs;
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struct device *dev = &pdev->dev;
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struct gpio_chip *gc;
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int ret;
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gs = devm_kzalloc(&pdev->dev, sizeof(*gs), GFP_KERNEL);
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if (!gs)
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return -ENOMEM;
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gs->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(gs->base))
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return PTR_ERR(gs->base);
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gc = &gs->gc;
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ret = bgpio_init(gc, dev, 8,
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gs->base + MLXBF_GPIO_PIN_STATE,
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NULL,
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NULL,
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gs->base + MLXBF_GPIO_PIN_DIR_O,
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gs->base + MLXBF_GPIO_PIN_DIR_I,
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0);
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if (ret)
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return -ENODEV;
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gc->owner = THIS_MODULE;
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gc->ngpio = MLXBF_GPIO_NR;
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ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
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if (ret) {
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dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
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return ret;
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}
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platform_set_drvdata(pdev, gs);
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dev_info(&pdev->dev, "registered Mellanox BlueField GPIO");
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return 0;
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}
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#ifdef CONFIG_PM
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static int mlxbf_gpio_suspend(struct platform_device *pdev, pm_message_t state)
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{
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struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
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gs->csave_regs.scratchpad = readq(gs->base + MLXBF_GPIO_SCRATCHPAD);
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gs->csave_regs.pad_control[0] =
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readq(gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
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gs->csave_regs.pad_control[1] =
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readq(gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
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gs->csave_regs.pad_control[2] =
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readq(gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
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gs->csave_regs.pad_control[3] =
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readq(gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
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gs->csave_regs.pin_dir_i = readq(gs->base + MLXBF_GPIO_PIN_DIR_I);
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gs->csave_regs.pin_dir_o = readq(gs->base + MLXBF_GPIO_PIN_DIR_O);
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return 0;
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}
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static int mlxbf_gpio_resume(struct platform_device *pdev)
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{
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struct mlxbf_gpio_state *gs = platform_get_drvdata(pdev);
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writeq(gs->csave_regs.scratchpad, gs->base + MLXBF_GPIO_SCRATCHPAD);
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writeq(gs->csave_regs.pad_control[0],
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gs->base + MLXBF_GPIO_PAD_CONTROL_FIRST_WORD);
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writeq(gs->csave_regs.pad_control[1],
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gs->base + MLXBF_GPIO_PAD_CONTROL_1_FIRST_WORD);
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writeq(gs->csave_regs.pad_control[2],
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gs->base + MLXBF_GPIO_PAD_CONTROL_2_FIRST_WORD);
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writeq(gs->csave_regs.pad_control[3],
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gs->base + MLXBF_GPIO_PAD_CONTROL_3_FIRST_WORD);
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writeq(gs->csave_regs.pin_dir_i, gs->base + MLXBF_GPIO_PIN_DIR_I);
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writeq(gs->csave_regs.pin_dir_o, gs->base + MLXBF_GPIO_PIN_DIR_O);
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return 0;
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}
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#endif
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2020-06-30 21:33:43 +08:00
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static const struct acpi_device_id __maybe_unused mlxbf_gpio_acpi_match[] = {
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2019-03-26 22:42:48 +08:00
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{ "MLNXBF02", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, mlxbf_gpio_acpi_match);
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static struct platform_driver mlxbf_gpio_driver = {
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.driver = {
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.name = "mlxbf_gpio",
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.acpi_match_table = ACPI_PTR(mlxbf_gpio_acpi_match),
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},
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.probe = mlxbf_gpio_probe,
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#ifdef CONFIG_PM
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.suspend = mlxbf_gpio_suspend,
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.resume = mlxbf_gpio_resume,
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#endif
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};
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module_platform_driver(mlxbf_gpio_driver);
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MODULE_DESCRIPTION("Mellanox BlueField GPIO Driver");
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MODULE_AUTHOR("Mellanox Technologies");
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MODULE_LICENSE("GPL");
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