2014-06-04 04:03:58 +08:00
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/*
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* Thunderbolt Cactus Ridge driver - NHI driver
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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*/
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#ifndef DSL3510_H_
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#define DSL3510_H_
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2017-06-06 20:24:57 +08:00
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#include <linux/idr.h>
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2014-06-04 04:03:58 +08:00
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#include <linux/mutex.h>
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#include <linux/workqueue.h>
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/**
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* struct tb_nhi - thunderbolt native host interface
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2017-06-06 20:24:57 +08:00
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* @lock: Must be held during ring creation/destruction. Is acquired by
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* interrupt_work when dispatching interrupts to individual rings.
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* @pdev: Pointer to the PCI device
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* @iobase: MMIO space of the NHI
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* @tx_rings: All Tx rings available on this host controller
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* @rx_rings: All Rx rings available on this host controller
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* @msix_ida: Used to allocate MSI-X vectors for rings
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2017-06-06 20:25:15 +08:00
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* @going_away: The host controller device is about to disappear so when
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* this flag is set, avoid touching the hardware anymore.
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2017-06-06 20:24:57 +08:00
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* @interrupt_work: Work scheduled to handle ring interrupt when no
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* MSI-X is used.
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* @hop_count: Number of rings (end point hops) supported by NHI.
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2014-06-04 04:03:58 +08:00
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*/
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struct tb_nhi {
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2017-06-06 20:24:57 +08:00
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struct mutex lock;
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2014-06-04 04:03:58 +08:00
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struct pci_dev *pdev;
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void __iomem *iobase;
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struct tb_ring **tx_rings;
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struct tb_ring **rx_rings;
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2017-06-06 20:24:57 +08:00
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struct ida msix_ida;
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2017-06-06 20:25:15 +08:00
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bool going_away;
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2014-06-04 04:03:58 +08:00
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struct work_struct interrupt_work;
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2017-06-06 20:24:57 +08:00
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u32 hop_count;
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2014-06-04 04:03:58 +08:00
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};
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/**
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* struct tb_ring - thunderbolt TX or RX ring associated with a NHI
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2017-06-06 20:24:57 +08:00
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* @lock: Lock serializing actions to this ring. Must be acquired after
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* nhi->lock.
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* @nhi: Pointer to the native host controller interface
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* @size: Size of the ring
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* @hop: Hop (DMA channel) associated with this ring
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* @head: Head of the ring (write next descriptor here)
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* @tail: Tail of the ring (complete next descriptor here)
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* @descriptors: Allocated descriptors for this ring
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* @queue: Queue holding frames to be transferred over this ring
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* @in_flight: Queue holding frames that are currently in flight
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* @work: Interrupt work structure
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* @is_tx: Is the ring Tx or Rx
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* @running: Is the ring running
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* @irq: MSI-X irq number if the ring uses MSI-X. %0 otherwise.
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* @vector: MSI-X vector number the ring uses (only set if @irq is > 0)
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* @flags: Ring specific flags
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2014-06-04 04:03:58 +08:00
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*/
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struct tb_ring {
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struct mutex lock;
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2014-06-04 04:03:58 +08:00
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struct tb_nhi *nhi;
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int size;
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int hop;
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2017-06-06 20:24:57 +08:00
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int head;
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int tail;
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2014-06-04 04:03:58 +08:00
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struct ring_desc *descriptors;
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dma_addr_t descriptors_dma;
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struct list_head queue;
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struct list_head in_flight;
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struct work_struct work;
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2017-06-06 20:24:57 +08:00
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bool is_tx:1;
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2014-06-04 04:03:58 +08:00
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bool running:1;
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2017-06-06 20:24:57 +08:00
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int irq;
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u8 vector;
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unsigned int flags;
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2014-06-04 04:03:58 +08:00
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};
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2017-06-06 20:24:57 +08:00
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/* Leave ring interrupt enabled on suspend */
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#define RING_FLAG_NO_SUSPEND BIT(0)
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2014-06-04 04:03:58 +08:00
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struct ring_frame;
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typedef void (*ring_cb)(struct tb_ring*, struct ring_frame*, bool canceled);
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/**
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* struct ring_frame - for use with ring_rx/ring_tx
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*/
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struct ring_frame {
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dma_addr_t buffer_phy;
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ring_cb callback;
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struct list_head list;
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u32 size:12; /* TX: in, RX: out*/
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u32 flags:12; /* RX: out */
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u32 eof:4; /* TX:in, RX: out */
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u32 sof:4; /* TX:in, RX: out */
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};
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#define TB_FRAME_SIZE 0x100 /* minimum size for ring_rx */
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2017-06-06 20:24:57 +08:00
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struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags);
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struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
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unsigned int flags);
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2014-06-04 04:03:58 +08:00
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void ring_start(struct tb_ring *ring);
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void ring_stop(struct tb_ring *ring);
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void ring_free(struct tb_ring *ring);
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int __ring_enqueue(struct tb_ring *ring, struct ring_frame *frame);
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/**
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* ring_rx() - enqueue a frame on an RX ring
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*
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* frame->buffer, frame->buffer_phy and frame->callback have to be set. The
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* buffer must contain at least TB_FRAME_SIZE bytes.
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*
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* frame->callback will be invoked with frame->size, frame->flags, frame->eof,
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* frame->sof set once the frame has been received.
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*
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* If ring_stop is called after the packet has been enqueued frame->callback
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* will be called with canceled set to true.
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*
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* Return: Returns ESHUTDOWN if ring_stop has been called. Zero otherwise.
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*/
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static inline int ring_rx(struct tb_ring *ring, struct ring_frame *frame)
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{
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WARN_ON(ring->is_tx);
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return __ring_enqueue(ring, frame);
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}
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/**
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* ring_tx() - enqueue a frame on an TX ring
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*
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* frame->buffer, frame->buffer_phy, frame->callback, frame->size, frame->eof
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* and frame->sof have to be set.
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*
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* frame->callback will be invoked with once the frame has been transmitted.
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*
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* If ring_stop is called after the packet has been enqueued frame->callback
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* will be called with canceled set to true.
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*
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* Return: Returns ESHUTDOWN if ring_stop has been called. Zero otherwise.
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*/
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static inline int ring_tx(struct tb_ring *ring, struct ring_frame *frame)
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{
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WARN_ON(!ring->is_tx);
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return __ring_enqueue(ring, frame);
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}
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2017-06-06 20:25:12 +08:00
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enum nhi_fw_mode {
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NHI_FW_SAFE_MODE,
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NHI_FW_AUTH_MODE,
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NHI_FW_EP_MODE,
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NHI_FW_CM_MODE,
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};
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enum nhi_mailbox_cmd {
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NHI_MAILBOX_SAVE_DEVS = 0x05,
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2017-06-06 20:25:17 +08:00
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NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
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2017-06-06 20:25:12 +08:00
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NHI_MAILBOX_DRV_UNLOADS = 0x07,
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NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
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};
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int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
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enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
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2017-06-06 20:25:11 +08:00
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/*
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* PCI IDs used in this driver from Win Ridge forward. There is no
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* need for the PCI quirk anymore as we will use ICM also on Apple
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* hardware.
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*/
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
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#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
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#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
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2014-06-04 04:03:58 +08:00
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#endif
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