2019-05-30 07:57:46 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2013-01-18 17:42:21 +08:00
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#include <linux/ptrace.h>
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2013-01-18 17:42:23 +08:00
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include <linux/kdev_t.h>
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#include <linux/proc_fs.h>
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#include <linux/file.h>
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2017-02-09 01:51:29 +08:00
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#include <linux/sched/mm.h>
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2017-02-09 01:51:35 +08:00
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#include <linux/sched/debug.h>
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2017-02-09 01:51:29 +08:00
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2013-01-18 17:42:23 +08:00
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#include <asm/arcregs.h>
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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#include <asm/irqflags.h>
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2013-01-18 17:42:23 +08:00
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2018-12-18 06:11:19 +08:00
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#define ARC_PATH_MAX 256
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2013-01-18 17:42:23 +08:00
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/*
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* Common routine to print scratch regs (r0-r12) or callee regs (r13-r25)
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* -Prints 3 regs per line and a CR.
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* -To continue, callee regs right after scratch, special handling of CR
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*/
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static noinline void print_reg_file(long *reg_rev, int start_num)
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{
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unsigned int i;
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char buf[512];
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int n = 0, len = sizeof(buf);
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for (i = start_num; i < start_num + 13; i++) {
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n += scnprintf(buf + n, len - n, "r%02u: 0x%08lx\t",
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i, (unsigned long)*reg_rev);
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if (((i + 1) % 3) == 0)
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n += scnprintf(buf + n, len - n, "\n");
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2013-03-22 19:46:49 +08:00
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/* because pt_regs has regs reversed: r12..r0, r25..r13 */
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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if (is_isa_arcv2() && start_num == 0)
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reg_rev++;
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else
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reg_rev--;
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2013-01-18 17:42:23 +08:00
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}
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if (start_num != 0)
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n += scnprintf(buf + n, len - n, "\n\n");
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2013-03-22 19:46:49 +08:00
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/* To continue printing callee regs on same line as scratch regs */
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if (start_num == 0)
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pr_info("%s", buf);
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else
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pr_cont("%s\n", buf);
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2013-01-18 17:42:23 +08:00
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}
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static void show_callee_regs(struct callee_regs *cregs)
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{
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print_reg_file(&(cregs->r13), 13);
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}
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2018-12-18 06:11:19 +08:00
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static void print_task_path_n_nm(struct task_struct *tsk)
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2013-01-18 17:42:23 +08:00
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{
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char *path_nm = NULL;
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struct mm_struct *mm;
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struct file *exe_file;
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2018-12-18 06:11:19 +08:00
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char buf[ARC_PATH_MAX];
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2013-01-18 17:42:23 +08:00
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mm = get_task_mm(tsk);
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if (!mm)
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goto done;
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exe_file = get_mm_exe_file(mm);
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mmput(mm);
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if (exe_file) {
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2018-12-18 06:11:19 +08:00
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path_nm = file_path(exe_file, buf, ARC_PATH_MAX-1);
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2013-01-18 17:42:23 +08:00
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fput(exe_file);
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}
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done:
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2015-06-19 16:29:13 +08:00
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pr_info("Path: %s\n", !IS_ERR(path_nm) ? path_nm : "?");
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2013-01-18 17:42:23 +08:00
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}
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2018-12-18 06:11:19 +08:00
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static void show_faulting_vma(unsigned long address)
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2013-01-18 17:42:23 +08:00
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{
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struct vm_area_struct *vma;
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2014-06-05 07:07:29 +08:00
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struct mm_struct *active_mm = current->active_mm;
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2013-01-18 17:42:23 +08:00
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2013-03-22 19:46:49 +08:00
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/* can't use print_vma_addr() yet as it doesn't check for
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* non-inclusive vma
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*/
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2020-06-09 12:33:25 +08:00
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mmap_read_lock(active_mm);
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2014-06-05 07:07:29 +08:00
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vma = find_vma(active_mm, address);
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2013-01-18 17:42:23 +08:00
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/* check against the find_vma( ) behaviour which returns the next VMA
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* if the container VMA is not found
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*/
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if (vma && (vma->vm_start <= address)) {
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2018-12-18 06:11:19 +08:00
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char buf[ARC_PATH_MAX];
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char *nm = "?";
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2018-08-07 00:44:23 +08:00
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if (vma->vm_file) {
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2018-12-18 06:11:19 +08:00
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nm = file_path(vma->vm_file, buf, ARC_PATH_MAX-1);
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2018-08-07 00:44:23 +08:00
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if (IS_ERR(nm))
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nm = "?";
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2013-01-18 17:42:23 +08:00
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}
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2020-03-04 14:10:01 +08:00
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pr_info(" @off 0x%lx in [%s] VMA: 0x%08lx to 0x%08lx\n",
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2013-03-22 19:46:49 +08:00
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vma->vm_start < TASK_UNMAPPED_BASE ?
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address : address - vma->vm_start,
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nm, vma->vm_start, vma->vm_end);
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2014-06-05 07:07:29 +08:00
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} else
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2013-01-18 17:42:23 +08:00
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pr_info(" @No matching VMA found\n");
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2014-06-05 07:07:29 +08:00
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2020-06-09 12:33:25 +08:00
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mmap_read_unlock(active_mm);
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2013-01-18 17:42:23 +08:00
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}
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static void show_ecr_verbose(struct pt_regs *regs)
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{
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2013-06-11 21:26:54 +08:00
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unsigned int vec, cause_code;
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2013-01-18 17:42:23 +08:00
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unsigned long address;
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/* For Data fault, this is data address not instruction addr */
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address = current->thread.fault_address;
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2013-06-11 21:26:54 +08:00
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vec = regs->ecr_vec;
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cause_code = regs->ecr_cause;
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2013-01-18 17:42:23 +08:00
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/* For DTLB Miss or ProtV, display the memory involved too */
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if (vec == ECR_V_DTLB_MISS) {
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2020-03-04 14:10:01 +08:00
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pr_cont("Invalid %s @ 0x%08lx by insn @ %pS\n",
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2013-06-12 18:05:18 +08:00
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(cause_code == 0x01) ? "Read" :
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((cause_code == 0x02) ? "Write" : "EX"),
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2020-03-04 14:10:01 +08:00
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address, (void *)regs->ret);
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2013-01-18 17:42:23 +08:00
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} else if (vec == ECR_V_ITLB_MISS) {
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pr_cont("Insn could not be fetched\n");
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} else if (vec == ECR_V_MACH_CHK) {
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2017-08-29 17:14:20 +08:00
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pr_cont("Machine Check (%s)\n", (cause_code == 0x0) ?
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2013-01-18 17:42:23 +08:00
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"Double Fault" : "Other Fatal Err");
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} else if (vec == ECR_V_PROTV) {
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if (cause_code == ECR_C_PROTV_INST_FETCH)
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pr_cont("Execute from Non-exec Page\n");
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2019-01-31 00:32:41 +08:00
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else if (cause_code == ECR_C_PROTV_MISALIG_DATA &&
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IS_ENABLED(CONFIG_ISA_ARCOMPACT))
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2013-01-18 17:42:23 +08:00
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pr_cont("Misaligned r/w from 0x%08lx\n", address);
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2013-06-12 18:05:18 +08:00
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else
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pr_cont("%s access not allowed on page\n",
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(cause_code == 0x01) ? "Read" :
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((cause_code == 0x02) ? "Write" : "EX"));
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2013-01-18 17:42:23 +08:00
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} else if (vec == ECR_V_INSN_ERR) {
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pr_cont("Illegal Insn\n");
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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#ifdef CONFIG_ISA_ARCV2
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} else if (vec == ECR_V_MEM_ERR) {
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if (cause_code == 0x00)
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pr_cont("Bus Error from Insn Mem\n");
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else if (cause_code == 0x10)
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pr_cont("Bus Error from Data Mem\n");
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else
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pr_cont("Bus Error, check PRM\n");
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2019-01-31 00:32:41 +08:00
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} else if (vec == ECR_V_MISALIGN) {
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pr_cont("Misaligned r/w from 0x%08lx\n", address);
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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#endif
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2017-12-21 04:37:54 +08:00
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} else if (vec == ECR_V_TRAP) {
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if (regs->ecr_param == 5)
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pr_cont("gcc generated __builtin_trap\n");
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2013-01-18 17:42:23 +08:00
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} else {
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pr_cont("Check Programmer's Manual\n");
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}
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}
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/************************************************************************
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* API called by rest of kernel
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***********************************************************************/
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2013-01-18 17:42:21 +08:00
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void show_regs(struct pt_regs *regs)
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{
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2013-01-18 17:42:23 +08:00
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struct task_struct *tsk = current;
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struct callee_regs *cregs;
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2018-12-19 02:39:58 +08:00
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/*
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* generic code calls us with preemption disabled, but some calls
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* here could sleep, so re-enable to avoid lockdep splat
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*/
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preempt_enable();
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2018-12-18 06:11:19 +08:00
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print_task_path_n_nm(tsk);
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dump_stack: unify debug information printed by show_regs()
show_regs() is inherently arch-dependent but it does make sense to print
generic debug information and some archs already do albeit in slightly
different forms. This patch introduces a generic function to print debug
information from show_regs() so that different archs print out the same
information and it's much easier to modify what's printed.
show_regs_print_info() prints out the same debug info as dump_stack()
does plus task and thread_info pointers.
* Archs which didn't print debug info now do.
alpha, arc, blackfin, c6x, cris, frv, h8300, hexagon, ia64, m32r,
metag, microblaze, mn10300, openrisc, parisc, score, sh64, sparc,
um, xtensa
* Already prints debug info. Replaced with show_regs_print_info().
The printed information is superset of what used to be there.
arm, arm64, avr32, mips, powerpc, sh32, tile, unicore32, x86
* s390 is special in that it used to print arch-specific information
along with generic debug info. Heiko and Martin think that the
arch-specific extra isn't worth keeping s390 specfic implementation.
Converted to use the generic version.
Note that now all archs print the debug info before actual register
dumps.
An example BUG() dump follows.
kernel BUG at /work/os/work/kernel/workqueue.c:4841!
invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.9.0-rc1-work+ #7
Hardware name: empty empty/S3992, BIOS 080011 10/26/2007
task: ffff88007c85e040 ti: ffff88007c860000 task.ti: ffff88007c860000
RIP: 0010:[<ffffffff8234a07e>] [<ffffffff8234a07e>] init_workqueues+0x4/0x6
RSP: 0000:ffff88007c861ec8 EFLAGS: 00010246
RAX: ffff88007c861fd8 RBX: ffffffff824466a8 RCX: 0000000000000001
RDX: 0000000000000046 RSI: 0000000000000001 RDI: ffffffff8234a07a
RBP: ffff88007c861ec8 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000001 R11: 0000000000000000 R12: ffffffff8234a07a
R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000
FS: 0000000000000000(0000) GS:ffff88007dc00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b
CR2: ffff88015f7ff000 CR3: 00000000021f1000 CR4: 00000000000007f0
DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
Stack:
ffff88007c861ef8 ffffffff81000312 ffffffff824466a8 ffff88007c85e650
0000000000000003 0000000000000000 ffff88007c861f38 ffffffff82335e5d
ffff88007c862080 ffffffff8223d8c0 ffff88007c862080 ffffffff81c47760
Call Trace:
[<ffffffff81000312>] do_one_initcall+0x122/0x170
[<ffffffff82335e5d>] kernel_init_freeable+0x9b/0x1c8
[<ffffffff81c47760>] ? rest_init+0x140/0x140
[<ffffffff81c4776e>] kernel_init+0xe/0xf0
[<ffffffff81c6be9c>] ret_from_fork+0x7c/0xb0
[<ffffffff81c47760>] ? rest_init+0x140/0x140
...
v2: Typo fix in x86-32.
v3: CPU number dropped from show_regs_print_info() as
dump_stack_print_info() has been updated to print it. s390
specific implementation dropped as requested by s390 maintainers.
Signed-off-by: Tejun Heo <tj@kernel.org>
Acked-by: David S. Miller <davem@davemloft.net>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Chris Metcalf <cmetcalf@tilera.com> [tile bits]
Acked-by: Richard Kuo <rkuo@codeaurora.org> [hexagon bits]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-05-01 06:27:17 +08:00
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show_regs_print_info(KERN_INFO);
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2013-01-18 17:42:23 +08:00
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2013-06-11 21:26:54 +08:00
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show_ecr_verbose(regs);
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2013-01-18 17:42:23 +08:00
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2013-03-22 19:46:49 +08:00
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if (user_mode(regs))
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2018-12-18 06:11:19 +08:00
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show_faulting_vma(regs->ret); /* faulting code, not data */
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2013-01-18 17:42:23 +08:00
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2020-05-06 03:19:22 +08:00
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pr_info("ECR: 0x%08lx EFA: 0x%08lx ERET: 0x%08lx\nSTAT: 0x%08lx",
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regs->event, current->thread.fault_address, regs->ret,
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regs->status32);
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2013-03-22 19:46:49 +08:00
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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#define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : ""
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2013-01-18 17:42:23 +08:00
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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#ifdef CONFIG_ISA_ARCOMPACT
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2020-03-04 14:10:01 +08:00
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pr_cont(" [%2s%2s%2s%2s%2s%2s%2s]",
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
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(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
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STS_BIT(regs, DE), STS_BIT(regs, AE),
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STS_BIT(regs, A2), STS_BIT(regs, A1),
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STS_BIT(regs, E2), STS_BIT(regs, E1));
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#else
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2020-03-04 14:10:01 +08:00
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pr_cont(" [%2s%2s%2s%2s]",
|
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 21:00:41 +08:00
|
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STS_BIT(regs, IE),
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(regs->status32 & STATUS_U_MASK) ? "U " : "K ",
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STS_BIT(regs, DE), STS_BIT(regs, AE));
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#endif
|
2020-05-06 03:19:22 +08:00
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pr_cont(" BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
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regs->bta, regs->sp, regs->fp, (void *)regs->blink);
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2013-01-18 17:42:23 +08:00
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pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
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2020-05-06 03:19:22 +08:00
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regs->lp_start, regs->lp_end, regs->lp_count);
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2013-01-18 17:42:23 +08:00
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/* print regs->r0 thru regs->r12
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* Sequential printing was generating horrible code
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*/
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print_reg_file(&(regs->r0), 0);
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/* If Callee regs were saved, display them too */
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cregs = (struct callee_regs *)current->thread.callee_reg;
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if (cregs)
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show_callee_regs(cregs);
|
2018-12-19 02:39:58 +08:00
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preempt_disable();
|
2013-01-18 17:42:21 +08:00
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}
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void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
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2013-06-12 17:43:40 +08:00
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unsigned long address)
|
2013-01-18 17:42:21 +08:00
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{
|
2013-01-18 17:42:23 +08:00
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current->thread.fault_address = address;
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|
2017-08-29 17:14:20 +08:00
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/* Show fault description */
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pr_info("\n%s\n", str);
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2013-01-18 17:42:23 +08:00
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/* Caller and Callee regs */
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show_regs(regs);
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/* Show stack trace if this Fatality happened in kernel mode */
|
|
|
|
if (!user_mode(regs))
|
2020-06-09 12:30:04 +08:00
|
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|
show_stacktrace(current, regs, KERN_DEFAULT);
|
2013-01-18 17:42:21 +08:00
|
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|
}
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