hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
linux-sg2042/drivers/clk/qcom/clk-rcg.h

165 lines
3.8 KiB
C
Raw Normal View History

clk: qcom: Configure the RCGs to a safe source as needed For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
#ifndef __QCOM_CLK_RCG_H__
#define __QCOM_CLK_RCG_H__
#include <linux/clk-provider.h>
#include "clk-regmap.h"
struct freq_tbl {
unsigned long freq;
u8 src;
u8 pre_div;
u16 m;
u16 n;
};
/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
* @mnctr_reset_bit: bit to assert mn counter reset
* @mnctr_mode_shift: lowest bit of mn counter mode field
* @n_val_shift: lowest bit of n value field
* @m_val_shift: lowest bit of m value field
* @width: number of bits in m/n/d values
* @reset_in_cc: true if the mnctr_reset_bit is in the CC register
*/
struct mn {
u8 mnctr_en_bit;
u8 mnctr_reset_bit;
u8 mnctr_mode_shift;
#define MNCTR_MODE_DUAL 0x2
#define MNCTR_MODE_MASK 0x3
u8 n_val_shift;
u8 m_val_shift;
u8 width;
bool reset_in_cc;
};
/**
* struct pre_div - pre-divider
* @pre_div_shift: lowest bit of pre divider field
* @pre_div_width: number of bits in predivider
*/
struct pre_div {
u8 pre_div_shift;
u8 pre_div_width;
};
/**
* struct src_sel - source selector
* @src_sel_shift: lowest bit of source selection field
* @parent_map: map from software's parent index to hardware's src_sel field
*/
struct src_sel {
u8 src_sel_shift;
#define SRC_SEL_MASK 0x7
clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-21 00:30:26 +08:00
const struct parent_map *parent_map;
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
};
/**
* struct clk_rcg - root clock generator
*
* @ns_reg: NS register
* @md_reg: MD register
* @mn: mn counter
* @p: pre divider
* @s: source selector
* @freq_tbl: frequency table
* @clkr: regmap clock handle
* @lock: register lock
*
*/
struct clk_rcg {
u32 ns_reg;
u32 md_reg;
struct mn mn;
struct pre_div p;
struct src_sel s;
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_rcg_ops;
clk: qcom: Support bypass RCG configuration In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-12 03:55:27 +08:00
extern const struct clk_ops clk_rcg_bypass_ops;
clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGs DSI specific RCG clocks required customized clk_ops. There are a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. There are a total of 2 clocks coming from the DSI PLL, which serve as inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by another divider of the PLL. In each of the 2 groups above, only one of the clocks sets its parent. These are BYTE RCG and DSI RCG for each of the groups respectively, as shown in the diagram below. The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't take in a freq table, since the DSI driver using these clocks is parent-able. The PIXEL RCG needs to derive the required pixel clock using dsixpll. It parses a m/n frac table to retrieve the correct clock. The ESC RCG doesn't have a frac M/N block, it can just apply a pre- divider. Its ops simply check if the required clock rate can be achieved by the pre-divider. +-------------------+ | |---dsixpllbyte---o---> To byte RCG | | | (sets parent rate) | | | | | | | DSI 1/2 PLL | | | | o---> To esc RCG | | (doesn't set parent rate) | | | |----dsixpll-----o---> To dsi RCG +-------------------+ | (sets parent rate) ( x = 1, 2 ) | | o---> To pixel rcg (doesn't set parent rate) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-14 20:54:44 +08:00
extern const struct clk_ops clk_rcg_bypass2_ops;
extern const struct clk_ops clk_rcg_pixel_ops;
extern const struct clk_ops clk_rcg_esc_ops;
clk: qcom: Properly change rates for ahbix clock The ahbix clock can never be turned off in practice. To change the rates we need to switch the mux off the M/N counter to an always on source (XO), reprogram the M/N counter to get the rate we want and finally switch back to the M/N counter. Add a new ops structure for this type of clock so that we can set the rate properly. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-07 07:41:53 +08:00
extern const struct clk_ops clk_rcg_lcc_ops;
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
/**
* struct clk_dyn_rcg - root clock generator with glitch free mux
*
* @mux_sel_bit: bit to switch glitch free mux
clk: qcom: Add support for banked MD RCGs The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-04-29 06:59:16 +08:00
* @ns_reg: NS0 and NS1 register
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
* @md_reg: MD0 and MD1 register
clk: qcom: Add support for banked MD RCGs The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-04-29 06:59:16 +08:00
* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
* @mn: mn counter (banked)
* @s: source selector (banked)
* @freq_tbl: frequency table
* @clkr: regmap clock handle
* @lock: register lock
*
*/
struct clk_dyn_rcg {
clk: qcom: Add support for banked MD RCGs The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-04-29 06:59:16 +08:00
u32 ns_reg[2];
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
u32 md_reg[2];
clk: qcom: Add support for banked MD RCGs The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-04-29 06:59:16 +08:00
u32 bank_reg;
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
u8 mux_sel_bit;
struct mn mn[2];
struct pre_div p[2];
struct src_sel s[2];
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_dyn_rcg_ops;
#define to_clk_dyn_rcg(_hw) \
container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
/**
* struct clk_rcg2 - root clock generator
*
* @cmd_rcgr: corresponds to *_CMD_RCGR
* @mnd_width: number of bits in m/n/d values
* @hid_width: number of bits in half integer divider
clk: qcom: Configure the RCGs to a safe source as needed For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
* @safe_src_index: safe src index value
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
* @parent_map: map from software's parent index to hardware's src_sel field
* @freq_tbl: frequency table
* @clkr: regmap clock handle
*
*/
struct clk_rcg2 {
u32 cmd_rcgr;
u8 mnd_width;
u8 hid_width;
clk: qcom: Configure the RCGs to a safe source as needed For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
u8 safe_src_index;
clk: qcom: Introduce parent_map tables In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-21 00:30:26 +08:00
const struct parent_map *parent_map;
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
};
#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
extern const struct clk_ops clk_rcg2_ops;
clk: qcom: Add rcg ops to return floor value closest to the requested rate The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-21 14:37:11 +08:00
extern const struct clk_ops clk_rcg2_floor_ops;
clk: qcom: Support display RCG clocks Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-17 07:07:11 +08:00
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
clk: qcom: Allow clk_set_parent() to work on display clocks Sometimes the display driver may want to change the parent PLL of the display clocks (byte and pixel clocks) depending on the use-case. Currently the parent is fixed by means of having a frequency table with one entry that chooses a particular parent. Remove this restriction and use the parent the clock is configured for in the hardware during clk_set_rate(). This requires consumers to rely on the default parent or to configure the parent with clk_set_parent()/assigned-clock-parents on the clocks before calling clk_set_rate(). Tested-by: Archit Taneja <architt@codeaurora.org> Cc: Hai Li <hali@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-10 14:02:02 +08:00
extern const struct clk_ops clk_byte2_ops;
clk: qcom: Support display RCG clocks Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-17 07:07:11 +08:00
extern const struct clk_ops clk_pixel_ops;
clk: qcom: Add gfx3d ping-pong PLL frequency switching The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2, MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624 MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To make switching frequencies faster, we ping-pong between MMPLL2 and MMPLL8 when we're switching between frequencies that aren't the maximum. Implement custom rcg clk ops for this type of frequency switching. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 09:31:41 +08:00
extern const struct clk_ops clk_gfx3d_ops;
clk: qcom: Configure the RCGs to a safe source as needed For some root clock generators, there could be child branches which are controlled by an entity other than application processor subsystem. For such RCGs, as per application processor subsystem clock driver, all of its downstream clocks are disabled and RCG is in disabled state but in reality downstream clocks can be left enabled before. So in this scenario, when RCG is disabled as per clock driver's point of view and when rate scaling request comes before downstream clock enable request, then RCG fails to update its configuration because in reality RCG is on and it expects its new source to already be in enable state but in reality new source is off. In order to avoid having the RCG to go into an invalid state, add support to update the CFG, M, N and D registers during set_rate() without configuration update and defer the actual RCG configuration update to be done during clk_enable() as at this point of time, both its new parent and safe source will be already enabled and RCG can safely switch to new parent. During clk_disable() request, configure it to safe source as both its parents, safe source and current parent will be enabled and RCG can safely execute a switch. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-05-07 18:50:18 +08:00
extern const struct clk_ops clk_rcg2_shared_ops;
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-16 02:47:25 +08:00
#endif