2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2017-10-17 02:04:33 +08:00
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menu "IRQ chip support"
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irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 06:00:52 +08:00
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config IRQCHIP
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def_bool y
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depends on OF_IRQ
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2012-11-21 11:21:40 +08:00
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config ARM_GIC
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bool
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2014-11-25 16:04:19 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2017-08-18 16:39:16 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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2012-11-21 11:21:40 +08:00
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irqchip/gic: Add platform driver for non-root GICs that require RPM
Add a platform driver to support non-root GICs that require runtime
power-management. Currently, only non-root GICs are supported because
the functions, smp_cross_call() and set_handle_irq(), that need to
be called for a root controller are located in the __init section and
so cannot be called by the platform driver.
The GIC platform driver re-uses many functions from the existing GIC
driver including some functions to save and restore the GIC context
during power transitions. The functions for saving and restoring the
GIC context are currently only defined if CONFIG_CPU_PM is enabled and
to ensure that these functions are always defined when the platform
driver is enabled, a dependency on CONFIG_ARM_GIC_PM (which selects the
platform driver) has been added.
In order to re-use the private GIC initialisation code, a new public
function, gic_of_init_child(), has been added which calls various
private functions to initialise the GIC. This is different from the
existing gic_of_init() because it only supports non-root GICs (ie. does
not call smp_cross_call() is set_handle_irq()) and is not located in
the __init section (so can be used by platform drivers). Furthermore,
gic_of_init_child() dynamically allocates memory for the GIC chip data
which is also different from gic_of_init().
There is no specific suspend handling for GICs registered as platform
devices. Non-wakeup interrupts will be disabled by the kernel during
late suspend, however, this alone will not power down the GIC if
interrupts have been requested and not freed. Therefore, requestors of
non-wakeup interrupts will need to free them on entering suspend in
order to power-down the GIC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-06-07 23:12:34 +08:00
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config ARM_GIC_PM
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bool
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depends on PM
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select ARM_GIC
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2015-12-18 17:44:53 +08:00
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config ARM_GIC_MAX_NR
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int
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2019-06-14 20:57:09 +08:00
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depends on ARM_GIC
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2015-12-18 17:44:53 +08:00
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default 2 if ARCH_REALVIEW
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default 1
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2014-11-26 02:47:22 +08:00
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config ARM_GIC_V2M
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bool
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2016-06-16 04:47:33 +08:00
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depends on PCI
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select ARM_GIC
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select PCI_MSI
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2014-11-26 02:47:22 +08:00
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2012-11-21 11:21:40 +08:00
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config GIC_NON_BANKED
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bool
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2014-06-30 23:01:31 +08:00
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config ARM_GIC_V3
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bool
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2014-11-24 22:35:09 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2016-04-11 16:57:54 +08:00
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select PARTITION_PERCPU
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2017-08-18 16:39:17 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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2014-06-30 23:01:31 +08:00
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2014-11-24 22:35:19 +08:00
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config ARM_GIC_V3_ITS
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bool
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2017-11-14 01:25:59 +08:00
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select GENERIC_MSI_IRQ_DOMAIN
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default ARM_GIC_V3
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config ARM_GIC_V3_ITS_PCI
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bool
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depends on ARM_GIC_V3_ITS
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2016-06-16 04:47:33 +08:00
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depends on PCI
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depends on PCI_MSI
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2017-11-14 01:25:59 +08:00
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default ARM_GIC_V3_ITS
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2014-06-30 23:01:31 +08:00
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2018-02-05 22:07:43 +08:00
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config ARM_GIC_V3_ITS_FSL_MC
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bool
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depends on ARM_GIC_V3_ITS
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depends on FSL_MC_BUS
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default ARM_GIC_V3_ITS
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2013-06-26 15:18:48 +08:00
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config ARM_NVIC
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bool
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2015-05-16 17:44:16 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2013-06-26 15:18:48 +08:00
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select GENERIC_IRQ_CHIP
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2012-10-28 06:25:26 +08:00
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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2016-02-10 22:46:56 +08:00
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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2016-06-16 04:47:33 +08:00
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select PCI_MSI if PCI
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2017-08-18 16:39:19 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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2016-02-10 22:46:56 +08:00
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2016-02-19 23:22:44 +08:00
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config ALPINE_MSI
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bool
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2016-06-16 04:47:33 +08:00
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depends on PCI
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select PCI_MSI
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2016-02-19 23:22:44 +08:00
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select GENERIC_IRQ_CHIP
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2019-06-10 16:34:43 +08:00
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config AL_FIC
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bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
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depends on OF || COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Support Amazon's Annapurna Labs Fabric Interrupt Controller.
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2014-07-11 01:14:18 +08:00
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select SPARSE_IRQ
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2015-07-08 20:46:08 +08:00
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config I8259
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bool
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select IRQ_DOMAIN
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2015-11-22 22:30:14 +08:00
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2017-08-18 16:39:20 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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2015-11-22 22:30:14 +08:00
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IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-26 01:49:06 +08:00
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config BCM7038_L1_IRQ
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2021-10-21 02:48:52 +08:00
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tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BRCMSTB || BMIPS_GENERIC
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IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-26 01:49:06 +08:00
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2017-08-18 16:39:21 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-26 01:49:06 +08:00
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2014-11-07 14:44:27 +08:00
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config BCM7120_L2_IRQ
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2021-10-21 02:48:56 +08:00
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tristate "Broadcom STB 7120-style L2 interrupt controller driver"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BRCMSTB || BMIPS_GENERIC
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2014-11-07 14:44:27 +08:00
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2014-05-24 08:40:53 +08:00
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config BRCMSTB_L2_IRQ
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2021-10-21 02:48:54 +08:00
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tristate "Broadcom STB generic L2 interrupt controller driver"
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depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
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default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
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2014-05-24 08:40:53 +08:00
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2019-02-14 22:52:16 +08:00
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config DAVINCI_AINTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2019-02-14 22:52:30 +08:00
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config DAVINCI_CP_INTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2013-09-09 20:01:20 +08:00
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config DW_APB_ICTL
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bool
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2014-10-22 20:59:10 +08:00
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select GENERIC_IRQ_CHIP
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2020-09-24 15:17:51 +08:00
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select IRQ_DOMAIN_HIERARCHY
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2013-09-09 20:01:20 +08:00
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2017-03-19 00:53:24 +08:00
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select SPARSE_IRQ
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2016-03-23 17:06:33 +08:00
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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2013-04-22 22:43:50 +08:00
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2019-01-25 23:41:25 +08:00
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config IXP4XX_IRQ
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bool
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select IRQ_DOMAIN
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select SPARSE_IRQ
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2018-12-14 22:44:16 +08:00
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config MADERA_IRQ
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tristate
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2015-05-27 00:20:06 +08:00
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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2017-03-31 03:06:11 +08:00
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select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
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2015-05-27 00:20:06 +08:00
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select IRQ_DOMAIN
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2017-08-18 16:39:24 +08:00
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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2015-05-27 00:20:06 +08:00
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2014-02-02 16:07:46 +08:00
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select SPARSE_IRQ
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default y
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2017-10-30 20:38:35 +08:00
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config OMPIC
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bool
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2014-05-27 04:31:42 +08:00
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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2014-09-16 05:15:02 +08:00
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2013-06-07 00:27:09 +08:00
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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2016-01-14 09:15:35 +08:00
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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2016-08-04 12:30:37 +08:00
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config JCORE_AIC
|
2016-10-20 01:53:52 +08:00
|
|
|
bool "J-Core integrated AIC" if COMPILE_TEST
|
|
|
|
|
depends on OF
|
2016-08-04 12:30:37 +08:00
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
Support for the J-Core integrated AIC.
|
|
|
|
|
|
2018-12-11 01:35:43 +08:00
|
|
|
config RDA_INTC
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
|
2013-02-18 22:28:34 +08:00
|
|
|
config RENESAS_INTC_IRQPIN
|
2019-06-07 17:50:36 +08:00
|
|
|
bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
|
2013-02-18 22:28:34 +08:00
|
|
|
select IRQ_DOMAIN
|
2019-06-07 17:50:36 +08:00
|
|
|
help
|
|
|
|
|
Enable support for the Renesas Interrupt Controller for external
|
|
|
|
|
interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
|
2013-02-18 22:28:34 +08:00
|
|
|
|
2013-02-27 16:15:01 +08:00
|
|
|
config RENESAS_IRQC
|
2020-09-11 18:04:39 +08:00
|
|
|
bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
|
2015-09-28 17:42:37 +08:00
|
|
|
select GENERIC_IRQ_CHIP
|
2013-02-27 16:15:01 +08:00
|
|
|
select IRQ_DOMAIN
|
2019-06-07 17:50:36 +08:00
|
|
|
help
|
|
|
|
|
Enable support for the Renesas Interrupt Controller for external
|
2020-09-11 18:04:39 +08:00
|
|
|
devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
|
2013-02-27 16:15:01 +08:00
|
|
|
|
2019-05-27 20:17:11 +08:00
|
|
|
config RENESAS_RZA1_IRQC
|
2019-06-07 17:50:36 +08:00
|
|
|
bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
|
2019-05-27 20:17:11 +08:00
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
2019-06-07 17:50:36 +08:00
|
|
|
help
|
|
|
|
|
Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
|
|
|
|
|
to 8 external interrupts with configurable sense select.
|
2019-05-27 20:17:11 +08:00
|
|
|
|
2020-09-15 05:43:32 +08:00
|
|
|
config SL28CPLD_INTC
|
|
|
|
|
bool "Kontron sl28cpld IRQ controller"
|
|
|
|
|
depends on MFD_SL28CPLD=y || COMPILE_TEST
|
|
|
|
|
select REGMAP_IRQ
|
|
|
|
|
help
|
|
|
|
|
Interrupt controller driver for the board management controller
|
|
|
|
|
found on the Kontron sl28 CPLD.
|
|
|
|
|
|
2015-02-18 23:13:58 +08:00
|
|
|
config ST_IRQCHIP
|
|
|
|
|
bool
|
|
|
|
|
select REGMAP
|
|
|
|
|
select MFD_SYSCON
|
|
|
|
|
help
|
|
|
|
|
Enables SysCfg Controlled IRQs on STi based platforms.
|
|
|
|
|
|
2022-05-09 11:49:41 +08:00
|
|
|
config SUN4I_INTC
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config SUN6I_R_INTC
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
select IRQ_FASTEOI_HIERARCHY_HANDLERS
|
|
|
|
|
|
|
|
|
|
config SUNXI_NMI_INTC
|
|
|
|
|
bool
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
|
2013-06-26 00:29:57 +08:00
|
|
|
config TB10X_IRQC
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
|
2015-12-22 04:11:23 +08:00
|
|
|
config TS4800_IRQ
|
|
|
|
|
tristate "TS-4800 IRQ controller"
|
|
|
|
|
select IRQ_DOMAIN
|
2016-01-26 06:24:17 +08:00
|
|
|
depends on HAS_IOMEM
|
2016-02-09 18:19:20 +08:00
|
|
|
depends on SOC_IMX51 || COMPILE_TEST
|
2015-12-22 04:11:23 +08:00
|
|
|
help
|
|
|
|
|
Support for the TS-4800 FPGA IRQ controller
|
|
|
|
|
|
2012-11-01 05:04:31 +08:00
|
|
|
config VERSATILE_FPGA_IRQ
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
|
|
|
|
|
config VERSATILE_FPGA_IRQ_NR
|
|
|
|
|
int
|
|
|
|
|
default 4
|
|
|
|
|
depends on VERSATILE_FPGA_IRQ
|
2013-12-01 16:04:57 +08:00
|
|
|
|
|
|
|
|
config XTENSA_MX
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
2017-08-18 16:39:25 +08:00
|
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
2013-12-03 18:27:23 +08:00
|
|
|
|
2016-11-14 20:13:45 +08:00
|
|
|
config XILINX_INTC
|
2021-04-24 02:58:53 +08:00
|
|
|
bool "Xilinx Interrupt Controller IP"
|
2022-06-07 05:39:52 +08:00
|
|
|
depends on OF
|
2016-11-14 20:13:45 +08:00
|
|
|
select IRQ_DOMAIN
|
2021-04-24 02:58:53 +08:00
|
|
|
help
|
|
|
|
|
Support for the Xilinx Interrupt Controller IP core.
|
|
|
|
|
This is used as a primary controller with MicroBlaze and can also
|
|
|
|
|
be used as a secondary chained controller on other platforms.
|
2016-11-14 20:13:45 +08:00
|
|
|
|
2013-12-03 18:27:23 +08:00
|
|
|
config IRQ_CROSSBAR
|
|
|
|
|
bool
|
|
|
|
|
help
|
2014-09-18 11:09:42 +08:00
|
|
|
Support for a CROSSBAR ip that precedes the main interrupt controller.
|
2013-12-03 18:27:23 +08:00
|
|
|
The primary irqchip invokes the crossbar's callback which inturn allocates
|
|
|
|
|
a free irq and configures the IP. Thus the peripheral interrupts are
|
|
|
|
|
routed to one of the free irqchip interrupt lines.
|
2014-07-23 22:40:30 +08:00
|
|
|
|
|
|
|
|
config KEYSTONE_IRQ
|
|
|
|
|
tristate "Keystone 2 IRQ controller IP"
|
|
|
|
|
depends on ARCH_KEYSTONE
|
|
|
|
|
help
|
|
|
|
|
Support for Texas Instruments Keystone 2 IRQ controller IP which
|
|
|
|
|
is part of the Keystone 2 IPC mechanism
|
2014-09-19 05:47:19 +08:00
|
|
|
|
|
|
|
|
config MIPS_GIC
|
|
|
|
|
bool
|
2015-12-08 21:20:28 +08:00
|
|
|
select GENERIC_IRQ_IPI
|
2014-09-19 05:47:19 +08:00
|
|
|
select MIPS_CM
|
2015-05-10 01:30:47 +08:00
|
|
|
|
2015-05-24 23:11:31 +08:00
|
|
|
config INGENIC_IRQ
|
|
|
|
|
bool
|
|
|
|
|
depends on MACH_INGENIC
|
|
|
|
|
default y
|
2015-06-28 03:44:34 +08:00
|
|
|
|
2019-07-25 01:16:08 +08:00
|
|
|
config INGENIC_TCU_IRQ
|
|
|
|
|
bool "Ingenic JZ47xx TCU interrupt controller"
|
|
|
|
|
default MACH_INGENIC
|
|
|
|
|
depends on MIPS || COMPILE_TEST
|
|
|
|
|
select MFD_SYSCON
|
2019-08-13 09:56:02 +08:00
|
|
|
select GENERIC_IRQ_CHIP
|
2019-07-25 01:16:08 +08:00
|
|
|
help
|
|
|
|
|
Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
|
|
|
|
|
JZ47xx SoCs.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2015-08-25 03:04:15 +08:00
|
|
|
config IMX_GPCV2
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
Enables the wakeup IRQs for IMX platforms with GPCv2 block
|
2015-10-13 03:15:34 +08:00
|
|
|
|
|
|
|
|
config IRQ_MXS
|
|
|
|
|
def_bool y if MACH_ASM9260 || ARCH_MXS
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select STMP_DEVICE
|
2016-02-19 21:34:43 +08:00
|
|
|
|
2018-03-22 23:15:24 +08:00
|
|
|
config MSCC_OCELOT_IRQ
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
|
2017-06-21 21:29:14 +08:00
|
|
|
config MVEBU_GICP
|
|
|
|
|
bool
|
|
|
|
|
|
2017-06-21 21:29:15 +08:00
|
|
|
config MVEBU_ICU
|
|
|
|
|
bool
|
|
|
|
|
|
2016-02-19 21:34:43 +08:00
|
|
|
config MVEBU_ODMI
|
|
|
|
|
bool
|
2017-03-14 20:54:12 +08:00
|
|
|
select GENERIC_MSI_IRQ_DOMAIN
|
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 16:57:53 +08:00
|
|
|
|
2016-08-05 22:55:19 +08:00
|
|
|
config MVEBU_PIC
|
|
|
|
|
bool
|
|
|
|
|
|
2018-10-01 22:13:51 +08:00
|
|
|
config MVEBU_SEI
|
|
|
|
|
bool
|
|
|
|
|
|
irqchip: Add support for Layerscape external interrupt lines
The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.
In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.
Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.
Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
2019-11-07 20:21:15 +08:00
|
|
|
config LS_EXTIRQ
|
|
|
|
|
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
|
|
|
|
|
select MFD_SYSCON
|
|
|
|
|
|
2016-03-23 19:08:20 +08:00
|
|
|
config LS_SCFG_MSI
|
|
|
|
|
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
|
|
|
|
|
depends on PCI && PCI_MSI
|
|
|
|
|
|
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 16:57:53 +08:00
|
|
|
config PARTITION_PERCPU
|
|
|
|
|
bool
|
2016-05-20 00:46:18 +08:00
|
|
|
|
2016-09-21 00:00:57 +08:00
|
|
|
config STM32_EXTI
|
|
|
|
|
bool
|
|
|
|
|
select IRQ_DOMAIN
|
2017-11-07 01:03:31 +08:00
|
|
|
select GENERIC_IRQ_CHIP
|
2017-02-03 07:23:59 +08:00
|
|
|
|
|
|
|
|
config QCOM_IRQ_COMBINER
|
|
|
|
|
bool "QCOM IRQ combiner support"
|
|
|
|
|
depends on ARCH_QCOM && ACPI
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Say yes here to add support for the IRQ combiner devices embedded
|
|
|
|
|
in Qualcomm Technologies chips.
|
2017-08-23 09:31:47 +08:00
|
|
|
|
|
|
|
|
config IRQ_UNIPHIER_AIDET
|
|
|
|
|
bool "UniPhier AIDET support" if COMPILE_TEST
|
|
|
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
|
|
|
|
default ARCH_UNIPHIER
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Support for the UniPhier AIDET (ARM Interrupt Detector).
|
2017-10-17 02:04:33 +08:00
|
|
|
|
2017-09-18 21:46:10 +08:00
|
|
|
config MESON_IRQ_GPIO
|
2021-09-02 21:49:13 +08:00
|
|
|
tristate "Meson GPIO Interrupt Multiplexer"
|
|
|
|
|
depends on ARCH_MESON || COMPILE_TEST
|
|
|
|
|
default ARCH_MESON
|
2017-09-18 21:46:10 +08:00
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Support Meson SoC Family GPIO Interrupt Multiplexer
|
|
|
|
|
|
2017-12-29 23:41:46 +08:00
|
|
|
config GOLDFISH_PIC
|
|
|
|
|
bool "Goldfish programmable interrupt controller"
|
|
|
|
|
depends on MIPS && (GOLDFISH || COMPILE_TEST)
|
2021-09-06 00:25:19 +08:00
|
|
|
select GENERIC_IRQ_CHIP
|
2017-12-29 23:41:46 +08:00
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
Say yes here to enable Goldfish interrupt controller driver used
|
|
|
|
|
for Goldfish based virtual platforms.
|
|
|
|
|
|
2018-03-01 01:27:29 +08:00
|
|
|
config QCOM_PDC
|
2021-05-19 05:19:21 +08:00
|
|
|
tristate "QCOM PDC"
|
2018-03-01 01:27:29 +08:00
|
|
|
depends on ARCH_QCOM
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Power Domain Controller driver to manage and configure wakeup
|
|
|
|
|
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
|
|
|
|
|
|
2022-03-08 16:05:34 +08:00
|
|
|
config QCOM_MPM
|
|
|
|
|
tristate "QCOM MPM"
|
|
|
|
|
depends on ARCH_QCOM
|
2022-03-17 21:19:56 +08:00
|
|
|
depends on MAILBOX
|
2022-03-08 16:05:34 +08:00
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
MSM Power Manager driver to manage and configure wakeup
|
|
|
|
|
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
|
|
|
|
|
|
2018-09-16 15:57:14 +08:00
|
|
|
config CSKY_MPINTC
|
2021-02-04 15:46:08 +08:00
|
|
|
bool
|
2018-09-16 15:57:14 +08:00
|
|
|
depends on CSKY
|
|
|
|
|
help
|
|
|
|
|
Say yes here to enable C-SKY SMP interrupt controller driver used
|
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|
for C-SKY SMP system.
|
2020-01-29 10:25:14 +08:00
|
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In fact it's not mmio map in hardware and it uses ld/st to visit the
|
2018-09-16 15:57:14 +08:00
|
|
|
controller's register inside CPU.
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|
2018-09-16 15:57:14 +08:00
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config CSKY_APB_INTC
|
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|
bool "C-SKY APB Interrupt Controller"
|
|
|
|
|
depends on CSKY
|
|
|
|
|
help
|
|
|
|
|
Say yes here to enable C-SKY APB interrupt controller driver used
|
2020-01-29 10:25:14 +08:00
|
|
|
by C-SKY single core SOC system. It uses mmio map apb-bus to visit
|
2018-09-16 15:57:14 +08:00
|
|
|
the controller's register.
|
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|
2018-12-17 22:01:20 +08:00
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|
|
config IMX_IRQSTEER
|
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|
|
bool "i.MX IRQSTEER support"
|
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|
|
|
depends on ARCH_MXC || COMPILE_TEST
|
|
|
|
|
default ARCH_MXC
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
|
|
|
|
|
|
2020-01-17 14:10:10 +08:00
|
|
|
config IMX_INTMUX
|
2021-02-08 22:56:05 +08:00
|
|
|
bool "i.MX INTMUX support" if COMPILE_TEST
|
|
|
|
|
default y if ARCH_MXC
|
2020-01-17 14:10:10 +08:00
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
Support for the i.MX INTMUX interrupt multiplexer.
|
|
|
|
|
|
2019-02-01 14:22:35 +08:00
|
|
|
config LS1X_IRQ
|
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|
|
bool "Loongson-1 Interrupt Controller"
|
|
|
|
|
depends on MACH_LOONGSON32
|
|
|
|
|
default y
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
help
|
|
|
|
|
Support for the Loongson-1 platform Interrupt Controller.
|
|
|
|
|
|
2019-04-30 18:12:25 +08:00
|
|
|
config TI_SCI_INTR_IRQCHIP
|
|
|
|
|
bool
|
|
|
|
|
depends on TI_SCI_PROTOCOL
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
This enables the irqchip driver support for K3 Interrupt router
|
|
|
|
|
over TI System Control Interface available on some new TI's SoCs.
|
|
|
|
|
If you wish to use interrupt router irq resources managed by the
|
|
|
|
|
TI System Controller, say Y here. Otherwise, say N.
|
|
|
|
|
|
2019-04-30 18:12:27 +08:00
|
|
|
config TI_SCI_INTA_IRQCHIP
|
|
|
|
|
bool
|
|
|
|
|
depends on TI_SCI_PROTOCOL
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
2019-04-30 18:12:29 +08:00
|
|
|
select TI_SCI_INTA_MSI_DOMAIN
|
2019-04-30 18:12:27 +08:00
|
|
|
help
|
|
|
|
|
This enables the irqchip driver support for K3 Interrupt aggregator
|
|
|
|
|
over TI System Control Interface available on some new TI's SoCs.
|
|
|
|
|
If you wish to use interrupt aggregator irq resources managed by the
|
|
|
|
|
TI System Controller, say Y here. Otherwise, say N.
|
|
|
|
|
|
2020-09-17 00:36:03 +08:00
|
|
|
config TI_PRUSS_INTC
|
2021-01-09 00:29:01 +08:00
|
|
|
tristate
|
|
|
|
|
depends on TI_PRUSS
|
|
|
|
|
default TI_PRUSS
|
2020-09-17 00:36:03 +08:00
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
help
|
|
|
|
|
This enables support for the PRU-ICSS Local Interrupt Controller
|
|
|
|
|
present within a PRU-ICSS subsystem present on various TI SoCs.
|
|
|
|
|
The PRUSS INTC enables various interrupts to be routed to multiple
|
|
|
|
|
different processors within the SoC.
|
|
|
|
|
|
2020-06-01 17:15:40 +08:00
|
|
|
config RISCV_INTC
|
|
|
|
|
bool "RISC-V Local Interrupt Controller"
|
|
|
|
|
depends on RISCV
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
This enables support for the per-HART local interrupt controller
|
|
|
|
|
found in standard RISC-V systems. The per-HART local interrupt
|
|
|
|
|
controller handles timer interrupts, software interrupts, and
|
|
|
|
|
hardware interrupts. Without a per-HART local interrupt controller,
|
|
|
|
|
a RISC-V system will be unable to handle any interrupts.
|
|
|
|
|
|
|
|
|
|
If you don't know what to do here, say Y.
|
|
|
|
|
|
2018-07-26 22:27:00 +08:00
|
|
|
config SIFIVE_PLIC
|
|
|
|
|
bool "SiFive Platform-Level Interrupt Controller"
|
|
|
|
|
depends on RISCV
|
2019-12-10 19:11:11 +08:00
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
2018-07-26 22:27:00 +08:00
|
|
|
help
|
|
|
|
|
This enables support for the PLIC chip found in SiFive (and
|
|
|
|
|
potentially other) RISC-V systems. The PLIC controls devices
|
|
|
|
|
interrupts and connects them to each core's local interrupt
|
|
|
|
|
controller. Aside from timer and software interrupts, all other
|
|
|
|
|
interrupt sources are subordinate to the PLIC.
|
|
|
|
|
|
|
|
|
|
If you don't know what to do here, say Y.
|
2019-10-02 22:44:52 +08:00
|
|
|
|
2019-12-25 05:11:07 +08:00
|
|
|
config EXYNOS_IRQ_COMBINER
|
|
|
|
|
bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
|
|
|
|
|
depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
|
|
|
|
|
help
|
|
|
|
|
Say yes here to add support for the IRQ combiner devices embedded
|
|
|
|
|
in Samsung Exynos chips.
|
|
|
|
|
|
2020-03-25 11:54:54 +08:00
|
|
|
config LOONGSON_LIOINTC
|
|
|
|
|
bool "Loongson Local I/O Interrupt Controller"
|
|
|
|
|
depends on MACH_LOONGSON64
|
|
|
|
|
default y
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
help
|
|
|
|
|
Support for the Loongson Local I/O Interrupt Controller.
|
|
|
|
|
|
2020-03-25 11:54:57 +08:00
|
|
|
config LOONGSON_HTPIC
|
|
|
|
|
bool "Loongson3 HyperTransport PIC Controller"
|
2022-05-31 18:04:10 +08:00
|
|
|
depends on MACH_LOONGSON64 && MIPS
|
2020-03-25 11:54:57 +08:00
|
|
|
default y
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
help
|
|
|
|
|
Support for the Loongson-3 HyperTransport PIC Controller.
|
|
|
|
|
|
2020-05-28 23:27:49 +08:00
|
|
|
config LOONGSON_HTVEC
|
2022-05-31 18:04:10 +08:00
|
|
|
bool "Loongson HyperTransport Interrupt Vector Controller"
|
2020-06-01 15:45:27 +08:00
|
|
|
depends on MACH_LOONGSON64
|
2020-05-28 23:27:49 +08:00
|
|
|
default MACH_LOONGSON64
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
2022-05-31 18:04:10 +08:00
|
|
|
Support for the Loongson HyperTransport Interrupt Vector Controller.
|
2020-05-28 23:27:49 +08:00
|
|
|
|
2020-05-28 23:27:51 +08:00
|
|
|
config LOONGSON_PCH_PIC
|
|
|
|
|
bool "Loongson PCH PIC Controller"
|
|
|
|
|
depends on MACH_LOONGSON64 || COMPILE_TEST
|
|
|
|
|
default MACH_LOONGSON64
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
select IRQ_FASTEOI_HIERARCHY_HANDLERS
|
|
|
|
|
help
|
|
|
|
|
Support for the Loongson PCH PIC Controller.
|
|
|
|
|
|
2020-05-28 23:27:53 +08:00
|
|
|
config LOONGSON_PCH_MSI
|
2020-05-30 20:11:12 +08:00
|
|
|
bool "Loongson PCH MSI Controller"
|
2020-05-28 23:27:53 +08:00
|
|
|
depends on MACH_LOONGSON64 || COMPILE_TEST
|
|
|
|
|
depends on PCI
|
|
|
|
|
default MACH_LOONGSON64
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
select PCI_MSI
|
|
|
|
|
help
|
|
|
|
|
Support for the Loongson PCH MSI Controller.
|
|
|
|
|
|
2020-09-02 14:33:43 +08:00
|
|
|
config MST_IRQ
|
|
|
|
|
bool "MStar Interrupt Controller"
|
2020-10-14 21:17:03 +08:00
|
|
|
depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
|
2020-09-02 14:33:43 +08:00
|
|
|
default ARCH_MEDIATEK
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Support MStar Interrupt Controller.
|
|
|
|
|
|
2021-04-06 20:09:17 +08:00
|
|
|
config WPCM450_AIC
|
|
|
|
|
bool "Nuvoton WPCM450 Advanced Interrupt Controller"
|
2021-04-08 15:56:27 +08:00
|
|
|
depends on ARCH_WPCM450
|
2021-04-06 20:09:17 +08:00
|
|
|
help
|
|
|
|
|
Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
|
|
|
|
|
|
2021-04-22 22:53:28 +08:00
|
|
|
config IRQ_IDT3243X
|
|
|
|
|
bool
|
|
|
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
|
2021-01-21 07:55:15 +08:00
|
|
|
config APPLE_AIC
|
|
|
|
|
bool "Apple Interrupt Controller (AIC)"
|
|
|
|
|
depends on ARM64
|
2021-04-13 20:21:58 +08:00
|
|
|
depends on ARCH_APPLE || COMPILE_TEST
|
2021-01-21 07:55:15 +08:00
|
|
|
help
|
|
|
|
|
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
|
|
|
|
|
such as the M1.
|
|
|
|
|
|
2021-09-27 14:36:57 +08:00
|
|
|
config MCHP_EIC
|
|
|
|
|
bool "Microchip External Interrupt Controller"
|
|
|
|
|
depends on ARCH_AT91 || COMPILE_TEST
|
|
|
|
|
select IRQ_DOMAIN
|
|
|
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
|
|
|
help
|
|
|
|
|
Support for Microchip External Interrupt Controller.
|
|
|
|
|
|
2019-10-02 22:44:52 +08:00
|
|
|
endmenu
|