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linux-sg2042/drivers/iio/adc/adi-axi-adc.c

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iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog Devices Generic AXI ADC IP core
* Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
*
* Copyright 2012-2020 Analog Devices Inc.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/buffer-dmaengine.h>
#include <linux/fpga/adi-axi-common.h>
#include <linux/iio/adc/adi-axi-adc.h>
iio: adc: adi-axi-adc: Drop false marking for kernel-doc This comment block isn't in kernel-doc format so drop the /** marking. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20210314164655.408461-7-jic23@kernel.org
2021-03-15 00:46:53 +08:00
/*
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
* Register definitions:
* https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
*/
/* ADC controls */
#define ADI_AXI_REG_RSTN 0x0040
#define ADI_AXI_REG_RSTN_CE_N BIT(2)
#define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
#define ADI_AXI_REG_RSTN_RSTN BIT(0)
/* ADC Channel controls */
#define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
#define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
#define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
#define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
#define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
#define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
#define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
#define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
#define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
#define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
#define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
(ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
ADI_AXI_REG_CHAN_CTRL_ENABLE)
struct adi_axi_adc_core_info {
unsigned int version;
};
struct adi_axi_adc_state {
struct mutex lock;
struct adi_axi_adc_client *client;
void __iomem *regs;
};
struct adi_axi_adc_client {
struct list_head entry;
struct adi_axi_adc_conv conv;
struct adi_axi_adc_state *state;
struct device *dev;
const struct adi_axi_adc_core_info *info;
};
static LIST_HEAD(registered_clients);
static DEFINE_MUTEX(registered_clients_lock);
static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
{
return container_of(conv, struct adi_axi_adc_client, conv);
}
void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
{
struct adi_axi_adc_client *cl = conv_to_client(conv);
iio: core: Fix IIO_ALIGN and rename as it was not sufficiently large Discussion of the series: https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/ mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm platforms out their with non coherent DMA and larger cache lines at at higher levels of their cache hierarchy. Rename the define to make it's purpose more explicit. It will be used much more widely going forwards (to replace incorrect ____cacheline_aligned markings. Note this patch will greatly reduce the padding on some architectures that have smaller requirements for DMA safe buffers. The history of changing values of ARCH_KMALLOC_MINALIGN via ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this as fixing a particular patch from that route as it's not clear what to tag. Most recently a change to bring them back inline was reverted because of some Qualcomm Kryo cores with an L2 cache with 128-byte lines sitting above the point of coherency. c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" That reverts: 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which refers to the change originally being motivated by Thunder x1 performance rather than correctness. Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-2-jic23@kernel.org
2022-05-09 01:55:41 +08:00
return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
IIO_DMA_MINALIGN);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
}
iio: adc: adi-axi: Move exported symbols into IIO_ADI_AXI namespace. Avoid unnecessary pollution of the global symbol namespace by moving library functions in to a specific namespace and import that into the drivers that make use of the functions. For more info: https://lwn.net/Articles/760045/ Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Nuno Sá <nuno.sa@analog.com> Reviewed-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220220173701.502331-5-jic23@kernel.org
2022-02-21 01:37:00 +08:00
EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
static void adi_axi_adc_write(struct adi_axi_adc_state *st,
unsigned int reg,
unsigned int val)
{
iowrite32(val, st->regs + reg);
}
static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
unsigned int reg)
{
return ioread32(st->regs + reg);
}
static int adi_axi_adc_config_dma_buffer(struct device *dev,
struct iio_dev *indio_dev)
{
const char *dma_name;
if (!device_property_present(dev, "dmas"))
return 0;
if (device_property_read_string(dev, "dma-names", &dma_name))
dma_name = "rx";
iio: buffer-dma,adi-axi-adc: introduce devm_iio_dmaengine_buffer_setup() This change does a conversion of the devm_iio_dmaengine_buffer_alloc() to devm_iio_dmaengine_buffer_setup(). This will allocate an IIO DMA buffer and attach it to the IIO device, similar to devm_iio_triggered_buffer_setup() (though the underlying code is different, the final logic is the same). Since the only user of the devm_iio_dmaengine_buffer_alloc() was the adi-axi-adc driver, this change does the replacement in a single go in the driver. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210215104043.91251-7-alexandru.ardelean@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-02-15 18:40:25 +08:00
return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
indio_dev, dma_name);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
}
static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
if (!conv->read_raw)
return -EOPNOTSUPP;
return conv->read_raw(conv, chan, val, val2, mask);
}
static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
if (!conv->write_raw)
return -EOPNOTSUPP;
return conv->write_raw(conv, chan, val, val2, mask);
}
iio: adc: ad9467: fix scale setting [ Upstream commit b73f08bb7fe5a0901646ca5ceaa1e7a2d5ee6293 ] When reading in_voltage_scale we can get something like: root@analog:/sys/bus/iio/devices/iio:device2# cat in_voltage_scale 0.038146 However, when reading the available options: root@analog:/sys/bus/iio/devices/iio:device2# cat in_voltage_scale_available 2000.000000 2100.000006 2200.000007 2300.000008 2400.000009 2500.000010 which does not make sense. Moreover, when trying to set a new scale we get an error because there's no call to __ad9467_get_scale() to give us values as given when reading in_voltage_scale. Fix it by computing the available scales during probe and properly pass the list when .read_available() is called. While at it, change to use .read_available() from iio_info. Also note that to properly fix this, adi-axi-adc.c has to be changed accordingly. Fixes: ad6797120238 ("iio: adc: ad9467: add support AD9467 ADC") Signed-off-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20231207-iio-backend-prep-v2-4-a4a33bc4d70e@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-12-07 20:39:27 +08:00
static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
const int **vals, int *type, int *length,
long mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
if (!conv->read_avail)
return -EOPNOTSUPP;
return conv->read_avail(conv, chan, vals, type, length, mask);
}
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *scan_mask)
{
struct adi_axi_adc_state *st = iio_priv(indio_dev);
struct adi_axi_adc_conv *conv = &st->client->conv;
unsigned int i, ctrl;
for (i = 0; i < conv->chip_info->num_channels; i++) {
ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
if (test_bit(i, scan_mask))
ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
else
ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
}
return 0;
}
static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
size_t sizeof_priv)
{
struct adi_axi_adc_client *cl;
size_t alloc_size;
iio: core: Fix IIO_ALIGN and rename as it was not sufficiently large Discussion of the series: https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/ mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm platforms out their with non coherent DMA and larger cache lines at at higher levels of their cache hierarchy. Rename the define to make it's purpose more explicit. It will be used much more widely going forwards (to replace incorrect ____cacheline_aligned markings. Note this patch will greatly reduce the padding on some architectures that have smaller requirements for DMA safe buffers. The history of changing values of ARCH_KMALLOC_MINALIGN via ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this as fixing a particular patch from that route as it's not clear what to tag. Most recently a change to bring them back inline was reverted because of some Qualcomm Kryo cores with an L2 cache with 128-byte lines sitting above the point of coherency. c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" That reverts: 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which refers to the change originally being motivated by Thunder x1 performance rather than correctness. Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-2-jic23@kernel.org
2022-05-09 01:55:41 +08:00
alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
if (sizeof_priv)
iio: core: Fix IIO_ALIGN and rename as it was not sufficiently large Discussion of the series: https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/ mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm platforms out their with non coherent DMA and larger cache lines at at higher levels of their cache hierarchy. Rename the define to make it's purpose more explicit. It will be used much more widely going forwards (to replace incorrect ____cacheline_aligned markings. Note this patch will greatly reduce the padding on some architectures that have smaller requirements for DMA safe buffers. The history of changing values of ARCH_KMALLOC_MINALIGN via ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this as fixing a particular patch from that route as it's not clear what to tag. Most recently a change to bring them back inline was reverted because of some Qualcomm Kryo cores with an L2 cache with 128-byte lines sitting above the point of coherency. c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" That reverts: 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which refers to the change originally being motivated by Thunder x1 performance rather than correctness. Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-2-jic23@kernel.org
2022-05-09 01:55:41 +08:00
alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
cl = kzalloc(alloc_size, GFP_KERNEL);
if (!cl)
return ERR_PTR(-ENOMEM);
mutex_lock(&registered_clients_lock);
cl->dev = get_device(dev);
list_add_tail(&cl->entry, &registered_clients);
mutex_unlock(&registered_clients_lock);
return &cl->conv;
}
static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
{
struct adi_axi_adc_client *cl = conv_to_client(conv);
mutex_lock(&registered_clients_lock);
list_del(&cl->entry);
put_device(cl->dev);
mutex_unlock(&registered_clients_lock);
kfree(cl);
}
iio: adc: adi-axi-adc: simplify devm_adi_axi_adc_conv_register() Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/1617881896-3164-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-08 19:38:10 +08:00
static void devm_adi_axi_adc_conv_release(void *conv)
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
{
iio: adc: adi-axi-adc: simplify devm_adi_axi_adc_conv_register() Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/1617881896-3164-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-08 19:38:10 +08:00
adi_axi_adc_conv_unregister(conv);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
}
struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
size_t sizeof_priv)
{
iio: adc: adi-axi-adc: simplify devm_adi_axi_adc_conv_register() Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/1617881896-3164-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-08 19:38:10 +08:00
struct adi_axi_adc_conv *conv;
int ret;
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
conv = adi_axi_adc_conv_register(dev, sizeof_priv);
iio: adc: adi-axi-adc: simplify devm_adi_axi_adc_conv_register() Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/1617881896-3164-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-08 19:38:10 +08:00
if (IS_ERR(conv))
return conv;
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
iio: adc: adi-axi-adc: simplify devm_adi_axi_adc_conv_register() Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Alexandru Ardelean <ardeleanalex@gmail.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/1617881896-3164-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-08 19:38:10 +08:00
ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
conv);
if (ret)
return ERR_PTR(ret);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
return conv;
}
iio: adc: adi-axi: Move exported symbols into IIO_ADI_AXI namespace. Avoid unnecessary pollution of the global symbol namespace by moving library functions in to a specific namespace and import that into the drivers that make use of the functions. For more info: https://lwn.net/Articles/760045/ Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Nuno Sá <nuno.sa@analog.com> Reviewed-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220220173701.502331-5-jic23@kernel.org
2022-02-21 01:37:00 +08:00
EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
static const struct iio_info adi_axi_adc_info = {
.read_raw = &adi_axi_adc_read_raw,
.write_raw = &adi_axi_adc_write_raw,
.update_scan_mode = &adi_axi_adc_update_scan_mode,
iio: adc: ad9467: fix scale setting [ Upstream commit b73f08bb7fe5a0901646ca5ceaa1e7a2d5ee6293 ] When reading in_voltage_scale we can get something like: root@analog:/sys/bus/iio/devices/iio:device2# cat in_voltage_scale 0.038146 However, when reading the available options: root@analog:/sys/bus/iio/devices/iio:device2# cat in_voltage_scale_available 2000.000000 2100.000006 2200.000007 2300.000008 2400.000009 2500.000010 which does not make sense. Moreover, when trying to set a new scale we get an error because there's no call to __ad9467_get_scale() to give us values as given when reading in_voltage_scale. Fix it by computing the available scales during probe and properly pass the list when .read_available() is called. While at it, change to use .read_available() from iio_info. Also note that to properly fix this, adi-axi-adc.c has to be changed accordingly. Fixes: ad6797120238 ("iio: adc: ad9467: add support AD9467 ADC") Signed-off-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20231207-iio-backend-prep-v2-4-a4a33bc4d70e@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-12-07 20:39:27 +08:00
.read_avail = &adi_axi_adc_read_avail,
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
};
static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
.version = ADI_AXI_PCORE_VER(10, 0, 'a'),
};
static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
{
const struct adi_axi_adc_core_info *info;
struct adi_axi_adc_client *cl;
struct device_node *cln;
info = of_device_get_match_data(dev);
if (!info)
return ERR_PTR(-ENODEV);
cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
if (!cln) {
dev_err(dev, "No 'adi,adc-dev' node defined\n");
return ERR_PTR(-ENODEV);
}
mutex_lock(&registered_clients_lock);
list_for_each_entry(cl, &registered_clients, entry) {
if (!cl->dev)
continue;
if (cl->dev->of_node != cln)
continue;
iio: adc: adi-axi-adc: Fix object reference counting When looking for a registered client to attach with, the wrong reference counters are being grabbed. The idea is to increment the module and device counters of the client device and not the counters of the axi device being probed. Fixes: ef04070692a2 (iio: adc: adi-axi-adc: add support for AXI ADC IP core) Signed-off-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-07-01 20:04:41 +08:00
if (!try_module_get(cl->dev->driver->owner)) {
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
mutex_unlock(&registered_clients_lock);
iio: adc: adi-axi-adc: Fix refcount leak in adi_axi_adc_attach_client of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak. Fixes: ef04070692a2 ("iio: adc: adi-axi-adc: add support for AXI ADC IP core") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220524074517.45268-1-linmq006@gmail.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-05-24 15:45:17 +08:00
of_node_put(cln);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
return ERR_PTR(-ENODEV);
}
iio: adc: adi-axi-adc: Fix object reference counting When looking for a registered client to attach with, the wrong reference counters are being grabbed. The idea is to increment the module and device counters of the client device and not the counters of the axi device being probed. Fixes: ef04070692a2 (iio: adc: adi-axi-adc: add support for AXI ADC IP core) Signed-off-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-07-01 20:04:41 +08:00
get_device(cl->dev);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
cl->info = info;
mutex_unlock(&registered_clients_lock);
iio: adc: adi-axi-adc: Fix refcount leak in adi_axi_adc_attach_client of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak. Fixes: ef04070692a2 ("iio: adc: adi-axi-adc: add support for AXI ADC IP core") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220524074517.45268-1-linmq006@gmail.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-05-24 15:45:17 +08:00
of_node_put(cln);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
return cl;
}
mutex_unlock(&registered_clients_lock);
iio: adc: adi-axi-adc: Fix refcount leak in adi_axi_adc_attach_client of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak. Fixes: ef04070692a2 ("iio: adc: adi-axi-adc: add support for AXI ADC IP core") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220524074517.45268-1-linmq006@gmail.com Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2022-05-24 15:45:17 +08:00
of_node_put(cln);
iio: adc: adi-axi-adc: add support for AXI ADC IP core This change adds support for the Analog Devices Generic AXI ADC IP core. The IP core is used for interfacing with analog-to-digital (ADC) converters that require either a high-speed serial interface (JESD204B/C) or a source synchronous parallel interface (LVDS/CMOS). Usually, some other interface type (i.e SPI) is used as a control interface for the actual ADC, while the IP core (controlled via this driver), will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. Because of this, the AXI ADC driver needs the other SPI-ADC driver to register with it. The SPI-ADC needs to be register via the SPI framework, while the AXI ADC registers as a platform driver. The two cannot be ordered in a hierarchy as both drivers have their own registers, and trying to organize this [in a hierarchy becomes] problematic when trying to map memory/registers. There are some modes where the AXI ADC can operate as standalone ADC, but those will be implemented at a later point in time. DocLink: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-24 21:46:33 +08:00
return ERR_PTR(-EPROBE_DEFER);
}
static int adi_axi_adc_setup_channels(struct device *dev,
struct adi_axi_adc_state *st)
{
struct adi_axi_adc_conv *conv = &st->client->conv;
int i, ret;
if (conv->preenable_setup) {
ret = conv->preenable_setup(conv);
if (ret)
return ret;
}
for (i = 0; i < conv->chip_info->num_channels; i++) {
adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
}
return 0;
}
static void axi_adc_reset(struct adi_axi_adc_state *st)
{
adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
mdelay(10);
adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
mdelay(10);
adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
}
static void adi_axi_adc_cleanup(void *data)
{
struct adi_axi_adc_client *cl = data;
put_device(cl->dev);
module_put(cl->dev->driver->owner);
}
static int adi_axi_adc_probe(struct platform_device *pdev)
{
struct adi_axi_adc_conv *conv;
struct iio_dev *indio_dev;
struct adi_axi_adc_client *cl;
struct adi_axi_adc_state *st;
unsigned int ver;
int ret;
cl = adi_axi_adc_attach_client(&pdev->dev);
if (IS_ERR(cl))
return PTR_ERR(cl);
ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
if (ret)
return ret;
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
if (indio_dev == NULL)
return -ENOMEM;
st = iio_priv(indio_dev);
st->client = cl;
cl->state = st;
mutex_init(&st->lock);
st->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(st->regs))
return PTR_ERR(st->regs);
conv = &st->client->conv;
axi_adc_reset(st);
ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
if (cl->info->version > ver) {
dev_err(&pdev->dev,
"IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
ADI_AXI_PCORE_VER_MINOR(cl->info->version),
ADI_AXI_PCORE_VER_PATCH(cl->info->version),
ADI_AXI_PCORE_VER_MAJOR(ver),
ADI_AXI_PCORE_VER_MINOR(ver),
ADI_AXI_PCORE_VER_PATCH(ver));
return -ENODEV;
}
indio_dev->info = &adi_axi_adc_info;
indio_dev->name = "adi-axi-adc";
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = conv->chip_info->num_channels;
indio_dev->channels = conv->chip_info->channels;
ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
if (ret)
return ret;
ret = adi_axi_adc_setup_channels(&pdev->dev, st);
if (ret)
return ret;
ret = devm_iio_device_register(&pdev->dev, indio_dev);
if (ret)
return ret;
dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
ADI_AXI_PCORE_VER_MAJOR(ver),
ADI_AXI_PCORE_VER_MINOR(ver),
ADI_AXI_PCORE_VER_PATCH(ver));
return 0;
}
/* Match table for of_platform binding */
static const struct of_device_id adi_axi_adc_of_match[] = {
{ .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
{ /* end of list */ }
};
MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
static struct platform_driver adi_axi_adc_driver = {
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = adi_axi_adc_of_match,
},
.probe = adi_axi_adc_probe,
};
module_platform_driver(adi_axi_adc_driver);
MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
MODULE_LICENSE("GPL v2");